diff options
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 30 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-NEON-thumb.txt | 9 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-VFP-thumb.txt | 9 |
3 files changed, 35 insertions, 13 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 6aaf4c0..31941c1 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -754,21 +754,25 @@ DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return result; } - MI.clear(); - result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); - if (result != MCDisassembler::Fail) { - Size = 4; - UpdateThumbVFPPredicate(MI); - return result; + if (fieldFromInstruction(insn32, 28, 4) == 0xE) { + MI.clear(); + result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI); + if (result != MCDisassembler::Fail) { + Size = 4; + UpdateThumbVFPPredicate(MI); + return result; + } } - MI.clear(); - result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, - this, STI); - if (result != MCDisassembler::Fail) { - Size = 4; - Check(result, AddThumbPredicate(MI)); - return result; + if (fieldFromInstruction(insn32, 28, 4) == 0xE) { + MI.clear(); + result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address, + this, STI); + if (result != MCDisassembler::Fail) { + Size = 4; + Check(result, AddThumbPredicate(MI)); + return result; + } } if (fieldFromInstruction(insn32, 24, 8) == 0xF9) { diff --git a/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt new file mode 100644 index 0000000..a191d9e --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-NEON-thumb.txt @@ -0,0 +1,9 @@ +# VMOV/VDUP between scalar and core registers with invalid predicate bits (pred != 0b1110) + +# VMOV +# RUN: echo "0x00 0xde 0x10 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VDUP +# RUN: echo "0xff 0xde 0xf0 0xfb" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt new file mode 100644 index 0000000..7a4ddaa --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-VFP-thumb.txt @@ -0,0 +1,9 @@ +# VFP instructions with invalid predicate bits (pred != 0b1110) + +# VABS +# RUN: echo "0x40 0xde 0x00 0x0a" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# VMLA +# RUN: echo "0xf0 0xde 0xe0 0x0b" | llvm-mc -triple thumbv7 -disassemble 2>&1 | FileCheck %s + +# CHECK: invalid instruction encoding |