diff options
| -rw-r--r-- | lib/Target/R600/AMDGPUISelLowering.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/R600/fabs.ll | 36 |
2 files changed, 35 insertions, 2 deletions
diff --git a/lib/Target/R600/AMDGPUISelLowering.cpp b/lib/Target/R600/AMDGPUISelLowering.cpp index f2a6aab..c4d75ff 100644 --- a/lib/Target/R600/AMDGPUISelLowering.cpp +++ b/lib/Target/R600/AMDGPUISelLowering.cpp @@ -179,6 +179,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : for (unsigned int x = 0; x < NumFloatTypes; ++x) { MVT::SimpleValueType VT = FloatTypes[x]; + setOperationAction(ISD::FABS, VT, Expand); setOperationAction(ISD::FADD, VT, Expand); setOperationAction(ISD::FDIV, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll index 23ab468..a5f5df9 100644 --- a/test/CodeGen/R600/fabs.ll +++ b/test/CodeGen/R600/fabs.ll @@ -5,10 +5,10 @@ ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF)) ; unless isFabsFree returns true -; R600-CHECK: @fabs_free +; R600-CHECK-LABEL: @fabs_free ; R600-CHECK-NOT: AND ; R600-CHECK: |PV.{{[XYZW]}}| -; SI-CHECK: @fabs_free +; SI-CHECK-LABEL: @fabs_free ; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 define void @fabs_free(float addrspace(1)* %out, i32 %in) { @@ -19,4 +19,36 @@ entry: ret void } +; R600-CHECK-LABEL: @fabs_v2 +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; SI-CHECK-LABEL: @fabs_v2 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +define void @fabs_v2(<2 x float> addrspace(1)* %out, <2 x float> %in) { +entry: + %0 = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in) + store <2 x float> %0, <2 x float> addrspace(1)* %out + ret void +} + +; R600-CHECK-LABEL: @fabs_v4 +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; R600-CHECK: |{{(PV|T[0-9])\.[XYZW]}}| +; SI-CHECK-LABEL: @fabs_v4 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +; SI-CHECK: V_ADD_F32_e64 v{{[0-9]}}, s{{[0-9]}}, 0, 1, 0, 0, 0 +define void @fabs_v4(<4 x float> addrspace(1)* %out, <4 x float> %in) { +entry: + %0 = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in) + store <4 x float> %0, <4 x float> addrspace(1)* %out + ret void +} + declare float @fabs(float ) readnone +declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone +declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone |