diff options
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/ARM/inlineasm3.ll | 12 |
2 files changed, 15 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 903efd7..46b4299 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -7596,6 +7596,9 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const { case 'x': return C_RegisterClass; case 't': return C_RegisterClass; case 'j': return C_Other; // Constant for movw. + // An address with a single base register. Due to the way we + // currently handle addresses it is the same as an 'r' memory constraint. + case 'Q': return C_Memory; } } else if (Constraint.size() == 2) { switch (Constraint[0]) { diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 853585d..cb5243c 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -98,3 +98,15 @@ entry: %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind ret i32 %0 } + +; Radar 9866494 + +define void @t10(i8* %f, i32 %g) nounwind { +entry: +; CHECK: t10 +; CHECK: str r1, [r0] + %f.addr = alloca i8*, align 4 + store i8* %f, i8** %f.addr, align 4 + call void asm "str $1, $0", "=*Q,r"(i8** %f.addr, i32 %g) nounwind + ret void +} |