diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 8 | ||||
| -rw-r--r-- | test/CodeGen/Mips/fcopysign.ll | 9 | ||||
| -rw-r--r-- | test/CodeGen/Mips/mips64imm.ll | 8 |
4 files changed, 21 insertions, 6 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index b3fbbae..2eea4cf 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -225,6 +225,8 @@ def : Pat<(i64 immSExt16:$in), (DADDiu ZERO_64, imm:$in)>; def : Pat<(i64 immZExt16:$in), (ORi64 ZERO_64, imm:$in)>; +def : Pat<(i64 immLUiOpnd:$in), + (LUi64 (HI16 imm:$in))>; // 32-bit immediates def : Pat<(i64 immSExt32:$imm), diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index bcaa8c3..5260943 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -219,6 +219,12 @@ def immZExt16 : PatLeaf<(imm), [{ return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); }], LO16>; +// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). +def immLUiOpnd : PatLeaf<(imm), [{ + int64_t Val = N->getSExtValue(); + return isInt<32>(Val) && !(Val & 0xffff); +}]>; + // shamt field must fit in 5 bits. def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; @@ -933,6 +939,8 @@ def : Pat<(i32 immSExt16:$in), (ADDiu ZERO, imm:$in)>; def : Pat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; +def : Pat<(i32 immLUiOpnd:$in), + (LUi (HI16 imm:$in))>; // Arbitrary immediates def : Pat<(i32 imm:$imm), diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll index 950c437..e494fe2 100644 --- a/test/CodeGen/Mips/fcopysign.ll +++ b/test/CodeGen/Mips/fcopysign.ll @@ -5,9 +5,8 @@ define double @func0(double %d0, double %d1) nounwind readnone { entry: ; MIPS32-EL: func0: -; MIPS32-EL: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EL: mfc1 $[[HI0:[0-9]+]], $f15 +; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EL: and $[[AND1:[0-9]+]], $[[HI0]], $[[MSK1]] ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 @@ -18,9 +17,8 @@ entry: ; MIPS32-EL: mtc1 $[[LO0]], $f0 ; MIPS32-EL: mtc1 $[[OR]], $f1 ; -; MIPS32-EB: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EB: mfc1 $[[HI1:[0-9]+]], $f14 +; MIPS32-EB: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] ; MIPS32-EB: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 @@ -46,9 +44,8 @@ declare double @copysign(double, double) nounwind readnone define float @func1(float %f0, float %f1) nounwind readnone { entry: ; MIPS32-EL: func1: -; MIPS32-EL: lui $[[T1:[0-9]+]], 32768 -; MIPS32-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 ; MIPS32-EL: mfc1 $[[ARG1:[0-9]+]], $f14 +; MIPS32-EL: lui $[[MSK1:[0-9]+]], 32768 ; MIPS32-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]] ; MIPS32-EL: lui $[[T0:[0-9]+]], 32767 ; MIPS32-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 diff --git a/test/CodeGen/Mips/mips64imm.ll b/test/CodeGen/Mips/mips64imm.ll index dca656c..8cec536 100644 --- a/test/CodeGen/Mips/mips64imm.ll +++ b/test/CodeGen/Mips/mips64imm.ll @@ -1,5 +1,13 @@ ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s +define i32 @foo1() nounwind readnone { +entry: +; CHECK: foo1 +; CHECK: lui ${{[0-9]+}}, 4660 +; CHECK-NOT: ori + ret i32 305397760 +} + define i64 @foo3() nounwind readnone { entry: ; CHECK: foo3 |