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-rw-r--r--lib/CodeGen/RegisterCoalescer.cpp33
-rw-r--r--test/CodeGen/ARM/coalesce-subregs.ll2
2 files changed, 11 insertions, 24 deletions
diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp
index 7d69176..57aa6f9 100644
--- a/lib/CodeGen/RegisterCoalescer.cpp
+++ b/lib/CodeGen/RegisterCoalescer.cpp
@@ -2001,30 +2001,17 @@ void RegisterCoalescer::joinAllIntervals() {
DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
assert(WorkList.empty() && "Old data still around.");
- if (Loops->empty()) {
- // If there are no loops in the function, join intervals in function order.
- for (MachineFunction::iterator I = MF->begin(), E = MF->end();
- I != E; ++I)
- copyCoalesceInMBB(I);
- } else {
- // Otherwise, join intervals in inner loops before other intervals.
- // Unfortunately we can't just iterate over loop hierarchy here because
- // there may be more MBB's than BB's. Collect MBB's for sorting.
-
- // Join intervals in the function prolog first. We want to join physical
- // registers with virtual registers before the intervals got too long.
- std::vector<MBBPriorityInfo> MBBs;
- for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
- MachineBasicBlock *MBB = I;
- MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
- isSplitEdge(MBB)));
- }
- std::sort(MBBs.begin(), MBBs.end(), MBBPriorityCompare());
-
- // Finally, join intervals in loop nest order.
- for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
- copyCoalesceInMBB(MBBs[i].MBB);
+ std::vector<MBBPriorityInfo> MBBs;
+ for (MachineFunction::iterator I = MF->begin(), E = MF->end();I != E;++I){
+ MachineBasicBlock *MBB = I;
+ MBBs.push_back(MBBPriorityInfo(MBB, Loops->getLoopDepth(MBB),
+ isSplitEdge(MBB)));
}
+ std::sort(MBBs.begin(), MBBs.end(), MBBPriorityCompare());
+
+ // Coalesce intervals in MBB priority order.
+ for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
+ copyCoalesceInMBB(MBBs[i].MBB);
// Joining intervals can allow other intervals to be joined. Iteratively join
// until we make no progress.
diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll
index 14511ad..5bdad1d 100644
--- a/test/CodeGen/ARM/coalesce-subregs.ll
+++ b/test/CodeGen/ARM/coalesce-subregs.ll
@@ -147,7 +147,7 @@ if.end: ; preds = %entry, %if.then
; CHECK: vmov.f32 {{.*}}, #1.0
; CHECK-NOT: vmov
; CHECK-NOT: vorr
-; CHECK: %if.end
+; CHECK: bx
; We may leave the last insertelement in the if.end block.
; It is inserting the %add value into a dead lane, but %add causes interference
; in the entry block, and we don't do dead lane checks across basic blocks.