diff options
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 9 | ||||
| -rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 10 | ||||
| -rw-r--r-- | test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll | 41 |
3 files changed, 58 insertions, 2 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index fc1b8cf..ebd0d05 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -301,9 +301,16 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, A == &X86::GR64_NOREX_NOSPRegClass) return &X86::GR64_ABCDRegClass; } else if (B == &X86::GR32_NOREXRegClass) { + if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass) + return &X86::GR64_NOREXRegClass; + else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) + return &X86::GR64_NOREX_NOSPRegClass; + else if (A == &X86::GR64_ABCDRegClass) + return &X86::GR64_ABCDRegClass; + } else if (B == &X86::GR32_NOREX_NOSPRegClass) { if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) - return &X86::GR64_NOREXRegClass; + return &X86::GR64_NOREX_NOSPRegClass; else if (A == &X86::GR64_ABCDRegClass) return &X86::GR64_ABCDRegClass; } diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index d2dce1f..a383d3d 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -601,12 +601,20 @@ def GR64_NOSP : RegisterClass<"X86", [i64], 64, (GR32_NOSP sub_32bit)]; } +// GR32_NOREX_NOSP - GR32 registers which do not require a REX prefix except +// ESP. +def GR32_NOREX_NOSP : RegisterClass<"X86", [i32], 32, + [EAX, ECX, EDX, ESI, EDI, EBX, EBP]> { + let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), + (GR16_NOREX sub_16bit)]; +} + // GR64_NOREX_NOSP - GR64_NOREX registers except RSP. def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, RBX, RBP]> { let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi), (GR16_NOREX sub_16bit), - (GR32_NOREX sub_32bit)]; + (GR32_NOREX_NOSP sub_32bit)]; } // A class to support the 'A' assembler constraint: EAX then EDX. diff --git a/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll new file mode 100644 index 0000000..c595bba --- /dev/null +++ b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -verify-coalescing +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.0" + +@bit_count = external constant [256 x i32], align 16 + +define fastcc void @unate_intersect() nounwind uwtable ssp { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.inc.i + br label %do.body.i + +do.body.i: ; preds = %do.body.i, %for.body + %exitcond149 = icmp eq i64 undef, undef + br i1 %exitcond149, label %land.lhs.true, label %do.body.i + +land.lhs.true: ; preds = %do.body.i + br label %for.body.i + +for.body.i: ; preds = %for.inc.i, %if.then + %tmp3524.i = phi i32 [ 0, %land.lhs.true ], [ %tmp351.i, %for.inc.i ] + %tmp6.i12 = load i32* undef, align 4 + br i1 undef, label %for.inc.i, label %if.then.i17 + +if.then.i17: ; preds = %for.body.i + %shr.i14 = lshr i32 %tmp6.i12, 8 + %and14.i = and i32 %shr.i14, 255 + %idxprom15.i = zext i32 %and14.i to i64 + %arrayidx16.i = getelementptr inbounds [256 x i32]* @bit_count, i64 0, i64 %idxprom15.i + %tmp17.i15 = load i32* %arrayidx16.i, align 4 + %add.i = add i32 0, %tmp3524.i + %add24.i = add i32 %add.i, %tmp17.i15 + %add31.i = add i32 %add24.i, 0 + %add33.i = add i32 %add31.i, 0 + br label %for.inc.i + +for.inc.i: ; preds = %if.then.i17, %for.body.i + %tmp351.i = phi i32 [ %add33.i, %if.then.i17 ], [ %tmp3524.i, %for.body.i ] + br label %for.body.i +} |