diff options
| -rw-r--r-- | lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 7 | ||||
| -rw-r--r-- | test/CodeGen/ARM/str_pre-2.ll | 2 | ||||
| -rw-r--r-- | test/MC/ARM/basic-arm-instructions.s | 3 |
4 files changed, 25 insertions, 3 deletions
diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 0b049e9..806c384 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -2879,6 +2879,22 @@ processInstruction(MCInst &Inst, Inst = TmpInst; } break; + case ARM::STMDB_UPD: + // If this is a store of a single register via a 'push', then we should use + // a pre-indexed STR instruction instead, per the ARM ARM. + if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && + Inst.getNumOperands() == 5) { + MCInst TmpInst; + TmpInst.setOpcode(ARM::STR_PRE_IMM); + TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb + TmpInst.addOperand(Inst.getOperand(4)); // Rt + TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 + TmpInst.addOperand(MCOperand::CreateImm(-4)); + TmpInst.addOperand(Inst.getOperand(2)); // CondCode + TmpInst.addOperand(Inst.getOperand(3)); + Inst = TmpInst; + } + break; } } diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index a8008faa..af04355 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -88,6 +88,13 @@ void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { printRegisterList(MI, 4, O); return; } + if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && + MI->getOperand(3).getImm() == -4) { + O << '\t' << "push"; + printPredicateOperand(MI, 4, O); + O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}"; + return; + } // A8.6.122 POP if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) && diff --git a/test/CodeGen/ARM/str_pre-2.ll b/test/CodeGen/ARM/str_pre-2.ll index 8d0c7a5..f4e3a44 100644 --- a/test/CodeGen/ARM/str_pre-2.ll +++ b/test/CodeGen/ARM/str_pre-2.ll @@ -7,7 +7,7 @@ define i64 @t(i64 %a) nounwind readonly { entry: -; CHECK: str lr, [sp, #-4]! +; CHECK: push {lr} ; CHECK: pop {lr} %0 = load i64** @b, align 4 %1 = load i64* %0, align 4 diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index adcecb5..2cec284 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -1071,8 +1071,7 @@ Lforward: push {r7} push {r7, r8, r9, r10} -@ FIXME: push of a single register should encode as "str r7, [sp, #-4]!" -@ CHECK-FIXME: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5] +@ CHECK: push {r7} @ encoding: [0x04,0x70,0x2d,0xe5] @ CHECK: push {r7, r8, r9, r10} @ encoding: [0x80,0x07,0x2d,0xe9] |