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Diffstat (limited to 'docs/R600Usage.rst')
| -rw-r--r-- | docs/R600Usage.rst | 60 |
1 files changed, 53 insertions, 7 deletions
diff --git a/docs/R600Usage.rst b/docs/R600Usage.rst index 48a30c8..093cdd7 100644 --- a/docs/R600Usage.rst +++ b/docs/R600Usage.rst @@ -6,22 +6,51 @@ Introduction ============ The R600 back-end provides ISA code generation for AMD GPUs, starting with -the R600 family up until the current Sea Islands (GCN Gen 2). +the R600 family up until the current Volcanic Islands (GCN Gen 3). Assembler ========= -The assembler is currently a work in progress and not yet complete. Below -are the currently supported features. +The assembler is currently considered experimental. + +For syntax examples look in test/MC/R600. + +Below some of the currently supported features (modulo bugs). These +all apply to the Southern Islands ISA, Sea Islands and Volcanic Islands +are also supported but may be missing some instructions and have more bugs: + +DS Instructions +--------------- +All DS instructions are supported. + +MUBUF Instructions +------------------ +All non-atomic MUBUF instructions are supported. + +SMRD Instructions +----------------- +Only the s_load_dword* SMRD instructions are supported. + +SOP1 Instructions +----------------- +All SOP1 instructions are supported. + +SOP2 Instructions +----------------- +All SOP2 instructions are supported. + +SOPC Instructions +----------------- +All SOPC instructions are supported. SOPP Instructions ----------------- -Unless otherwise mentioned, all SOPP instructions that with an operand -accept a integer operand(s) only. No verification is performed on the -operands, so it is up to the programmer to be familiar with the range -or acceptable values. +Unless otherwise mentioned, all SOPP instructions that have one or more +operands accept integer operands only. No verification is performed +on the operands, so it is up to the programmer to be familiar with the +range or acceptable values. s_waitcnt ^^^^^^^^^ @@ -41,3 +70,20 @@ wait for. // Wait for vmcnt counter to be 1. s_waitcnt vmcnt(1) +VOP1, VOP2, VOP3, VOPC Instructions +----------------------------------- + +All 32-bit and 64-bit encodings should work. + +The assembler will automatically detect which encoding size to use for +VOP1, VOP2, and VOPC instructions based on the operands. If you want to force +a specific encoding size, you can add an _e32 (for 32-bit encoding) or +_e64 (for 64-bit encoding) suffix to the instruction. Most, but not all +instructions support an explicit suffix. These are all valid assembly +strings: + +.. code-block:: nasm + + v_mul_i32_i24 v1, v2, v3 + v_mul_i32_i24_e32 v1, v2, v3 + v_mul_i32_i24_e64 v1, v2, v3 |