diff options
Diffstat (limited to 'docs/ReleaseNotes.html')
| -rw-r--r-- | docs/ReleaseNotes.html | 88 |
1 files changed, 82 insertions, 6 deletions
diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html index b9361a5..fd95a8a 100644 --- a/docs/ReleaseNotes.html +++ b/docs/ReleaseNotes.html @@ -267,6 +267,8 @@ Release Notes</a>.</h1> a fast memory error detector.</li> <li><a href="CodeGenerator.html#machineinstrbundle">MachineInstr Bundles</a>, Support to model instruction bundling / packing.</li> + <li><a href="#armintegratedassembler">ARM Integrated Assembler</a>, + A full featured assembler and direct-to-object support for ARM.</li> <li>....</li> </ul> @@ -284,6 +286,10 @@ Release Notes</a>.</h1> expose new optimization opportunities:</p> <ul> + <li>IR support for half float</li> + <li>IR support for vectors of pointers, including vector GEPs.</li> + <li>Module flags have been introduced. They convey information about the + module as a whole to LLVM subsystems.</li> <li>....</li> </ul> </div> @@ -332,13 +338,33 @@ Release Notes</a>.</h1> <div> +<p>We have changed the way that the Type Legalizer legalizes vectors. The type + legalizer now attempts to promote integer elements. This enabled the + implementation of vector-select. Additionally, we see a performance boost on + workloads which use vectors of chars and shorts, since they are now promoted + to 32-bit types, which are better supported by the SIMD instruction set. + Floating point types are still widened as before.</p> + + <p>We have put a significant amount of work into the code generator infrastructure, which allows us to implement more aggressive algorithms and make it run faster:</p> <ul> - <li>....</li> + <li>TableGen can now synthesize register classes that are only needed to + represent combinations of constraints from instructions and sub-registers. + The synthetic register classes inherit most of their properties form their + closest user-defined super-class.</li> + <li><code>MachineRegisterInfo</code> now allows the reserved registers to be + frozen when register allocation starts. Target hooks should use the + <code>MRI->canReserveReg(FramePtr)</code> method to avoid accidentally + disabling frame pointer elimination during register allocation.</li> + <li>A new kind of <code>MachineOperand</code> provides a compact + representation of large clobber lists on call instructions. The register + mask operand references a bit mask of preserved registers. Everything else + is clobbered.</li> </ul> + </div> <!--=========================================================================--> @@ -351,7 +377,11 @@ Release Notes</a>.</h1> <p>New features and major changes in the X86 target include:</p> <ul> - <li>....</li> + <li>Bug fixes and improved support for AVX1</li> + <li>Support for AVX2 (still incomplete at this point)</li> + <li>Call instructions use the new register mask operands for faster compile + times and better support for different calling conventions. The old WINCALL + instructions are no longer needed.</li> </ul> </div> @@ -366,11 +396,29 @@ Release Notes</a>.</h1> <p>New features of the ARM target include:</p> <ul> - <li>....</li> + <li>The constant island pass now supports basic block and constant pool entry + alignments greater than 4 bytes.</li> + <li>On Darwin, the ARM target now has a full-featured integrated assembler. + </li> </ul> </div> +<h4> +<a name="armintegratedassembler">ARM Integrated Assembler</a> +</h4> +<div> +<p>The ARM target now includes a full featured macro assembler, including +direct-to-object module support for clang. The assembler is currently enabled +by default for Darwin only pending testing and any additional necessary +platform specific support for Linux.</p> +<p>Full support is included for Thumb1, Thumb2 and ARM modes, along with +subtarget and CPU specific extensions for VFP2, VFP3 and NEON.</p> + +<p>The assembler is Unified Syntax only (see ARM Architecural Reference Manual +for details). While there is some, and growing, support for pre-unfied (divided) +syntax, there are still significant gaps in that support.</p> +</div> <!--=========================================================================--> <h3> <a name="MIPS">MIPS Target Improvements</a> @@ -413,9 +461,12 @@ Release Notes</a>.</h1> from the previous release.</p> <ul> -<li>LLVM 3.1 removes support for reading LLVM 2.9 bitcode files. Going forward, - we aim for all future versions of LLVM to read bitcode files and .ll files - produced by LLVM 3.0 and later.</li> + <li>LLVM 3.1 removes support for reading LLVM 2.9 bitcode files. Going + forward, we aim for all future versions of LLVM to read bitcode files and + <tt>.ll</tt> files produced by LLVM 3.0 and later.</li> + <li>The <tt>unwind</tt> instruction is now gone. With the introduction of the + new exception handling system in LLVM 3.0, the <tt>unwind</tt> instruction + became obsolete.</li> <li>....</li> </ul> @@ -439,6 +490,31 @@ Release Notes</a>.</h1> </div> +<!--=========================================================================--> +<h3> +<a name="tools_changes">Tools Changes</a> +</h3> + +<div> + +<p>In addition, some tools have changed in this release. Some of the changes + are:</p> + + +<ul> + <li>llvm-stress is a command line tool for generating random .ll files to fuzz + different LLVM components. </li> + <li>....</li> +</ul> + +<ul> + <li>....</li> +</ul> + +</div> + +</div> + <!-- *********************************************************************** --> <h2> <a name="knownproblems">Known Problems</a> |