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-rw-r--r--include/llvm/Target/Target.td9
1 files changed, 8 insertions, 1 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index d4a1850..5a8707b 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -221,6 +221,11 @@ class Instruction {
bit mayHaveSideEffects = 0;
bit neverHasSideEffects = 0;
+ // Is this instruction a "real" instruction (with a distinct machine
+ // encoding), or is it a pseudo instruction used for codegen modeling
+ // purposes.
+ bit isCodeGenOnly = 0;
+
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
string Constraints = ""; // OperandConstraint, e.g. $src = $dst.
@@ -386,7 +391,8 @@ class InstrInfo {
bit isLittleEndianEncoding = 0;
}
-// Standard Instructions.
+// Standard Pseudo Instructions.
+let isCodeGenOnly = 1 in {
def PHI : Instruction {
let OutOperandList = (ops);
let InOperandList = (ops variable_ops);
@@ -466,6 +472,7 @@ def COPY_TO_REGCLASS : Instruction {
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
}
+}
//===----------------------------------------------------------------------===//
// AsmParser - This class can be implemented by targets that wish to implement