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-rw-r--r--include/llvm/Target/MachineInstrInfo.h25
-rw-r--r--include/llvm/Target/TargetCacheInfo.h6
-rw-r--r--include/llvm/Target/TargetData.h6
-rw-r--r--include/llvm/Target/TargetInstrInfo.h25
-rw-r--r--include/llvm/Target/TargetMachine.h6
-rw-r--r--include/llvm/Target/TargetRegInfo.h10
-rw-r--r--include/llvm/Target/TargetSchedInfo.h46
7 files changed, 59 insertions, 65 deletions
diff --git a/include/llvm/Target/MachineInstrInfo.h b/include/llvm/Target/MachineInstrInfo.h
index 6b1804f..e2489f4 100644
--- a/include/llvm/Target/MachineInstrInfo.h
+++ b/include/llvm/Target/MachineInstrInfo.h
@@ -59,11 +59,11 @@ const unsigned int M_PSEUDO_FLAG = 1 << 14;
struct MachineInstrDescriptor {
- string opCodeString; // Assembly language mnemonic for the opcode.
- int numOperands; // Number of args; -1 if variable #args
- int resultPos; // Position of the result; -1 if no result
+ std::string opCodeString; // Assembly language mnemonic for the opcode.
+ int numOperands; // Number of args; -1 if variable #args
+ int resultPos; // Position of the result; -1 if no result
unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned int numDelaySlots; // Number of delay slots after instruction
unsigned int latency; // Latency in machine cycles
@@ -246,8 +246,8 @@ public:
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& temps) const =0;
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*> &) const = 0;
// Create an instruction sequence to copy an integer value `val'
// to a floating point value `dest' by copying to memory and back.
@@ -258,8 +258,8 @@ public:
virtual void CreateCodeToCopyIntToFloat(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstVec,
+ std::vector<TmpInstruction*>& tmpVec,
TargetMachine& target) const = 0;
// Similarly, create an instruction sequence to copy an FP value
@@ -269,8 +269,8 @@ public:
virtual void CreateCodeToCopyFloatToInt(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstVec,
+ std::vector<TmpInstruction*>& tmpVec,
TargetMachine& target) const = 0;
@@ -279,10 +279,7 @@ public:
CreateCopyInstructionsByType(const TargetMachine& target,
Value* src,
Instruction* dest,
- vector<MachineInstr*>& minstrVec) const = 0;
-
-
-
+ std::vector<MachineInstr*>& minstrVec) const = 0;
};
#endif
diff --git a/include/llvm/Target/TargetCacheInfo.h b/include/llvm/Target/TargetCacheInfo.h
index 21436d0..34194ec 100644
--- a/include/llvm/Target/TargetCacheInfo.h
+++ b/include/llvm/Target/TargetCacheInfo.h
@@ -28,9 +28,9 @@ public:
protected:
unsigned int numLevels;
- vector<unsigned short> cacheLineSizes;
- vector<unsigned int> cacheSizes;
- vector<unsigned short> cacheAssoc;
+ std::vector<unsigned short> cacheLineSizes;
+ std::vector<unsigned int> cacheSizes;
+ std::vector<unsigned short> cacheAssoc;
public:
/*ctor*/ MachineCacheInfo (const TargetMachine& tgt);
diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h
index edd6b26..2bce5f40 100644
--- a/include/llvm/Target/TargetData.h
+++ b/include/llvm/Target/TargetData.h
@@ -31,7 +31,7 @@ class TargetData {
static Annotation *TypeAnFactory(AnnotationID, const Annotable *, void *);
public:
- TargetData(const string &TargetName, unsigned char PtrSize = 8,
+ TargetData(const std::string &TargetName, unsigned char PtrSize = 8,
unsigned char PtrAl = 8, unsigned char DoubleAl = 8,
unsigned char FloatAl = 4, unsigned char LongAl = 8,
unsigned char IntAl = 4, unsigned char ShortAl = 2,
@@ -61,7 +61,7 @@ public:
// stores that include the implicit form of getelementptr.
//
unsigned getIndexedOffset(const Type *Ty,
- const vector<Value*> &Indices) const;
+ const std::vector<Value*> &Indices) const;
inline const StructLayout *getStructLayout(const StructType *Ty) const {
return (const StructLayout*)((const Type*)Ty)->getOrCreateAnnotation(AID);
@@ -73,7 +73,7 @@ public:
// TargetData structure.
//
struct StructLayout : public Annotation {
- vector<unsigned> MemberOffsets;
+ std::vector<unsigned> MemberOffsets;
unsigned StructSize;
unsigned StructAlignment;
private:
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index 6b1804f..e2489f4 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -59,11 +59,11 @@ const unsigned int M_PSEUDO_FLAG = 1 << 14;
struct MachineInstrDescriptor {
- string opCodeString; // Assembly language mnemonic for the opcode.
- int numOperands; // Number of args; -1 if variable #args
- int resultPos; // Position of the result; -1 if no result
+ std::string opCodeString; // Assembly language mnemonic for the opcode.
+ int numOperands; // Number of args; -1 if variable #args
+ int resultPos; // Position of the result; -1 if no result
unsigned int maxImmedConst; // Largest +ve constant in IMMMED field or 0.
- bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
+ bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned int numDelaySlots; // Number of delay slots after instruction
unsigned int latency; // Latency in machine cycles
@@ -246,8 +246,8 @@ public:
//
virtual void CreateCodeToLoadConst(Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& temps) const =0;
+ std::vector<MachineInstr*>& minstrVec,
+ std::vector<TmpInstruction*> &) const = 0;
// Create an instruction sequence to copy an integer value `val'
// to a floating point value `dest' by copying to memory and back.
@@ -258,8 +258,8 @@ public:
virtual void CreateCodeToCopyIntToFloat(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstVec,
+ std::vector<TmpInstruction*>& tmpVec,
TargetMachine& target) const = 0;
// Similarly, create an instruction sequence to copy an FP value
@@ -269,8 +269,8 @@ public:
virtual void CreateCodeToCopyFloatToInt(Method* method,
Value* val,
Instruction* dest,
- vector<MachineInstr*>& minstrVec,
- vector<TmpInstruction*>& tempVec,
+ std::vector<MachineInstr*>& minstVec,
+ std::vector<TmpInstruction*>& tmpVec,
TargetMachine& target) const = 0;
@@ -279,10 +279,7 @@ public:
CreateCopyInstructionsByType(const TargetMachine& target,
Value* src,
Instruction* dest,
- vector<MachineInstr*>& minstrVec) const = 0;
-
-
-
+ std::vector<MachineInstr*>& minstrVec) const = 0;
};
#endif
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index ad1f105..6effeed 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -38,14 +38,14 @@ typedef int OpCodeMask;
class TargetMachine : public NonCopyableV {
public:
- const string TargetName;
+ const std::string TargetName;
const TargetData DataLayout; // Calculates type size & alignment
int optSizeForSubWordData;
int minMemOpWordSize;
int maxAtomicMemOpWordSize;
protected:
- TargetMachine(const string &targetname, // Can only create subclasses...
+ TargetMachine(const std::string &targetname, // Can only create subclasses...
unsigned char PtrSize = 8, unsigned char PtrAl = 8,
unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
unsigned char LongAl = 8, unsigned char IntAl = 4,
@@ -86,7 +86,7 @@ public:
// method. The specified method must have been compiled before this may be
// used.
//
- virtual void emitAssembly(const Module *M, ostream &OutStr) const = 0;
+ virtual void emitAssembly(const Module *M, std::ostream &OutStr) const = 0;
};
#endif
diff --git a/include/llvm/Target/TargetRegInfo.h b/include/llvm/Target/TargetRegInfo.h
index ae083c9..b2fa048 100644
--- a/include/llvm/Target/TargetRegInfo.h
+++ b/include/llvm/Target/TargetRegInfo.h
@@ -9,7 +9,7 @@
#define LLVM_TARGET_MACHINEREGINFO_H
#include "Support/NonCopyable.h"
-#include <hash_map>
+#include <ext/hash_map>
#include <string>
class TargetMachine;
@@ -76,11 +76,11 @@ public:
-typedef hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
+typedef std::hash_map<const MachineInstr *, AddedInstrns *> AddedInstrMapType;
// A vector of all machine register classes
//
-typedef vector<const MachineRegClassInfo *> MachineRegClassArrayType;
+typedef std::vector<const MachineRegClassInfo *> MachineRegClassArrayType;
class MachineRegInfo : public NonCopyableV {
@@ -128,7 +128,7 @@ public:
LiveRangeInfo & LRI) const = 0;
virtual void suggestRegs4CallArgs(const MachineInstr *const CallI,
- LiveRangeInfo& LRI, vector<RegClass *> RCL) const = 0;
+ LiveRangeInfo& LRI, std::vector<RegClass *> RCL) const = 0;
virtual void suggestReg4RetValue(const MachineInstr *const RetI,
LiveRangeInfo& LRI) const = 0;
@@ -186,7 +186,7 @@ public:
//
virtual int getUnifiedRegNum(int RegClassID, int reg) const = 0;
- virtual const string getUnifiedRegName(int UnifiedRegNum) const = 0;
+ virtual const std::string getUnifiedRegName(int UnifiedRegNum) const = 0;
// Gives the type of a register based on the type of the LR
diff --git a/include/llvm/Target/TargetSchedInfo.h b/include/llvm/Target/TargetSchedInfo.h
index 356c785..e8908c5 100644
--- a/include/llvm/Target/TargetSchedInfo.h
+++ b/include/llvm/Target/TargetSchedInfo.h
@@ -8,10 +8,10 @@
#define LLVM_TARGET_MACHINESCHEDINFO_H
#include "llvm/Target/MachineInstrInfo.h"
-#include <hash_map>
+#include <ext/hash_map>
typedef long long cycles_t;
-const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-1);
+const cycles_t HUGE_LATENCY = ~((unsigned long long) 1 << sizeof(cycles_t)-2);
const cycles_t INVALID_LATENCY = -HUGE_LATENCY;
static const unsigned MAX_OPCODE_SIZE = 16;
@@ -28,13 +28,13 @@ private:
OpCodePair(); // disable for now
};
-
+namespace std {
template <> struct hash<OpCodePair> {
size_t operator()(const OpCodePair& pair) const {
return hash<long>()(pair.val);
}
};
-
+}
//---------------------------------------------------------------------------
// class MachineResource
@@ -50,10 +50,10 @@ typedef unsigned int resourceId_t;
class MachineResource {
public:
- const string rname;
+ const std::string rname;
resourceId_t rid;
- /*ctor*/ MachineResource(const string& resourceName)
+ /*ctor*/ MachineResource(const std::string& resourceName)
: rname(resourceName), rid(nextId++) {}
private:
@@ -66,7 +66,7 @@ class CPUResource : public MachineResource {
public:
int maxNumUsers; // MAXINT if no restriction
- /*ctor*/ CPUResource(const string& rname, int maxUsers)
+ /*ctor*/ CPUResource(const std::string& rname, int maxUsers)
: MachineResource(rname), maxNumUsers(maxUsers) {}
};
@@ -147,11 +147,11 @@ struct InstrRUsage {
cycles_t numBubbles;
// Feasible slots to use for this instruction.
- vector<bool> feasibleSlots;
+ std::vector<bool> feasibleSlots;
// Resource usages for this instruction, with one resource vector per cycle.
cycles_t numCycles;
- vector<vector<resourceId_t> > resourcesByCycle;
+ std::vector<std::vector<resourceId_t> > resourcesByCycle;
private:
// Conveniences for initializing this structure
@@ -243,7 +243,7 @@ InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
// resize the resources vector if more cycles are specified
unsigned maxCycles = this->numCycles;
- maxCycles = max(maxCycles, delta.startCycle + abs(NC) - 1);
+ maxCycles = std::max(maxCycles, delta.startCycle + abs(NC) - 1);
if (maxCycles > this->numCycles)
{
this->resourcesByCycle.resize(maxCycles);
@@ -259,7 +259,7 @@ InstrRUsage::addUsageDelta(const InstrRUsageDelta& delta)
{
// Look for the resource backwards so we remove the last entry
// for that resource in each cycle.
- vector<resourceId_t>& rvec = this->resourcesByCycle[c];
+ std::vector<resourceId_t>& rvec = this->resourcesByCycle[c];
int r;
for (r = (int) rvec.size(); r >= 0; r--)
if (rvec[r] == delta.resourceId)
@@ -349,14 +349,14 @@ public:
inline int getMinIssueGap (MachineOpCode fromOp,
MachineOpCode toOp) const {
- hash_map<OpCodePair,int>::const_iterator
+ std::hash_map<OpCodePair,int>::const_iterator
I = issueGaps.find(OpCodePair(fromOp, toOp));
return (I == issueGaps.end())? 0 : (*I).second;
}
- inline const vector<MachineOpCode>*
+ inline const std::vector<MachineOpCode>*
getConflictList(MachineOpCode opCode) const {
- hash_map<MachineOpCode,vector<MachineOpCode> >::const_iterator
+ std::hash_map<MachineOpCode, std::vector<MachineOpCode> >::const_iterator
I = conflictLists.find(opCode);
return (I == conflictLists.end())? NULL : & (*I).second;
}
@@ -377,22 +377,22 @@ protected:
virtual void initializeResources ();
private:
- void computeInstrResources(const vector<InstrRUsage>& instrRUForClasses);
- void computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses);
+ void computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses);
+ void computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses);
protected:
int numSchedClasses;
const MachineInstrInfo* mii;
- const InstrClassRUsage* classRUsages; // raw array by sclass
- const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
- const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
+ const InstrClassRUsage* classRUsages; // raw array by sclass
+ const InstrRUsageDelta* usageDeltas; // raw array [1:numUsageDeltas]
+ const InstrIssueDelta* issueDeltas; // raw array [1:numIssueDeltas]
unsigned int numUsageDeltas;
unsigned int numIssueDeltas;
- vector<InstrRUsage> instrRUsages; // indexed by opcode
- hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
- hash_map<MachineOpCode,vector<MachineOpCode> >
- conflictLists; // indexed by opcode
+ std::vector<InstrRUsage> instrRUsages; // indexed by opcode
+ std::hash_map<OpCodePair,int> issueGaps; // indexed by opcode pair
+ std::hash_map<MachineOpCode, std::vector<MachineOpCode> >
+ conflictLists; // indexed by opcode
};
#endif
generated by cgit v1.1 at 2025-08-17 14:10:19 +0000