diff options
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 38 | ||||
| -rw-r--r-- | include/llvm/Target/TargetAsmInfo.h | 31 | ||||
| -rw-r--r-- | include/llvm/Target/TargetAsmParser.h | 13 | ||||
| -rw-r--r-- | include/llvm/Target/TargetData.h | 8 | ||||
| -rw-r--r-- | include/llvm/Target/TargetFrameLowering.h | 10 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 7 | ||||
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 2 | ||||
| -rw-r--r-- | include/llvm/Target/TargetMachine.h | 22 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegisterInfo.h | 2 | ||||
| -rw-r--r-- | include/llvm/Target/TargetRegistry.h | 101 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelect.h | 48 | ||||
| -rw-r--r-- | include/llvm/Target/TargetSelectionDAG.td | 1 |
12 files changed, 186 insertions, 97 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 4d7116b..018ccbd 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -293,7 +293,12 @@ class Instruction { // code. list<Predicate> Predicates = []; - // Code size. + // Size - Size of encoded instruction, or zero if the size cannot be determined + // from the opcode. + int Size = 0; + + // Code size, for instruction selection. + // FIXME: What does this actually mean? int CodeSize = 0; // Added complexity passed onto matching pattern. @@ -324,6 +329,9 @@ class Instruction { bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction. bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement? bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement? + bit isPseudo = 0; // Is this instruction a pseudo-instruction? + // If so, won't have encoding information for + // the [MC]CodeEmitter stuff. // Side effect flags - When set, the flags have these meanings: // @@ -338,6 +346,11 @@ class Instruction { // Is this instruction a "real" instruction (with a distinct machine // encoding), or is it a pseudo instruction used for codegen modeling // purposes. + // FIXME: For now this is distinct from isPseudo, above, as code-gen-only + // instructions can (and often do) still have encoding information + // associated with them. Once we've migrated all of them over to true + // pseudo-instructions that are lowered to real instructions prior to + // the printer/emitter, we can remove this attribute and just use isPseudo. bit isCodeGenOnly = 0; // Is this instruction a pseudo instruction for use by the assembler parser. @@ -365,6 +378,14 @@ class Instruction { ///@} } +/// PseudoInstExpansion - Expansion information for a pseudo-instruction. +/// Which instruction it expands to and how the operands map from the +/// pseudo. +class PseudoInstExpansion<dag Result> { + dag ResultInst = Result; // The instruction to generate. + bit isPseudo = 1; +} + /// Predicates - These are extra conditionals which are turned into instruction /// selector matching code. Currently each predicate is just a string. class Predicate<string cond> { @@ -374,6 +395,15 @@ class Predicate<string cond> { /// matcher, this is true. Targets should set this by inheriting their /// feature from the AssemblerPredicate class in addition to Predicate. bit AssemblerMatcherPredicate = 0; + + /// AssemblerCondString - Name of the subtarget feature being tested used + /// as alternative condition string used for assembler matcher. + /// e.g. "ModeThumb" is translated to "(Bits & ModeThumb) != 0". + /// "!ModeThumb" is translated to "(Bits & ModeThumb) == 0". + /// It can also list multiple features separated by ",". + /// e.g. "ModeThumb,FeatureThumb2" is translated to + /// "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". + string AssemblerCondString = ""; } /// NoHonorSignDependentRounding - This predicate is true if support for @@ -470,6 +500,7 @@ class Operand<ValueType ty> { string EncoderMethod = ""; string DecoderMethod = ""; string AsmOperandLowerMethod = ?; + string OperandType = "OPERAND_UNKNOWN"; dag MIOperandInfo = (ops); // ParserMatchClass - The "match class" that operands of this type fit @@ -501,6 +532,7 @@ class RegisterOperand<RegisterClass regclass, string pm = "printOperand"> { AsmOperandClass ParserMatchClass; } +let OperandType = "OPERAND_IMMEDIATE" in { def i1imm : Operand<i1>; def i8imm : Operand<i8>; def i16imm : Operand<i16>; @@ -509,6 +541,7 @@ def i64imm : Operand<i64>; def f32imm : Operand<f32>; def f64imm : Operand<f64>; +} /// zero_reg definition - Special node to stand for the zero register. /// @@ -681,8 +714,9 @@ def DefaultAsmParser : AsmParser; /// AssemblerPredicate - This is a Predicate that can be used when the assembler /// matches instructions and aliases. -class AssemblerPredicate { +class AssemblerPredicate<string cond> { bit AssemblerMatcherPredicate = 1; + string AssemblerCondString = cond; } diff --git a/include/llvm/Target/TargetAsmInfo.h b/include/llvm/Target/TargetAsmInfo.h index 1a417a1..5a526dc 100644 --- a/include/llvm/Target/TargetAsmInfo.h +++ b/include/llvm/Target/TargetAsmInfo.h @@ -20,6 +20,7 @@ #include "llvm/Target/TargetRegisterInfo.h" namespace llvm { + template <typename T> class ArrayRef; class MCSection; class MCContext; class MachineFunction; @@ -27,30 +28,14 @@ namespace llvm { class TargetLoweringObjectFile; class TargetAsmInfo { - unsigned PointerSize; - bool IsLittleEndian; - TargetFrameLowering::StackDirection StackDir; - const TargetRegisterInfo *TRI; std::vector<MachineMove> InitialFrameState; + const TargetRegisterInfo *TRI; + const TargetFrameLowering *TFI; const TargetLoweringObjectFile *TLOF; public: explicit TargetAsmInfo(const TargetMachine &TM); - /// getPointerSize - Get the pointer size in bytes. - unsigned getPointerSize() const { - return PointerSize; - } - - /// islittleendian - True if the target is little endian. - bool isLittleEndian() const { - return IsLittleEndian; - } - - TargetFrameLowering::StackDirection getStackGrowthDirection() const { - return StackDir; - } - const MCSection *getDwarfLineSection() const { return TLOF->getDwarfLineSection(); } @@ -83,6 +68,12 @@ public: return TLOF->isFunctionEHFrameSymbolPrivate(); } + int getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs, + int DataAlignmentFactor, + bool IsEH) const { + return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH); + } + const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const { return TRI->getCalleeSavedRegs(MF); } @@ -106,10 +97,6 @@ public: int getSEHRegNum(unsigned RegNum) const { return TRI->getSEHRegNum(RegNum); } - - int getCompactUnwindRegNum(unsigned RegNum) const { - return TRI->getCompactUnwindRegNum(RegNum); - } }; } diff --git a/include/llvm/Target/TargetAsmParser.h b/include/llvm/Target/TargetAsmParser.h index 9ff50cb..df84231 100644 --- a/include/llvm/Target/TargetAsmParser.h +++ b/include/llvm/Target/TargetAsmParser.h @@ -15,7 +15,6 @@ namespace llvm { class MCStreamer; class StringRef; -class Target; class SMLoc; class AsmToken; class MCParsedAsmOperand; @@ -26,23 +25,19 @@ class TargetAsmParser : public MCAsmParserExtension { TargetAsmParser(const TargetAsmParser &); // DO NOT IMPLEMENT void operator=(const TargetAsmParser &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetAsmParser(const Target &); + TargetAsmParser(); - /// The Target that this machine was created for. - const Target &TheTarget; - - /// The current set of available features. + /// AvailableFeatures - The current set of available features. unsigned AvailableFeatures; public: virtual ~TargetAsmParser(); - const Target &getTarget() const { return TheTarget; } - unsigned getAvailableFeatures() const { return AvailableFeatures; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } - virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) = 0; + virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, + SMLoc &EndLoc) = 0; /// ParseInstruction - Parse one assembly instruction. /// diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h index 32e3e2b..c280810 100644 --- a/include/llvm/Target/TargetData.h +++ b/include/llvm/Target/TargetData.h @@ -259,7 +259,7 @@ public: /// getIntPtrType - Return an unsigned integer type that is the same size or /// greater to the host pointer size. /// - const IntegerType *getIntPtrType(LLVMContext &C) const; + IntegerType *getIntPtrType(LLVMContext &C) const; /// getIndexedOffset - return the offset from the beginning of the type for /// the specified indices. This is used to implement getelementptr. @@ -272,12 +272,6 @@ public: /// information is lazily cached. const StructLayout *getStructLayout(const StructType *Ty) const; - /// InvalidateStructLayoutInfo - TargetData speculatively caches StructLayout - /// objects. If a TargetData object is alive when types are being refined and - /// removed, this method must be called whenever a StructType is removed to - /// avoid a dangling pointer in this cache. - void InvalidateStructLayoutInfo(const StructType *Ty) const; - /// getPreferredAlignment - Return the preferred alignment of the specified /// global. This includes an explicitly requested alignment (if the global /// has one). diff --git a/include/llvm/Target/TargetFrameLowering.h b/include/llvm/Target/TargetFrameLowering.h index e104b16..e3d77cf 100644 --- a/include/llvm/Target/TargetFrameLowering.h +++ b/include/llvm/Target/TargetFrameLowering.h @@ -15,6 +15,8 @@ #define LLVM_TARGET_TARGETFRAMELOWERING_H #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/MC/MCDwarf.h" +#include "llvm/ADT/ArrayRef.h" #include <utility> #include <vector> @@ -189,6 +191,14 @@ public: /// virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { } + + /// getCompactUnwindEncoding - Get the compact unwind encoding for the + /// function. Return 0 if the compact unwind isn't available. + virtual uint32_t getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs, + int DataAlignmentFactor, + bool IsEH) const { + return 0; + } }; } // End llvm namespace diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 1b6b3a7..f663566 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -32,6 +32,7 @@ class SelectionDAG; class ScheduleDAG; class TargetRegisterClass; class TargetRegisterInfo; +class BranchProbability; template<class T> class SmallVectorImpl; @@ -321,7 +322,7 @@ public: virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, unsigned ExtraPredCycles, - float Probability, float Confidence) const { + const BranchProbability &Probability) const { return false; } @@ -336,7 +337,7 @@ public: unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, - float Probability, float Confidence) const { + const BranchProbability &Probability) const { return false; } @@ -348,7 +349,7 @@ public: /// will be properly predicted. virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, - float Probability, float Confidence) const { + const BranchProbability &Probability) const { return false; } diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index f684163..533c3ac 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1540,6 +1540,8 @@ public: //===--------------------------------------------------------------------===// // Div utility functions // + SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, DebugLoc dl, + SelectionDAG &DAG) const; SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector<SDNode*>* Created) const; SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h index 01fdb57..ac41a58 100644 --- a/include/llvm/Target/TargetMachine.h +++ b/include/llvm/Target/TargetMachine.h @@ -14,6 +14,7 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H +#include "llvm/ADT/StringRef.h" #include <cassert> #include <string> @@ -91,7 +92,8 @@ class TargetMachine { TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT void operator=(const TargetMachine &); // DO NOT IMPLEMENT protected: // Can only create subclasses. - TargetMachine(const Target &); + TargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS); /// getSubtargetImpl - virtual method implemented by subclasses that returns /// a reference to that target's TargetSubtargetInfo-derived member variable. @@ -100,6 +102,12 @@ protected: // Can only create subclasses. /// TheTarget - The Target that this machine was created for. const Target &TheTarget; + /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target + /// feature strings the TargetMachine instance is created with. + std::string TargetTriple; + std::string TargetCPU; + std::string TargetFS; + /// AsmInfo - Contains target specific asm information. /// const MCAsmInfo *AsmInfo; @@ -115,6 +123,10 @@ public: const Target &getTarget() const { return TheTarget; } + const StringRef getTargetTriple() const { return TargetTriple; } + const StringRef getTargetCPU() const { return TargetCPU; } + const StringRef getTargetFeatureString() const { return TargetFS; } + // Interfaces to the major aspects of target machine information: // -- Instruction opcode and operand information // -- Pipelines and scheduling information @@ -295,10 +307,9 @@ public: /// implemented with the LLVM target-independent code generator. /// class LLVMTargetMachine : public TargetMachine { - std::string TargetTriple; - protected: // Can only create subclasses. - LLVMTargetMachine(const Target &T, const std::string &TargetTriple); + LLVMTargetMachine(const Target &T, StringRef TargetTriple, + StringRef CPU, StringRef FS); private: /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for @@ -311,9 +322,6 @@ private: virtual void setCodeModelForStatic(); public: - - const std::string &getTargetTriple() const { return TargetTriple; } - /// addPassesToEmitFile - Add passes to the specified pass manager to get the /// specified file emitted. Typically this will involve several steps of code /// generation. If OptLevel is None, the code generator should emit code as diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h index 3f28f6c..8d827f1 100644 --- a/include/llvm/Target/TargetRegisterInfo.h +++ b/include/llvm/Target/TargetRegisterInfo.h @@ -723,7 +723,7 @@ public: /// getCompactUnwindRegNum - This function maps the register to the number for /// compact unwind encoding. Return -1 if the register isn't valid. - virtual int getCompactUnwindRegNum(unsigned) const { + virtual int getCompactUnwindRegNum(unsigned, bool) const { return -1; } }; diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h index 2e79488..7e0ce19 100644 --- a/include/llvm/Target/TargetRegistry.h +++ b/include/llvm/Target/TargetRegistry.h @@ -35,8 +35,8 @@ namespace llvm { class MCInstPrinter; class MCInstrInfo; class MCRegisterInfo; - class MCSubtargetInfo; class MCStreamer; + class MCSubtargetInfo; class TargetAsmBackend; class TargetAsmLexer; class TargetAsmParser; @@ -66,11 +66,13 @@ namespace llvm { typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT); - typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T, - StringRef TT); + typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T, + StringRef TT); typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); - typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(void); + typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT, + StringRef CPU, + StringRef Features); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, const std::string &CPU, @@ -81,15 +83,14 @@ namespace llvm { const std::string &TT); typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T, const MCAsmInfo &MAI); - typedef TargetAsmParser *(*AsmParserCtorTy)(const Target &T,MCAsmParser &P, - TargetMachine &TM); + typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI, + MCAsmParser &P); typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T); typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T, - TargetMachine &TM, unsigned SyntaxVariant, const MCAsmInfo &MAI); - typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const Target &T, - TargetMachine &TM, + typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const MCInstrInfo &II, + const MCSubtargetInfo &STI, MCContext &Ctx); typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T, const std::string &TT, @@ -127,9 +128,9 @@ namespace llvm { /// HasJIT - Whether this target supports the JIT. bool HasJIT; - /// AsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if + /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if /// registered. - AsmInfoCtorFnTy AsmInfoCtorFn; + MCAsmInfoCtorFnTy MCAsmInfoCtorFn; /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, /// if registered. @@ -239,17 +240,17 @@ namespace llvm { /// @name Feature Constructors /// @{ - /// createAsmInfo - Create a MCAsmInfo implementation for the specified + /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified /// target triple. /// /// \arg Triple - This argument is used to determine the target machine /// feature set; it should always be provided. Generally this should be /// either the target triple from the module, or the target triple of the /// host if that does not exist. - MCAsmInfo *createAsmInfo(StringRef Triple) const { - if (!AsmInfoCtorFn) + MCAsmInfo *createMCAsmInfo(StringRef Triple) const { + if (!MCAsmInfoCtorFn) return 0; - return AsmInfoCtorFn(*this, Triple); + return MCAsmInfoCtorFn(*this, Triple); } /// createMCInstrInfo - Create a MCInstrInfo implementation. @@ -270,10 +271,18 @@ namespace llvm { /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation. /// - MCSubtargetInfo *createMCSubtargetInfo() const { + /// \arg Triple - This argument is used to determine the target machine + /// feature set; it should always be provided. Generally this should be + /// either the target triple from the module, or the target triple of the + /// host if that does not exist. + /// \arg CPU - This specifies the name of the target CPU. + /// \arg Features - This specifies the string representation of the + /// additional target features. + MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU, + StringRef Features) const { if (!MCSubtargetInfoCtorFn) return 0; - return MCSubtargetInfoCtorFn(); + return MCSubtargetInfoCtorFn(Triple, CPU, Features); } /// createTargetMachine - Create a target specific machine implementation @@ -313,11 +322,11 @@ namespace llvm { /// /// \arg Parser - The target independent parser implementation to use for /// parsing and lexing. - TargetAsmParser *createAsmParser(MCAsmParser &Parser, - TargetMachine &TM) const { + TargetAsmParser *createAsmParser(MCSubtargetInfo &STI, + MCAsmParser &Parser) const { if (!AsmParserCtorFn) return 0; - return AsmParserCtorFn(*this, Parser, TM); + return AsmParserCtorFn(STI, Parser); } /// createAsmPrinter - Create a target specific assembly printer pass. This @@ -334,20 +343,21 @@ namespace llvm { return MCDisassemblerCtorFn(*this); } - MCInstPrinter *createMCInstPrinter(TargetMachine &TM, - unsigned SyntaxVariant, + MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant, const MCAsmInfo &MAI) const { if (!MCInstPrinterCtorFn) return 0; - return MCInstPrinterCtorFn(*this, TM, SyntaxVariant, MAI); + return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI); } /// createCodeEmitter - Create a target specific code emitter. - MCCodeEmitter *createCodeEmitter(TargetMachine &TM, MCContext &Ctx) const { + MCCodeEmitter *createCodeEmitter(const MCInstrInfo &II, + const MCSubtargetInfo &STI, + MCContext &Ctx) const { if (!CodeEmitterCtorFn) return 0; - return CodeEmitterCtorFn(*this, TM, Ctx); + return CodeEmitterCtorFn(II, STI, Ctx); } /// createObjectStreamer - Create a target specific MCStreamer. @@ -475,7 +485,7 @@ namespace llvm { Target::TripleMatchQualityFnTy TQualityFn, bool HasJIT = false); - /// RegisterAsmInfo - Register a MCAsmInfo implementation for the + /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the /// given target. /// /// Clients are responsible for ensuring that registration doesn't occur @@ -484,10 +494,10 @@ namespace llvm { /// /// @param T - The target being registered. /// @param Fn - A function to construct a MCAsmInfo for the target. - static void RegisterAsmInfo(Target &T, Target::AsmInfoCtorFnTy Fn) { + static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) { // Ignore duplicate registration. - if (!T.AsmInfoCtorFn) - T.AsmInfoCtorFn = Fn; + if (!T.MCAsmInfoCtorFn) + T.MCAsmInfoCtorFn = Fn; } /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the @@ -712,18 +722,18 @@ namespace llvm { } }; - /// RegisterAsmInfo - Helper template for registering a target assembly info + /// RegisterMCAsmInfo - Helper template for registering a target assembly info /// implementation. This invokes the static "Create" method on the class to /// actually do the construction. Usage: /// /// extern "C" void LLVMInitializeFooTarget() { /// extern Target TheFooTarget; - /// RegisterAsmInfo<FooMCAsmInfo> X(TheFooTarget); + /// RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget); /// } template<class MCAsmInfoImpl> - struct RegisterAsmInfo { - RegisterAsmInfo(Target &T) { - TargetRegistry::RegisterAsmInfo(T, &Allocator); + struct RegisterMCAsmInfo { + RegisterMCAsmInfo(Target &T) { + TargetRegistry::RegisterMCAsmInfo(T, &Allocator); } private: static MCAsmInfo *Allocator(const Target &T, StringRef TT) { @@ -732,17 +742,17 @@ namespace llvm { }; - /// RegisterAsmInfoFn - Helper template for registering a target assembly info + /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info /// implementation. This invokes the specified function to do the /// construction. Usage: /// /// extern "C" void LLVMInitializeFooTarget() { /// extern Target TheFooTarget; - /// RegisterAsmInfoFn X(TheFooTarget, TheFunction); + /// RegisterMCAsmInfoFn X(TheFooTarget, TheFunction); /// } - struct RegisterAsmInfoFn { - RegisterAsmInfoFn(Target &T, Target::AsmInfoCtorFnTy Fn) { - TargetRegistry::RegisterAsmInfo(T, Fn); + struct RegisterMCAsmInfoFn { + RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) { + TargetRegistry::RegisterMCAsmInfo(T, Fn); } }; @@ -826,7 +836,8 @@ namespace llvm { TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator); } private: - static MCSubtargetInfo *Allocator() { + static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU, + StringRef FS) { return new MCSubtargetInfoImpl(); } }; @@ -922,9 +933,8 @@ namespace llvm { } private: - static TargetAsmParser *Allocator(const Target &T, MCAsmParser &P, - TargetMachine &TM) { - return new AsmParserImpl(T, P, TM); + static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) { + return new AsmParserImpl(STI, P); } }; @@ -963,9 +973,10 @@ namespace llvm { } private: - static MCCodeEmitter *Allocator(const Target &T, TargetMachine &TM, + static MCCodeEmitter *Allocator(const MCInstrInfo &II, + const MCSubtargetInfo &STI, MCContext &Ctx) { - return new CodeEmitterImpl(T, TM, Ctx); + return new CodeEmitterImpl(); } }; diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h index c5ab90b..272ee09 100644 --- a/include/llvm/Target/TargetSelect.h +++ b/include/llvm/Target/TargetSelect.h @@ -26,6 +26,18 @@ extern "C" { #define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target(); #include "llvm/Config/Targets.def" +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCAsmInfo(); +#include "llvm/Config/Targets.def" + +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCInstrInfo(); +#include "llvm/Config/Targets.def" + +#define LLVM_TARGET(TargetName) \ + void LLVMInitialize##TargetName##MCSubtargetInfo(); +#include "llvm/Config/Targets.def" + // Declare all of the available assembly printer initialization functions. #define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter(); #include "llvm/Config/AsmPrinters.def" @@ -35,7 +47,8 @@ extern "C" { #include "llvm/Config/AsmParsers.def" // Declare all of the available disassembler initialization functions. -#define LLVM_DISASSEMBLER(TargetName) void LLVMInitialize##TargetName##Disassembler(); +#define LLVM_DISASSEMBLER(TargetName) \ + void LLVMInitialize##TargetName##Disassembler(); #include "llvm/Config/Disassemblers.def" } @@ -63,6 +76,38 @@ namespace llvm { #include "llvm/Config/Targets.def" } + /// InitializeAllMCAsmInfos - The main program should call this function + /// if it wants access to all available assembly infos for targets that + /// LLVM is configured to support, to make them available via the + /// TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCAsmInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCAsmInfo(); +#include "llvm/Config/Targets.def" + } + + /// InitializeAllMCInstrInfos - The main program should call this function + /// if it wants access to all available instruction infos for targets that + /// LLVM is configured to support, to make them available via the + /// TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCInstrInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCInstrInfo(); +#include "llvm/Config/Targets.def" + } + + /// InitializeAllMCSubtargetInfos - The main program should call this function + /// if it wants access to all available subtarget infos for targets that LLVM + /// is configured to support, to make them available via the TargetRegistry. + /// + /// It is legal for a client to make multiple calls to this function. + inline void InitializeAllMCSubtargetInfos() { +#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo(); +#include "llvm/Config/Targets.def" + } + /// InitializeAllAsmPrinters - The main program should call this function if /// it wants all asm printers that LLVM is configured to support, to make them /// available via the TargetRegistry. @@ -103,6 +148,7 @@ namespace llvm { #ifdef LLVM_NATIVE_TARGET LLVM_NATIVE_TARGETINFO(); LLVM_NATIVE_TARGET(); + LLVM_NATIVE_MCASMINFO(); return false; #else return true; diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td index 285b8b1..9d1ef2c 100644 --- a/include/llvm/Target/TargetSelectionDAG.td +++ b/include/llvm/Target/TargetSelectionDAG.td @@ -353,6 +353,7 @@ def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>; def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>; def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; +def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>; def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; |