2 files changed, 16 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h
index b36ed86..7eef093 100644
--- a/include/llvm/CodeGen/SelectionDAG.h
+++ b/include/llvm/CodeGen/SelectionDAG.h
@@ -346,6 +346,14 @@ public:
     return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
   }
 
+  /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
+  /// if you just have an ISD::CondCode instead of an SDOperand.
+  ///
+  SDOperand getVSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
+                      ISD::CondCode Cond) {
+    return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
+  }
+
   /// getSelectCC - Helper function to make it easier to build SelectCC's if you
   /// just have an ISD::CondCode instead of an SDOperand.
   ///
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index f2ff91a..5cfc166 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -332,6 +332,14 @@ namespace ISD {
     // (op #2) as a CondCodeSDNode.
     SETCC,
 
+    // Vector SetCC operator - This evaluates to a vector of integer elements
+    // with the high bit in each element set to true if the comparison is true
+    // and false if the comparison is false.  All other bits in each element 
+    // are undefined.  The operands to this are the left and right operands
+    // to compare (ops #0, and #1) and the condition code to compare them with
+    // (op #2) as a CondCodeSDNode.
+    VSETCC,
+
     // SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
     // integer shift operations, just like ADD/SUB_PARTS.  The operation
     // ordering is: