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-rw-r--r--include/llvm/Target/Target.td2
-rw-r--r--include/llvm/Target/TargetInstrDesc.h4
2 files changed, 4 insertions, 2 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index ca551e5..6379459 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -244,7 +244,7 @@ class Instruction {
string DisableEncoding = "";
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
- bits<32> TSFlags = 0;
+ bits<64> TSFlags = 0;
}
/// Predicates - These are extra conditionals which are turned into instruction
diff --git a/include/llvm/Target/TargetInstrDesc.h b/include/llvm/Target/TargetInstrDesc.h
index adc37e1..a004f95 100644
--- a/include/llvm/Target/TargetInstrDesc.h
+++ b/include/llvm/Target/TargetInstrDesc.h
@@ -15,6 +15,8 @@
#ifndef LLVM_TARGET_TARGETINSTRDESC_H
#define LLVM_TARGET_TARGETINSTRDESC_H
+#include "llvm/System/DataTypes.h"
+
namespace llvm {
class TargetRegisterClass;
@@ -131,7 +133,7 @@ public:
unsigned short SchedClass; // enum identifying instr sched class
const char * Name; // Name of the instruction record in td file
unsigned Flags; // Flags identifying machine instr class
- unsigned TSFlags; // Target Specific Flag values
+ uint64_t TSFlags; // Target Specific Flag values
const unsigned *ImplicitUses; // Registers implicitly read by this instr
const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered"