aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/llvm/Target/Target.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 82cd4dd..89ca529 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -444,9 +444,6 @@ class Instruction {
/// constraint. For example, "$Rn = $Rd".
string TwoOperandAliasConstraint = "";
- /// Does the instruction mnemonic allow '.'
- bit MnemonicContainsDot = 0;
-
///@}
/// UseNamedOperandTable - If set, the operand indices of this instruction
@@ -821,6 +818,9 @@ class AsmParser {
// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
// written register name matcher
bit ShouldEmitMatchRegisterName = 1;
+
+ /// Does the instruction mnemonic allow '.'
+ bit MnemonicContainsDot = 0;
}
def DefaultAsmParser : AsmParser;