diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/llvm/CodeGen/LinkAllCodegenComponents.h | 10 | ||||
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 7 | ||||
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAGInstrs.h | 20 | ||||
-rw-r--r-- | include/llvm/CodeGen/ScheduleDAGSDNodes.h | 3 | ||||
-rw-r--r-- | include/llvm/CodeGen/SchedulerRegistry.h | 22 | ||||
-rw-r--r-- | include/llvm/CodeGen/SelectionDAGISel.h | 6 |
6 files changed, 31 insertions, 37 deletions
diff --git a/include/llvm/CodeGen/LinkAllCodegenComponents.h b/include/llvm/CodeGen/LinkAllCodegenComponents.h index 07aa8b7..74026a4 100644 --- a/include/llvm/CodeGen/LinkAllCodegenComponents.h +++ b/include/llvm/CodeGen/LinkAllCodegenComponents.h @@ -42,11 +42,11 @@ namespace { llvm::linkOcamlGC(); llvm::linkShadowStackGC(); - (void) llvm::createBURRListDAGScheduler(NULL, NULL, NULL, NULL, false); - (void) llvm::createTDRRListDAGScheduler(NULL, NULL, NULL, NULL, false); - (void) llvm::createTDListDAGScheduler(NULL, NULL, NULL, NULL, false); - (void) llvm::createFastDAGScheduler(NULL, NULL, NULL, NULL, false); - (void) llvm::createDefaultScheduler(NULL, NULL, NULL, NULL, false); + (void) llvm::createBURRListDAGScheduler(NULL, false); + (void) llvm::createTDRRListDAGScheduler(NULL, false); + (void) llvm::createTDListDAGScheduler(NULL, false); + (void) llvm::createFastDAGScheduler(NULL, false); + (void) llvm::createDefaultScheduler(NULL, false); } } ForceCodegenLinking; // Force link by creating a global definition. diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 765c26a..3fb266e 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -421,15 +421,14 @@ namespace llvm { const TargetInstrInfo *TII; // Target instruction information const TargetRegisterInfo *TRI; // Target processor register info TargetLowering *TLI; // Target lowering info - MachineFunction *MF; // Machine function + MachineFunction &MF; // Machine function MachineRegisterInfo &MRI; // Virtual/real register map MachineConstantPool *ConstPool; // Target constant pool std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s // represent noop instructions. std::vector<SUnit> SUnits; // The scheduling units. - ScheduleDAG(SelectionDAG *dag, MachineBasicBlock *bb, - const TargetMachine &tm); + explicit ScheduleDAG(MachineFunction &mf); virtual ~ScheduleDAG(); @@ -440,7 +439,7 @@ namespace llvm { /// Run - perform scheduling. /// - void Run(); + void Run(SelectionDAG *DAG, MachineBasicBlock *MBB); /// BuildSchedGraph - Build SUnits and set up their Preds and Succs /// to form the scheduling dependency graph. diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 96d3f0f..2e5d833 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -16,6 +16,7 @@ #define LLVM_CODEGEN_SCHEDULEDAGINSTRS_H #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/Target/TargetRegisterInfo.h" namespace llvm { class MachineLoopInfo; @@ -25,11 +26,22 @@ namespace llvm { const MachineLoopInfo &MLI; const MachineDominatorTree &MDT; + /// Defs, Uses - Remember where defs and uses of each physical register + /// are as we iterate upward through the instructions. This is allocated + /// here instead of inside BuildSchedGraph to avoid the need for it to be + /// initialized and destructed for each block. + std::vector<SUnit *> Defs[TargetRegisterInfo::FirstVirtualRegister]; + std::vector<SUnit *> Uses[TargetRegisterInfo::FirstVirtualRegister]; + + /// PendingLoads - Remember where unknown loads are after the most recent + /// unknown store, as we iterate. As with Defs and Uses, this is here + /// to minimize construction/destruction. + std::vector<SUnit *> PendingLoads; + public: - ScheduleDAGInstrs(MachineBasicBlock *bb, - const TargetMachine &tm, - const MachineLoopInfo &mli, - const MachineDominatorTree &mdt); + explicit ScheduleDAGInstrs(MachineFunction &mf, + const MachineLoopInfo &mli, + const MachineDominatorTree &mdt); virtual ~ScheduleDAGInstrs() {} diff --git a/include/llvm/CodeGen/ScheduleDAGSDNodes.h b/include/llvm/CodeGen/ScheduleDAGSDNodes.h index 65d96a9..6fc1493 100644 --- a/include/llvm/CodeGen/ScheduleDAGSDNodes.h +++ b/include/llvm/CodeGen/ScheduleDAGSDNodes.h @@ -74,8 +74,7 @@ namespace llvm { /// class ScheduleDAGSDNodes : public ScheduleDAG { public: - ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb, - const TargetMachine &tm); + explicit ScheduleDAGSDNodes(MachineFunction &mf); virtual ~ScheduleDAGSDNodes() {} diff --git a/include/llvm/CodeGen/SchedulerRegistry.h b/include/llvm/CodeGen/SchedulerRegistry.h index d7e39ae..b4daa05 100644 --- a/include/llvm/CodeGen/SchedulerRegistry.h +++ b/include/llvm/CodeGen/SchedulerRegistry.h @@ -32,9 +32,7 @@ class MachineBasicBlock; class RegisterScheduler : public MachinePassRegistryNode { public: - typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, SelectionDAG*, - const TargetMachine *, - MachineBasicBlock*, bool); + typedef ScheduleDAG *(*FunctionPassCtor)(SelectionDAGISel*, bool); static MachinePassRegistry Registry; @@ -66,44 +64,28 @@ public: /// createBURRListDAGScheduler - This creates a bottom up register usage /// reduction list scheduler. ScheduleDAG* createBURRListDAGScheduler(SelectionDAGISel *IS, - SelectionDAG *DAG, - const TargetMachine *TM, - MachineBasicBlock *BB, bool Fast); /// createTDRRListDAGScheduler - This creates a top down register usage /// reduction list scheduler. ScheduleDAG* createTDRRListDAGScheduler(SelectionDAGISel *IS, - SelectionDAG *DAG, - const TargetMachine *TM, - MachineBasicBlock *BB, bool Fast); /// createTDListDAGScheduler - This creates a top-down list scheduler with /// a hazard recognizer. ScheduleDAG* createTDListDAGScheduler(SelectionDAGISel *IS, - SelectionDAG *DAG, - const TargetMachine *TM, - MachineBasicBlock *BB, bool Fast); - + /// createFastDAGScheduler - This creates a "fast" scheduler. /// ScheduleDAG *createFastDAGScheduler(SelectionDAGISel *IS, - SelectionDAG *DAG, - const TargetMachine *TM, - MachineBasicBlock *BB, bool Fast); /// createDefaultScheduler - This creates an instruction scheduler appropriate /// for the target. ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS, - SelectionDAG *DAG, - const TargetMachine *TM, - MachineBasicBlock *BB, bool Fast); } // end namespace llvm - #endif diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h index 00219b2..072cb0c 100644 --- a/include/llvm/CodeGen/SelectionDAGISel.h +++ b/include/llvm/CodeGen/SelectionDAGISel.h @@ -41,9 +41,11 @@ namespace llvm { /// pattern-matching instruction selectors. class SelectionDAGISel : public FunctionPass { public: + const TargetMachine &TM; TargetLowering &TLI; - MachineRegisterInfo *RegInfo; FunctionLoweringInfo *FuncInfo; + MachineFunction *MF; + MachineRegisterInfo *RegInfo; SelectionDAG *CurDAG; SelectionDAGLowering *SDL; MachineBasicBlock *BB; @@ -52,7 +54,7 @@ public: bool Fast; static char ID; - explicit SelectionDAGISel(TargetLowering &tli, bool fast = false); + explicit SelectionDAGISel(TargetMachine &tm, bool fast = false); virtual ~SelectionDAGISel(); TargetLowering &getTargetLowering() { return TLI; } |