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-rw-r--r--lib/CodeGen/LiveIntervalUnion.h191
1 files changed, 99 insertions, 92 deletions
diff --git a/lib/CodeGen/LiveIntervalUnion.h b/lib/CodeGen/LiveIntervalUnion.h
index 38f6ac3..153ee2d 100644
--- a/lib/CodeGen/LiveIntervalUnion.h
+++ b/lib/CodeGen/LiveIntervalUnion.h
@@ -26,7 +26,7 @@ namespace llvm {
#ifndef NDEBUG
// forward declaration
template <unsigned Element> class SparseBitVector;
-typedef SparseBitVector<128> LvrBitSet;
+typedef SparseBitVector<128> LiveVirtRegBitSet;
#endif
/// A LiveSegment is a copy of a LiveRange object used within
@@ -37,52 +37,54 @@ typedef SparseBitVector<128> LvrBitSet;
/// interval within a virtual register's liveness. To limit confusion, in this
/// file we refer it as a live segment.
///
-/// Note: This currently represents a half-open interval [start,end).
+/// Note: This currently represents a half-open interval [Start,End).
/// If LiveRange is modified to represent a closed interval, so should this.
struct LiveSegment {
- SlotIndex start;
- SlotIndex end;
- LiveInterval *liveVirtReg;
+ SlotIndex Start;
+ SlotIndex End;
+ LiveInterval *VirtReg;
- LiveSegment(SlotIndex s, SlotIndex e, LiveInterval *lvr)
- : start(s), end(e), liveVirtReg(lvr) {}
+ LiveSegment(const LiveRange& LR, LiveInterval *VReg)
+ : Start(LR.start), End(LR.end), VirtReg(VReg) {}
- bool operator==(const LiveSegment &ls) const {
- return start == ls.start && end == ls.end && liveVirtReg == ls.liveVirtReg;
+ bool operator==(const LiveSegment &LS) const {
+ return Start == LS.Start && End == LS.End && VirtReg == LS.VirtReg;
}
- bool operator!=(const LiveSegment &ls) const {
- return !operator==(ls);
+ bool operator!=(const LiveSegment &LS) const {
+ return !operator==(LS);
}
// Order segments by starting point only--we expect them to be disjoint.
- bool operator<(const LiveSegment &ls) const { return start < ls.start; }
+ bool operator<(const LiveSegment &LS) const { return Start < LS.Start; }
void dump() const;
- void print(raw_ostream &os) const;
+ void print(raw_ostream &OS) const;
};
-inline bool operator<(SlotIndex V, const LiveSegment &ls) {
- return V < ls.start;
+inline bool operator<(SlotIndex Idx, const LiveSegment &LS) {
+ return Idx < LS.Start;
}
-inline bool operator<(const LiveSegment &ls, SlotIndex V) {
- return ls.start < V;
+inline bool operator<(const LiveSegment &LS, SlotIndex Idx) {
+ return LS.Start < Idx;
}
/// Compare a live virtual register segment to a LiveIntervalUnion segment.
-inline bool overlap(const LiveRange &lvrSeg, const LiveSegment &liuSeg) {
- return lvrSeg.start < liuSeg.end && liuSeg.start < lvrSeg.end;
+inline bool overlap(const LiveRange &VirtRegSegment,
+ const LiveSegment &LiveUnionSegment) {
+ return VirtRegSegment.start < LiveUnionSegment.End &&
+ LiveUnionSegment.Start < VirtRegSegment.end;
}
template <> struct isPodLike<LiveSegment> { static const bool value = true; };
-raw_ostream& operator<<(raw_ostream& os, const LiveSegment &ls);
+raw_ostream& operator<<(raw_ostream& OS, const LiveSegment &LS);
/// Abstraction to provide info for the representative register.
class AbstractRegisterDescription {
public:
- virtual const char *getName(unsigned reg) const = 0;
+ virtual const char *getName(unsigned Reg) const = 0;
virtual ~AbstractRegisterDescription() {}
};
@@ -92,7 +94,7 @@ public:
/// eventually make exceptions to handle value-based interference.
class LiveIntervalUnion {
// A set of live virtual register segments that supports fast insertion,
- // intersection, and removal.
+ // intersection, and removal.
//
// FIXME: std::set is a placeholder until we decide how to
// efficiently represent it. Probably need to roll our own B-tree.
@@ -103,7 +105,7 @@ class LiveIntervalUnion {
// This is traditionally known as a live range, but we refer is as a live
// virtual register to avoid confusing it with the misnamed LiveRange
// class.
- typedef std::vector<LiveInterval*> LiveVirtRegs;
+ typedef std::vector<LiveInterval*> LiveVRegs;
public:
// SegmentIter can advance to the next segment ordered by starting position
@@ -115,41 +117,41 @@ public:
class Query;
private:
- unsigned repReg_; // representative register number
- LiveSegments segments_; // union of virtual reg segements
+ unsigned RepReg; // representative register number
+ LiveSegments Segments; // union of virtual reg segements
public:
// default ctor avoids placement new
- LiveIntervalUnion() : repReg_(0) {}
+ LiveIntervalUnion() : RepReg(0) {}
// Initialize the union by associating it with a representative register
// number.
- void init(unsigned repReg) { repReg_ = repReg; }
+ void init(unsigned Reg) { RepReg = Reg; }
// Iterate over all segments in the union of live virtual registers ordered
// by their starting position.
- SegmentIter begin() { return segments_.begin(); }
- SegmentIter end() { return segments_.end(); }
+ SegmentIter begin() { return Segments.begin(); }
+ SegmentIter end() { return Segments.end(); }
// Return an iterator to the first segment after or including begin that
- // intersects with lvrSeg.
- SegmentIter upperBound(SegmentIter begin, const LiveSegment &seg);
+ // intersects with LS.
+ SegmentIter upperBound(SegmentIter SegBegin, const LiveSegment &LS);
// Add a live virtual register to this union and merge its segments.
- // Holds a nonconst reference to the LVR for later maniplution.
- void unify(LiveInterval &lvr);
+ // Holds a nonconst reference to the VirtReg for later maniplution.
+ void unify(LiveInterval &VirtReg);
// Remove a live virtual register's segments from this union.
- void extract(const LiveInterval &lvr);
+ void extract(const LiveInterval &VirtReg);
- void dump(const AbstractRegisterDescription *regInfo) const;
+ void dump(const AbstractRegisterDescription *RegDesc) const;
+
+ // If tri != NULL, use it to decode RepReg
+ void print(raw_ostream &OS, const AbstractRegisterDescription *RegDesc) const;
- // If tri != NULL, use it to decode repReg_
- void print(raw_ostream &os, const AbstractRegisterDescription *rdesc) const;
-
#ifndef NDEBUG
// Verify the live intervals in this union and add them to the visited set.
- void verify(LvrBitSet& visitedVRegs);
+ void verify(LiveVirtRegBitSet& VisitedVRegs);
#endif
/// Cache a single interference test result in the form of two intersecting
@@ -159,85 +161,89 @@ public:
class InterferenceResult {
friend class Query;
- LiveInterval::iterator lvrSegI_; // current position in _lvr
- SegmentIter liuSegI_; // current position in _liu
-
+ LiveInterval::iterator VirtRegI; // current position in VirtReg
+ SegmentIter LiveUnionI; // current position in LiveUnion
+
// Internal ctor.
- InterferenceResult(LiveInterval::iterator lvrSegI, SegmentIter liuSegI)
- : lvrSegI_(lvrSegI), liuSegI_(liuSegI) {}
+ InterferenceResult(LiveInterval::iterator VRegI, SegmentIter UnionI)
+ : VirtRegI(VRegI), LiveUnionI(UnionI) {}
public:
// Public default ctor.
- InterferenceResult(): lvrSegI_(), liuSegI_() {}
+ InterferenceResult(): VirtRegI(), LiveUnionI() {}
// Note: this interface provides raw access to the iterators because the
// result has no way to tell if it's valid to dereference them.
- // Access the lvr segment.
- LiveInterval::iterator lvrSegPos() const { return lvrSegI_; }
+ // Access the VirtReg segment.
+ LiveInterval::iterator virtRegPos() const { return VirtRegI; }
- // Access the liu segment.
- SegmentIter liuSegPos() const { return liuSegI_; }
+ // Access the LiveUnion segment.
+ SegmentIter liveUnionPos() const { return LiveUnionI; }
- bool operator==(const InterferenceResult &ir) const {
- return lvrSegI_ == ir.lvrSegI_ && liuSegI_ == ir.liuSegI_;
+ bool operator==(const InterferenceResult &IR) const {
+ return VirtRegI == IR.VirtRegI && LiveUnionI == IR.LiveUnionI;
}
- bool operator!=(const InterferenceResult &ir) const {
- return !operator==(ir);
+ bool operator!=(const InterferenceResult &IR) const {
+ return !operator==(IR);
}
};
/// Query interferences between a single live virtual register and a live
/// interval union.
class Query {
- LiveIntervalUnion *liu_;
- LiveInterval *lvr_;
- InterferenceResult firstInterference_;
- SmallVector<LiveInterval*,4> interferingVRegs_;
- bool seenUnspillableVReg_;
+ LiveIntervalUnion *LiveUnion;
+ LiveInterval *VirtReg;
+ InterferenceResult FirstInterference;
+ SmallVector<LiveInterval*,4> InterferingVRegs;
+ bool SeenAllInterferences;
+ bool SeenUnspillableVReg;
public:
- Query(): liu_(), lvr_() {}
+ Query(): LiveUnion(), VirtReg() {}
- Query(LiveInterval *lvr, LiveIntervalUnion *liu):
- liu_(liu), lvr_(lvr), seenUnspillableVReg_(false) {}
+ Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
+ LiveUnion(LIU), VirtReg(VReg), SeenAllInterferences(false),
+ SeenUnspillableVReg(false)
+ {}
void clear() {
- liu_ = NULL;
- lvr_ = NULL;
- firstInterference_ = InterferenceResult();
- interferingVRegs_.clear();
- seenUnspillableVReg_ = false;
+ LiveUnion = NULL;
+ VirtReg = NULL;
+ FirstInterference = InterferenceResult();
+ InterferingVRegs.clear();
+ SeenAllInterferences = false;
+ SeenUnspillableVReg = false;
}
-
- void init(LiveInterval *lvr, LiveIntervalUnion *liu) {
- if (lvr_ == lvr) {
+
+ void init(LiveInterval *VReg, LiveIntervalUnion *LIU) {
+ if (VirtReg == VReg) {
// We currently allow query objects to be reused acrossed live virtual
// registers, but always for the same live interval union.
- assert(liu_ == liu && "inconsistent initialization");
+ assert(LiveUnion == LIU && "inconsistent initialization");
// Retain cached results, e.g. firstInterference.
return;
}
- liu_ = liu;
- lvr_ = lvr;
- // Clear cached results.
- firstInterference_ = InterferenceResult();
- interferingVRegs_.clear();
- seenUnspillableVReg_ = false;
+ clear();
+ LiveUnion = LIU;
+ VirtReg = VReg;
}
- LiveInterval &lvr() const { assert(lvr_ && "uninitialized"); return *lvr_; }
+ LiveInterval &virtReg() const {
+ assert(VirtReg && "uninitialized");
+ return *VirtReg;
+ }
- bool isInterference(const InterferenceResult &ir) const {
- if (ir.lvrSegI_ != lvr_->end()) {
- assert(overlap(*ir.lvrSegI_, *ir.liuSegI_) &&
+ bool isInterference(const InterferenceResult &IR) const {
+ if (IR.VirtRegI != VirtReg->end()) {
+ assert(overlap(*IR.VirtRegI, *IR.LiveUnionI) &&
"invalid segment iterators");
return true;
}
return false;
}
- // Does this live virtual register interfere with the union.
+ // Does this live virtual register interfere with the union?
bool checkInterference() { return isInterference(firstInterference()); }
// Get the first pair of interfering segments, or a noninterfering result.
@@ -246,32 +252,33 @@ public:
// Treat the result as an iterator and advance to the next interfering pair
// of segments. Visiting each unique interfering pairs means that the same
- // lvr or liu segment may be visited multiple times.
- bool nextInterference(InterferenceResult &ir) const;
+ // VirtReg or LiveUnion segment may be visited multiple times.
+ bool nextInterference(InterferenceResult &IR) const;
// Count the virtual registers in this union that interfere with this
// query's live virtual register, up to maxInterferingRegs.
- unsigned collectInterferingVRegs(unsigned maxInterferingRegs = UINT_MAX);
+ unsigned collectInterferingVRegs(unsigned MaxInterferingRegs = UINT_MAX);
// Was this virtual register visited during collectInterferingVRegs?
- bool isSeenInterference(LiveInterval *lvr) const;
+ bool isSeenInterference(LiveInterval *VReg) const;
+
+ // Did collectInterferingVRegs collect all interferences?
+ bool seenAllInterferences() const { return SeenAllInterferences; }
// Did collectInterferingVRegs encounter an unspillable vreg?
- bool seenUnspillableVReg() const {
- return seenUnspillableVReg_;
- }
+ bool seenUnspillableVReg() const { return SeenUnspillableVReg; }
// Vector generated by collectInterferingVRegs.
const SmallVectorImpl<LiveInterval*> &interferingVRegs() const {
- return interferingVRegs_;
+ return InterferingVRegs;
}
-
+
private:
Query(const Query&); // DO NOT IMPLEMENT
void operator=(const Query&); // DO NOT IMPLEMENT
-
+
// Private interface for queries
- void findIntersection(InterferenceResult &ir) const;
+ void findIntersection(InterferenceResult &IR) const;
};
};
generated by cgit v1.1 at 2025-05-14 23:50:27 +0000