diff options
Diffstat (limited to 'lib/CodeGen/RegAllocFast.cpp')
| -rw-r--r-- | lib/CodeGen/RegAllocFast.cpp | 56 |
1 files changed, 35 insertions, 21 deletions
diff --git a/lib/CodeGen/RegAllocFast.cpp b/lib/CodeGen/RegAllocFast.cpp index 8f6496d..ede5dc4 100644 --- a/lib/CodeGen/RegAllocFast.cpp +++ b/lib/CodeGen/RegAllocFast.cpp @@ -48,7 +48,10 @@ namespace { public: static char ID; RAFast() : MachineFunctionPass(ID), StackSlotForVirtReg(-1), - isBulkSpilling(false) {} + isBulkSpilling(false) { + initializePHIEliminationPass(*PassRegistry::getPassRegistry()); + initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry()); + } private: const TargetMachine *TM; MachineFunction *MF; @@ -113,9 +116,9 @@ namespace { // Allocatable - vector of allocatable physical registers. BitVector Allocatable; - // SkippedInstrs - Descriptors of instructions whose clobber list was ignored - // because all registers were spilled. It is still necessary to mark all the - // clobbered registers as used by the function. + // SkippedInstrs - Descriptors of instructions whose clobber list was + // ignored because all registers were spilled. It is still necessary to + // mark all the clobbered registers as used by the function. SmallPtrSet<const TargetInstrDesc*, 4> SkippedInstrs; // isBulkSpilling - This flag is set when LiveRegMap will be cleared @@ -267,11 +270,11 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); ++NumStores; // Update statistics - // If this register is used by DBG_VALUE then insert new DBG_VALUE to + // If this register is used by DBG_VALUE then insert new DBG_VALUE to // identify spilled location as the place to find corresponding variable's // value. if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) { - const MDNode *MDPtr = + const MDNode *MDPtr = DBG->getOperand(DBG->getNumOperands()-1).getMetadata(); int64_t Offset = 0; if (DBG->getOperand(1).isImm()) @@ -284,7 +287,7 @@ void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, } else DL = MI->getDebugLoc(); - if (MachineInstr *NewDV = + if (MachineInstr *NewDV = TII->emitFrameIndexDebugValue(*MF, FI, Offset, MDPtr, DL)) { MachineBasicBlock *MBB = DBG->getParent(); MBB->insert(MI, NewDV); @@ -498,7 +501,8 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { // First try to find a completely free register. for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { unsigned PhysReg = *I; - if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) + if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && + Allocatable.test(PhysReg)) return assignVirtToPhysReg(LRE, PhysReg); } @@ -507,6 +511,8 @@ void RAFast::allocVirtReg(MachineInstr *MI, LiveRegEntry &LRE, unsigned Hint) { unsigned BestReg = 0, BestCost = spillImpossible; for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + if (!Allocatable.test(*I)) + continue; unsigned Cost = calcSpillCost(*I); // Cost is 0 when all aliases are already disabled. if (Cost == 0) @@ -736,7 +742,8 @@ void RAFast::AllocateBasicBlock() { // Add live-in registers as live. for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), E = MBB->livein_end(); I != E; ++I) - definePhysReg(MII, *I, regReserved); + if (Allocatable.test(*I)) + definePhysReg(MII, *I, regReserved); SmallVector<unsigned, 8> VirtDead; SmallVector<MachineInstr*, 32> Coalesced; @@ -794,25 +801,32 @@ void RAFast::AllocateBasicBlock() { setPhysReg(MI, i, LRI->second.PhysReg); else { int SS = StackSlotForVirtReg[Reg]; - if (SS == -1) - MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry! + if (SS == -1) { + // We can't allocate a physreg for a DebugValue, sorry! + DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); + MO.setReg(0); + } else { // Modify DBG_VALUE now that the value is in a spill slot. int64_t Offset = MI->getOperand(1).getImm(); - const MDNode *MDPtr = + const MDNode *MDPtr = MI->getOperand(MI->getNumOperands()-1).getMetadata(); DebugLoc DL = MI->getDebugLoc(); - if (MachineInstr *NewDV = + if (MachineInstr *NewDV = TII->emitFrameIndexDebugValue(*MF, SS, Offset, MDPtr, DL)) { - DEBUG(dbgs() << "Modifying debug info due to spill:" << "\t" << *MI); + DEBUG(dbgs() << "Modifying debug info due to spill:" << + "\t" << *MI); MachineBasicBlock *MBB = MI->getParent(); MBB->insert(MBB->erase(MI), NewDV); // Scan NewDV operands from the beginning. MI = NewDV; ScanDbgValue = true; break; - } else - MO.setReg(0); // We can't allocate a physreg for a DebugValue, sorry! + } else { + // We can't allocate a physreg for a DebugValue; sorry! + DEBUG(dbgs() << "Unable to allocate vreg used by DBG_VALUE"); + MO.setReg(0); + } } } } @@ -875,8 +889,8 @@ void RAFast::AllocateBasicBlock() { // operands. If there are also physical defs, these registers must avoid // both physical defs and uses, making them more constrained than normal // operands. - // Similarly, if there are multiple defs and tied operands, we must make sure - // the same register is allocated to uses and defs. + // Similarly, if there are multiple defs and tied operands, we must make + // sure the same register is allocated to uses and defs. // We didn't detect inline asm tied operands above, so just make this extra // pass for all inline asm. if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || @@ -927,9 +941,9 @@ void RAFast::AllocateBasicBlock() { unsigned DefOpEnd = MI->getNumOperands(); if (TID.isCall()) { // Spill all virtregs before a call. This serves two purposes: 1. If an - // exception is thrown, the landing pad is going to expect to find registers - // in their spill slots, and 2. we don't have to wade through all the - // <imp-def> operands on the call instruction. + // exception is thrown, the landing pad is going to expect to find + // registers in their spill slots, and 2. we don't have to wade through + // all the <imp-def> operands on the call instruction. DefOpEnd = VirtOpEnd; DEBUG(dbgs() << " Spilling remaining registers before call.\n"); spillAll(MI); |