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-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp464
1 files changed, 232 insertions, 232 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 31cbdb9..d957bf9 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -215,12 +215,12 @@ namespace {
SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
SDOperand N3, ISD::CondCode CC,
bool NotExtCompare = false);
- SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
+ SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
- SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT);
- SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
+ SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
+ SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
@@ -482,7 +482,7 @@ static bool isOneUseSetCC(SDOperand N) {
}
SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
@@ -887,7 +887,7 @@ SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) {
static
SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
SDOperand N00 = N0.getOperand(0);
SDOperand N01 = N0.getOperand(1);
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
@@ -904,7 +904,7 @@ SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
static
SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
SelectionDAG &DAG) {
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
unsigned Opc = N->getOpcode();
bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
@@ -930,8 +930,8 @@ SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
cast<ConstantSDNode>(RHS)->isNullValue()) {
std::swap(LHS, RHS);
SDOperand Op0 = Slct.getOperand(0);
- bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
- : Op0.getOperand(0).getValueType());
+ bool isInt = (isSlctCC ? Op0.getValueType() :
+ Op0.getOperand(0).getValueType()).isInteger();
CC = ISD::getSetCCInverse(CC, isInt);
DoXform = true;
InvCC = true;
@@ -956,10 +956,10 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1001,14 +1001,14 @@ SDOperand DAGCombiner::visitADD(SDNode *N) {
if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
return N1.getOperand(0);
- if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
+ if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (a+b) -> (a|b) iff a and b share no bits.
- if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
+ if (VT.isInteger() && !VT.isVector()) {
APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne;
- APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+ APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
@@ -1049,7 +1049,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// If the flag result is dead, turn this into an ADD.
if (N->hasNUsesOfValue(0, 1))
@@ -1069,7 +1069,7 @@ SDOperand DAGCombiner::visitADDC(SDNode *N) {
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne;
- APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+ APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
@@ -1091,7 +1091,7 @@ SDOperand DAGCombiner::visitADDE(SDNode *N) {
SDOperand CarryIn = N->getOperand(2);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- //MVT::ValueType VT = N0.getValueType();
+ //MVT VT = N0.getValueType();
// canonicalize constant to RHS
if (N0C && !N1C) {
@@ -1115,10 +1115,10 @@ SDOperand DAGCombiner::visitSUB(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1158,10 +1158,10 @@ SDOperand DAGCombiner::visitMUL(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1242,10 +1242,10 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1261,7 +1261,7 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
// If we know the sign bits of both operands are zero, strength reduce to a
// udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
- if (!MVT::isVector(VT)) {
+ if (!VT.isVector()) {
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
}
@@ -1278,12 +1278,12 @@ SDOperand DAGCombiner::visitSDIV(SDNode *N) {
unsigned lg2 = Log2_64(abs2);
// Splat the sign bit into the register
SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
- DAG.getConstant(MVT::getSizeInBits(VT)-1,
+ DAG.getConstant(VT.getSizeInBits()-1,
TLI.getShiftAmountTy()));
AddToWorkList(SGN.Val);
// Add (N0 < 0) ? abs2 - 1 : 0;
SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
- DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
+ DAG.getConstant(VT.getSizeInBits()-lg2,
TLI.getShiftAmountTy()));
SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
AddToWorkList(SRL.Val);
@@ -1320,10 +1320,10 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1340,7 +1340,7 @@ SDOperand DAGCombiner::visitUDIV(SDNode *N) {
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
- MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
+ MVT ADDVT = N1.getOperand(1).getValueType();
SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
DAG.getConstant(SHC->getAPIntValue()
.logBase2(),
@@ -1371,14 +1371,14 @@ SDOperand DAGCombiner::visitSREM(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (srem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
return DAG.getNode(ISD::SREM, VT, N0, N1);
// If we know the sign bits of both operands are zero, strength reduce to a
// urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
- if (!MVT::isVector(VT)) {
+ if (!VT.isVector()) {
if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
return DAG.getNode(ISD::UREM, VT, N0, N1);
}
@@ -1412,7 +1412,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (urem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
@@ -1427,7 +1427,7 @@ SDOperand DAGCombiner::visitUREM(SDNode *N) {
if (SHC->getAPIntValue().isPowerOf2()) {
SDOperand Add =
DAG.getNode(ISD::ADD, VT, N1,
- DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)),
+ DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
VT));
AddToWorkList(Add.Val);
return DAG.getNode(ISD::AND, VT, N0, Add);
@@ -1462,7 +1462,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (mulhs x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1470,7 +1470,7 @@ SDOperand DAGCombiner::visitMULHS(SDNode *N) {
// fold (mulhs x, 1) -> (sra x, size(x)-1)
if (N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
- DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
+ DAG.getConstant(N0.getValueType().getSizeInBits()-1,
TLI.getShiftAmountTy()));
// fold (mulhs x, undef) -> 0
if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
@@ -1483,7 +1483,7 @@ SDOperand DAGCombiner::visitMULHU(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (mulhu x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1583,7 +1583,7 @@ SDOperand DAGCombiner::visitUDIVREM(SDNode *N) {
/// two operands of the same opcode, try to simplify it.
SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
// For each of OP in AND/OR/XOR:
@@ -1624,11 +1624,11 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
SDOperand LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N1.getValueType();
- unsigned BitWidth = MVT::getSizeInBits(VT);
+ MVT VT = N1.getValueType();
+ unsigned BitWidth = VT.getSizeInBits();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1683,7 +1683,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
- MVT::isInteger(LL.getValueType())) {
+ LL.getValueType().isInteger()) {
// fold (X == 0) & (Y == 0) -> (X|Y == 0)
if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) {
SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
@@ -1709,7 +1709,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
std::swap(RL, RR);
}
if (LL == RL && LR == RR) {
- bool isInteger = MVT::isInteger(LL.getValueType());
+ bool isInteger = LL.getValueType().isInteger();
ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
if (Result != ISD::SETCC_INVALID)
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
@@ -1724,18 +1724,18 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
// fold (and (sra)) -> (and (srl)) when possible.
- if (!MVT::isVector(VT) &&
+ if (!VT.isVector() &&
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getMemoryVT();
+ MVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - MVT::getSizeInBits(EVT))) &&
+ BitWidth - EVT.getSizeInBits())) &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
@@ -1751,12 +1751,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getMemoryVT();
+ MVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
- BitWidth - MVT::getSizeInBits(EVT))) &&
+ BitWidth - EVT.getSizeInBits())) &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
@@ -1775,7 +1775,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
if (LN0->getExtensionType() != ISD::SEXTLOAD &&
LN0->isUnindexed() && N0.hasOneUse()) {
- MVT::ValueType EVT, LoadedVT;
+ MVT EVT, LoadedVT;
if (N1C->getAPIntValue() == 255)
EVT = MVT::i8;
else if (N1C->getAPIntValue() == 65535)
@@ -1788,12 +1788,12 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
LoadedVT = LN0->getMemoryVT();
if (EVT != MVT::Other && LoadedVT > EVT &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
- MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+ MVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
// load the correct bytes. For little endian systems, we merely need to
// read fewer bytes from the same pointer.
- unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
- unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
+ unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
+ unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
unsigned Alignment = LN0->getAlignment();
SDOperand NewPtr = LN0->getBasePtr();
@@ -1823,10 +1823,10 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
SDOperand LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N1.getValueType();
+ MVT VT = N1.getValueType();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -1868,7 +1868,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
- MVT::isInteger(LL.getValueType())) {
+ LL.getValueType().isInteger()) {
// fold (X != 0) | (Y != 0) -> (X|Y != 0)
// fold (X < 0) | (Y < 0) -> (X|Y < 0)
if (cast<ConstantSDNode>(LR)->isNullValue() &&
@@ -1892,7 +1892,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
std::swap(RL, RR);
}
if (LL == RL && LR == RR) {
- bool isInteger = MVT::isInteger(LL.getValueType());
+ bool isInteger = LL.getValueType().isInteger();
ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
if (Result != ISD::SETCC_INVALID)
return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
@@ -1959,7 +1959,7 @@ static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) {
// a rot[lr].
SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
// Must be a legal type. Expanded an promoted things won't work with rotates.
- MVT::ValueType VT = LHS.getValueType();
+ MVT VT = LHS.getValueType();
if (!TLI.isTypeLegal(VT)) return 0;
// The target must have at least one rotate flavor.
@@ -1991,7 +1991,7 @@ SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
std::swap(LHSMask , RHSMask );
}
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ unsigned OpSizeInBits = VT.getSizeInBits();
SDOperand LHSShiftArg = LHSShift.getOperand(0);
SDOperand LHSShiftAmt = LHSShift.getOperand(1);
SDOperand RHSShiftAmt = RHSShift.getOperand(1);
@@ -2115,10 +2115,10 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
SDOperand LHS, RHS, CC;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -2146,7 +2146,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
return RXOR;
// fold !(x cc y) -> (x !cc y)
if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
- bool isInt = MVT::isInteger(LHS.getValueType());
+ bool isInt = LHS.getValueType().isInteger();
ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
isInt);
if (N0.getOpcode() == ISD::SETCC)
@@ -2205,12 +2205,12 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
}
// fold (xor x, x) -> 0
if (N0 == N1) {
- if (!MVT::isVector(VT)) {
+ if (!VT.isVector()) {
return DAG.getConstant(0, VT);
} else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
// Produce a vector of zeros.
- SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
- std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El);
+ SDOperand El = DAG.getConstant(0, VT.getVectorElementType());
+ std::vector<SDOperand> Ops(VT.getVectorNumElements(), El);
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
}
@@ -2222,7 +2222,7 @@ SDOperand DAGCombiner::visitXOR(SDNode *N) {
}
// Simplify the expression using non-local knowledge.
- if (!MVT::isVector(VT) &&
+ if (!VT.isVector() &&
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
@@ -2274,7 +2274,7 @@ SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) {
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
return SDOperand();
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// If this is a signed shift right, and the high bit is modified
// by the logical operation, do not perform the transformation.
@@ -2305,8 +2305,8 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ MVT VT = N0.getValueType();
+ unsigned OpSizeInBits = VT.getSizeInBits();
// fold (shl c1, c2) -> c1<<c2
if (N0C && N1C)
@@ -2322,7 +2322,7 @@ SDOperand DAGCombiner::visitSHL(SDNode *N) {
return N0;
// if (shl x, c) is known to be zero, return 0
if (DAG.MaskedValueIsZero(SDOperand(N, 0),
- APInt::getAllOnesValue(MVT::getSizeInBits(VT))))
+ APInt::getAllOnesValue(VT.getSizeInBits())))
return DAG.getConstant(0, VT);
if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
@@ -2364,7 +2364,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
+ MVT VT = N0.getValueType();
// fold (sra c1, c2) -> c1>>c2
if (N0C && N1C)
@@ -2376,7 +2376,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
if (N0C && N0C->isAllOnesValue())
return N0;
// fold (sra x, c >= size(x)) -> undef
- if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
+ if (N1C && N1C->getValue() >= VT.getSizeInBits())
return DAG.getNode(ISD::UNDEF, VT);
// fold (sra x, 0) -> x
if (N1C && N1C->isNullValue())
@@ -2384,8 +2384,8 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
// fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
// sext_inreg.
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
- unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
- MVT::ValueType EVT;
+ unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
+ MVT EVT;
switch (LowBits) {
default: EVT = MVT::Other; break;
case 1: EVT = MVT::i1; break;
@@ -2402,7 +2402,7 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
if (N1C && N0.getOpcode() == ISD::SRA) {
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
unsigned Sum = N1C->getValue() + C1->getValue();
- if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
+ if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
DAG.getConstant(Sum, N1C->getValueType(0)));
}
@@ -2418,8 +2418,9 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
if (N01C && N1C) {
// Determine what the truncate's result bitsize and type would be.
- unsigned VTValSize = MVT::getSizeInBits(VT);
- MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
+ unsigned VTValSize = VT.getSizeInBits();
+ MVT TruncVT =
+ MVT::getIntegerVT(VTValSize - N1C->getValue());
// Determine the residual right-shift amount.
unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
@@ -2458,8 +2459,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT::ValueType VT = N0.getValueType();
- unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ MVT VT = N0.getValueType();
+ unsigned OpSizeInBits = VT.getSizeInBits();
// fold (srl c1, c2) -> c1 >>u c2
if (N0C && N1C)
@@ -2492,8 +2493,8 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
- MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
- if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
+ MVT SmallVT = N0.getOperand(0).getValueType();
+ if (N1C->getValue() >= SmallVT.getSizeInBits())
return DAG.getNode(ISD::UNDEF, VT);
SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
@@ -2503,16 +2504,16 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
// fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
// bit, which is unmodified by sra.
- if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
+ if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
if (N0.getOpcode() == ISD::SRA)
return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
}
// fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
if (N1C && N0.getOpcode() == ISD::CTLZ &&
- N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) {
+ N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
APInt KnownZero, KnownOne;
- APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
+ APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
// If any of the input bits are KnownOne, then the input couldn't be all
@@ -2551,7 +2552,7 @@ SDOperand DAGCombiner::visitSRL(SDNode *N) {
SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (ctlz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2561,7 +2562,7 @@ SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (cttz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2571,7 +2572,7 @@ SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (ctpop c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2586,8 +2587,8 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
- MVT::ValueType VT = N->getValueType(0);
- MVT::ValueType VT0 = N0.getValueType();
+ MVT VT = N->getValueType(0);
+ MVT VT0 = N0.getValueType();
// fold select C, X, X -> X
if (N1 == N2)
@@ -2599,16 +2600,16 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
if (N0C && N0C->isNullValue())
return N2;
// fold select C, 1, X -> C | X
- if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1)
+ if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::OR, VT, N0, N2);
// fold select C, 0, 1 -> ~C
- if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
+ if (VT.isInteger() && VT0.isInteger() &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
if (VT == VT0)
return XORNode;
AddToWorkList(XORNode.Val);
- if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
+ if (VT.getSizeInBits() > VT0.getSizeInBits())
return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
}
@@ -2626,13 +2627,13 @@ SDOperand DAGCombiner::visitSELECT(SDNode *N) {
}
// fold select C, X, 0 -> C & X
// FIXME: this should check for C type == X type, not i1?
- if (MVT::i1 == VT && N2C && N2C->isNullValue())
+ if (VT == MVT::i1 && N2C && N2C->isNullValue())
return DAG.getNode(ISD::AND, VT, N0, N1);
// fold X ? X : Y --> X ? 1 : Y --> X | Y
- if (MVT::i1 == VT && N0 == N1)
+ if (VT == MVT::i1 && N0 == N1)
return DAG.getNode(ISD::OR, VT, N0, N2);
// fold X ? Y : X --> X ? Y : 0 --> X & Y
- if (MVT::i1 == VT && N0 == N2)
+ if (VT == MVT::i1 && N0 == N2)
return DAG.getNode(ISD::AND, VT, N0, N1);
// If we can fold this based on the true/false value, do so.
@@ -2766,7 +2767,7 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0,
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (sext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -2790,9 +2791,9 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// See if the value being truncated is already sign extended. If so, just
// eliminate the trunc/sext pair.
SDOperand Op = N0.getOperand(0);
- unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
- unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
- unsigned DestBits = MVT::getSizeInBits(VT);
+ unsigned OpBits = Op.getValueType().getSizeInBits();
+ unsigned MidBits = N0.getValueType().getSizeInBits();
+ unsigned DestBits = VT.getSizeInBits();
unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
if (OpBits == DestBits) {
@@ -2866,7 +2867,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getMemoryVT();
+ MVT EVT = LN0->getMemoryVT();
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
@@ -2899,7 +2900,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (zext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -2943,7 +2944,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
X = DAG.getNode(ISD::TRUNCATE, VT, X);
}
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
- Mask.zext(MVT::getSizeInBits(VT));
+ Mask.zext(VT.getSizeInBits());
return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
}
@@ -2989,7 +2990,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getMemoryVT();
+ MVT EVT = LN0->getMemoryVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT,
@@ -3015,7 +3016,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (aext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3060,7 +3061,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
X = DAG.getNode(ISD::TRUNCATE, VT, X);
}
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
- Mask.zext(MVT::getSizeInBits(VT));
+ Mask.zext(VT.getSizeInBits());
return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
}
@@ -3087,7 +3088,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
!ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType EVT = LN0->getMemoryVT();
+ MVT EVT = LN0->getMemoryVT();
SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
@@ -3154,8 +3155,8 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
unsigned Opc = N->getOpcode();
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
- MVT::ValueType EVT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
+ MVT EVT = N->getValueType(0);
// Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
// extended to VT.
@@ -3166,7 +3167,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
return SDOperand();
}
- unsigned EVTBits = MVT::getSizeInBits(EVT);
+ unsigned EVTBits = EVT.getSizeInBits();
unsigned ShAmt = 0;
bool CombineSRL = false;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
@@ -3175,7 +3176,7 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
// Is the shift amount a multiple of size of VT?
if ((ShAmt & (EVTBits-1)) == 0) {
N0 = N0.getOperand(0);
- if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
+ if (N0.getValueType().getSizeInBits() <= EVTBits)
return SDOperand();
CombineSRL = true;
}
@@ -3188,15 +3189,15 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
// that it is already zero extended.
// FIXME: This should be reevaluated.
VT != MVT::i1) {
- assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
+ assert(N0.getValueType().getSizeInBits() > EVTBits &&
"Cannot truncate to larger type!");
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+ MVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to adjust the offset to the pointer to
// load the correct bytes.
if (TLI.isBigEndian()) {
- unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
- unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
+ unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits();
+ unsigned EVTStoreBits = EVT.getStoreSizeInBits();
ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
}
uint64_t PtrOff = ShAmt / 8;
@@ -3235,17 +3236,17 @@ SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
- MVT::ValueType VT = N->getValueType(0);
- MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
- unsigned VTBits = MVT::getSizeInBits(VT);
- unsigned EVTBits = MVT::getSizeInBits(EVT);
+ MVT VT = N->getValueType(0);
+ MVT EVT = cast<VTSDNode>(N1)->getVT();
+ unsigned VTBits = VT.getSizeInBits();
+ unsigned EVTBits = EVT.getSizeInBits();
// fold (sext_in_reg c1) -> c1
if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
// If the input is already sign extended, just drop the extension.
- if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
+ if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
return N0;
// fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
@@ -3274,11 +3275,11 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
if (N0.getOpcode() == ISD::SRL) {
if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
- if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
+ if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
// We can turn this into an SRA iff the input to the SRL is already sign
// extended enough.
unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
- if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
+ if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
}
}
@@ -3318,7 +3319,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// noop truncate
if (N0.getValueType() == N->getValueType(0))
@@ -3349,7 +3350,7 @@ SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
// -> trunc y
SDOperand Shorter =
GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
- MVT::getSizeInBits(VT)));
+ VT.getSizeInBits()));
if (Shorter.Val)
return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
@@ -3367,22 +3368,22 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) {
/// CombineConsecutiveLoads - build_pair (load, load) -> load
/// if load locations are consecutive.
-SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) {
+SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
assert(N->getOpcode() == ISD::BUILD_PAIR);
SDNode *LD1 = getBuildPairElt(N, 0);
if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
return SDOperand();
- MVT::ValueType LD1VT = LD1->getValueType(0);
+ MVT LD1VT = LD1->getValueType(0);
SDNode *LD2 = getBuildPairElt(N, 1);
const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (ISD::isNON_EXTLoad(LD2) &&
LD2->hasOneUse() &&
- TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) {
+ TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
LoadSDNode *LD = cast<LoadSDNode>(LD1);
unsigned Align = LD->getAlignment();
unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(VT));
+ getABITypeAlignment(VT.getTypeForMVT());
if ((!AfterLegalize || TLI.isTypeLegal(VT)) &&
TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align)
return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(),
@@ -3394,7 +3395,7 @@ SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) {
SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// If the input is a BUILD_VECTOR with all constant elements, fold this now.
// Only do this before legalize, since afterward the target may be depending
@@ -3402,7 +3403,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
// First check to see if this is all constant.
if (!AfterLegalize &&
N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
- MVT::isVector(VT)) {
+ VT.isVector()) {
bool isSimple = true;
for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
@@ -3412,8 +3413,8 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
break;
}
- MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
- assert(!MVT::isVector(DestEltVT) &&
+ MVT DestEltVT = N->getValueType(0).getVectorElementType();
+ assert(!DestEltVT.isVector() &&
"Element type of vector ValueType must not be vector!");
if (isSimple) {
return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
@@ -3435,7 +3436,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(VT));
+ getABITypeAlignment(VT.getTypeForMVT());
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
@@ -3452,11 +3453,11 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
// Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
// This often reduces constant pool loads.
if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
- N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) {
+ N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
AddToWorkList(NewConv.Val);
- APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
+ APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
if (N0.getOpcode() == ISD::FNEG)
return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
assert(N0.getOpcode() == ISD::FABS);
@@ -3468,14 +3469,15 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
// to an fneg or fabs.
if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
isa<ConstantFPSDNode>(N0.getOperand(0)) &&
- MVT::isInteger(VT) && !MVT::isVector(VT)) {
- unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType());
- SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth),
+ VT.isInteger() && !VT.isVector()) {
+ unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
+ SDOperand X = DAG.getNode(ISD::BIT_CONVERT,
+ MVT::getIntegerVT(OrigXWidth),
N0.getOperand(1));
AddToWorkList(X.Val);
// If X has a different width than the result/lhs, sext it or truncate it.
- unsigned VTWidth = MVT::getSizeInBits(VT);
+ unsigned VTWidth = VT.getSizeInBits();
if (OrigXWidth < VTWidth) {
X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
AddToWorkList(X.Val);
@@ -3489,7 +3491,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
AddToWorkList(X.Val);
}
- APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
+ APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
AddToWorkList(X.Val);
@@ -3511,7 +3513,7 @@ SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
}
SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) {
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
return CombineConsecutiveLoads(N, VT);
}
@@ -3519,14 +3521,14 @@ SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) {
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type.
SDOperand DAGCombiner::
-ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
- MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType();
+ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
+ MVT SrcEltVT = BV->getOperand(0).getValueType();
// If this is already the right type, we're done.
if (SrcEltVT == DstEltVT) return SDOperand(BV, 0);
- unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT);
- unsigned DstBitSize = MVT::getSizeInBits(DstEltVT);
+ unsigned SrcBitSize = SrcEltVT.getSizeInBits();
+ unsigned DstBitSize = DstEltVT.getSizeInBits();
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP<->INT cases.
@@ -3536,29 +3538,28 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i)));
AddToWorkList(Ops.back().Val);
}
- MVT::ValueType VT =
- MVT::getVectorType(DstEltVT,
- MVT::getVectorNumElements(BV->getValueType(0)));
+ MVT VT = MVT::getVectorVT(DstEltVT,
+ BV->getValueType(0).getVectorNumElements());
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
// Otherwise, we're growing or shrinking the elements. To avoid having to
// handle annoying details of growing/shrinking FP values, we convert them to
// int first.
- if (MVT::isFloatingPoint(SrcEltVT)) {
+ if (SrcEltVT.isFloatingPoint()) {
// Convert the input float vector to a int vector where the elements are the
// same sizes.
assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
- MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+ MVT IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val;
SrcEltVT = IntVT;
}
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
- if (MVT::isFloatingPoint(DstEltVT)) {
+ if (DstEltVT.isFloatingPoint()) {
assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
- MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
+ MVT TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64;
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val;
// Next, convert to FP elements of the same size.
@@ -3567,7 +3568,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
// Okay, we know the src/dst types are both integers of differing types.
// Handling growing first.
- assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT));
+ assert(SrcEltVT.isInteger() && DstEltVT.isInteger());
if (SrcBitSize < DstBitSize) {
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
@@ -3594,7 +3595,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
}
- MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size());
+ MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
@@ -3602,8 +3603,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) {
// turns into multiple outputs.
bool isS2V = ISD::isScalarToVector(BV);
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
- MVT::ValueType VT = MVT::getVectorType(DstEltVT,
- NumOutputsPerInput * BV->getNumOperands());
+ MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
SmallVector<SDOperand, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
if (BV->getOperand(i).getOpcode() == ISD::UNDEF) {
@@ -3635,10 +3635,10 @@ SDOperand DAGCombiner::visitFADD(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3672,10 +3672,10 @@ SDOperand DAGCombiner::visitFSUB(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3702,10 +3702,10 @@ SDOperand DAGCombiner::visitFMUL(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3749,10 +3749,10 @@ SDOperand DAGCombiner::visitFDIV(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold vector ops
- if (MVT::isVector(VT)) {
+ if (VT.isVector()) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
@@ -3782,7 +3782,7 @@ SDOperand DAGCombiner::visitFREM(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (frem c1, c2) -> fmod(c1,c2)
if (N0CFP && N1CFP && VT != MVT::ppcf128)
@@ -3796,7 +3796,7 @@ SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1);
@@ -3839,7 +3839,7 @@ SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) {
SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (sint_to_fp c1) -> c1fp
if (N0C && N0.getValueType() != MVT::ppcf128)
@@ -3850,7 +3850,7 @@ SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (uint_to_fp c1) -> c1fp
if (N0C && N0.getValueType() != MVT::ppcf128)
@@ -3861,7 +3861,7 @@ SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
@@ -3872,7 +3872,7 @@ SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
if (N0CFP && VT != MVT::ppcf128)
@@ -3884,7 +3884,7 @@ SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
if (N0CFP && N0.getValueType() != MVT::ppcf128)
@@ -3915,8 +3915,8 @@ SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
SDOperand N0 = N->getOperand(0);
- MVT::ValueType VT = N->getValueType(0);
- MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ MVT VT = N->getValueType(0);
+ MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
// fold (fp_round_inreg c1fp) -> c1fp
@@ -3930,7 +3930,7 @@ SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
if (N->hasOneUse() &&
@@ -3981,13 +3981,13 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) {
// Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading
// constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
- MVT::isInteger(N0.getOperand(0).getValueType()) &&
- !MVT::isVector(N0.getOperand(0).getValueType())) {
+ N0.getOperand(0).getValueType().isInteger() &&
+ !N0.getOperand(0).getValueType().isVector()) {
SDOperand Int = N0.getOperand(0);
- MVT::ValueType IntVT = Int.getValueType();
- if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
+ MVT IntVT = Int.getValueType();
+ if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::XOR, IntVT, Int,
- DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT));
+ DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT));
AddToWorkList(Int.Val);
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
}
@@ -3999,7 +3999,7 @@ SDOperand DAGCombiner::visitFNEG(SDNode *N) {
SDOperand DAGCombiner::visitFABS(SDNode *N) {
SDOperand N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT::ValueType VT = N->getValueType(0);
+ MVT VT = N->getValueType(0);
// fold (fabs c1) -> fabs(c1)
if (N0CFP && VT != MVT::ppcf128)
@@ -4015,13 +4015,13 @@ SDOperand DAGCombiner::visitFABS(SDNode *N) {
// Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading
// constant pool values.
if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() &&
- MVT::isInteger(N0.getOperand(0).getValueType()) &&
- !MVT::isVector(N0.getOperand(0).getValueType())) {
+ N0.getOperand(0).getValueType().isInteger() &&
+ !N0.getOperand(0).getValueType().isVector()) {
SDOperand Int = N0.getOperand(0);
- MVT::ValueType IntVT = Int.getValueType();
- if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) {
+ MVT IntVT = Int.getValueType();
+ if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::AND, IntVT, Int,
- DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT));
+ DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT));
AddToWorkList(Int.Val);
return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int);
}
@@ -4093,7 +4093,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) {
bool isLoad = true;
SDOperand Ptr;
- MVT::ValueType VT;
+ MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4214,7 +4214,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) {
bool isLoad = true;
SDOperand Ptr;
- MVT::ValueType VT;
+ MVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4513,9 +4513,9 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
ST->isUnindexed()) {
unsigned Align = ST->getAlignment();
- MVT::ValueType SVT = Value.getOperand(0).getValueType();
+ MVT SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(SVT));
+ getABITypeAlignment(SVT.getTypeForMVT());
if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(), Align);
@@ -4525,7 +4525,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) {
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDOperand Tmp;
- switch (CFP->getValueType(0)) {
+ switch (CFP->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unknown FP type");
case MVT::f80: // We don't do this for these yet.
case MVT::f128:
@@ -4610,14 +4610,14 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
// FIXME: is there such a thing as a truncating indexed store?
if (ST->isTruncatingStore() && ST->isUnindexed() &&
- MVT::isInteger(Value.getValueType())) {
+ Value.getValueType().isInteger()) {
// See if we can simplify the input to this truncstore with knowledge that
// only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
SDOperand Shorter =
GetDemandedBits(Value,
APInt::getLowBitsSet(Value.getValueSizeInBits(),
- MVT::getSizeInBits(ST->getMemoryVT())));
+ ST->getMemoryVT().getSizeInBits()));
AddToWorkList(Value.Val);
if (Shorter.Val)
return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(),
@@ -4629,7 +4629,7 @@ SDOperand DAGCombiner::visitSTORE(SDNode *N) {
if (SimplifyDemandedBits(Value,
APInt::getLowBitsSet(
Value.getValueSizeInBits(),
- MVT::getSizeInBits(ST->getMemoryVT()))))
+ ST->getMemoryVT().getSizeInBits())))
return SDOperand(N, 0);
}
@@ -4695,17 +4695,17 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue();
bool NewLoad = false;
- MVT::ValueType VT = InVec.getValueType();
- MVT::ValueType EVT = MVT::getVectorElementType(VT);
- MVT::ValueType LVT = EVT;
+ MVT VT = InVec.getValueType();
+ MVT EVT = VT.getVectorElementType();
+ MVT LVT = EVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
- MVT::ValueType BCVT = InVec.getOperand(0).getValueType();
- if (!MVT::isVector(BCVT)
- || (MVT::getSizeInBits(EVT) >
- MVT::getSizeInBits(MVT::getVectorElementType(BCVT))))
+ MVT BCVT = InVec.getOperand(0).getValueType();
+ if (!BCVT.isVector()
+ || (EVT.getSizeInBits() >
+ BCVT.getVectorElementType().getSizeInBits()))
return SDOperand();
InVec = InVec.getOperand(0);
- EVT = MVT::getVectorElementType(BCVT);
+ EVT = BCVT.getVectorElementType();
NewLoad = true;
}
@@ -4739,7 +4739,7 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// Check the resultant load doesn't need a higher alignment than the
// original load.
unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(MVT::getTypeForValueType(LVT));
+ getABITypeAlignment(LVT.getTypeForMVT());
if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align)
return SDOperand();
Align = NewAlign;
@@ -4747,10 +4747,10 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand NewPtr = LN0->getBasePtr();
if (Elt) {
- unsigned PtrOff = MVT::getSizeInBits(LVT) * Elt / 8;
- MVT::ValueType PtrType = NewPtr.getValueType();
+ unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
+ MVT PtrType = NewPtr.getValueType();
if (TLI.isBigEndian())
- PtrOff = MVT::getSizeInBits(VT) / 8 - PtrOff;
+ PtrOff = VT.getSizeInBits() / 8 - PtrOff;
NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr,
DAG.getConstant(PtrOff, PtrType));
}
@@ -4764,9 +4764,9 @@ SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
- MVT::ValueType VT = N->getValueType(0);
- unsigned NumElts = MVT::getVectorNumElements(VT);
- MVT::ValueType EltType = MVT::getVectorElementType(VT);
+ MVT VT = N->getValueType(0);
+ unsigned NumElts = VT.getVectorNumElements();
+ MVT EltType = VT.getVectorElementType();
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
@@ -4830,7 +4830,7 @@ SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
}
// Add count and size info.
- MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts);
+ MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts);
// Return the new VECTOR_SHUFFLE node.
SDOperand Ops[5];
@@ -4933,7 +4933,7 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
// look though conversions that change things like v4f32 to v2f64.
if (V->getOpcode() == ISD::BIT_CONVERT) {
SDOperand ConvInput = V->getOperand(0);
- if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts)
+ if (ConvInput.getValueType().getVectorNumElements() == NumElts)
V = ConvInput.Val;
}
@@ -5006,7 +5006,7 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
std::vector<SDOperand> IdxOps;
unsigned NumOps = RHS.getNumOperands();
unsigned NumElts = NumOps;
- MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType());
+ MVT EVT = RHS.getValueType().getVectorElementType();
for (unsigned i = 0; i != NumElts; ++i) {
SDOperand Elt = RHS.getOperand(i);
if (!isa<ConstantSDNode>(Elt))
@@ -5024,7 +5024,7 @@ SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) {
return SDOperand();
// Return the new VECTOR_SHUFFLE node.
- MVT::ValueType VT = MVT::getVectorType(EVT, NumElts);
+ MVT VT = MVT::getVectorVT(EVT, NumElts);
std::vector<SDOperand> Ops;
LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS);
Ops.push_back(LHS);
@@ -5052,10 +5052,10 @@ SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
// things. Simplifying them may result in a loss of legality.
if (AfterLegalize) return SDOperand();
- MVT::ValueType VT = N->getValueType(0);
- assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!");
+ MVT VT = N->getValueType(0);
+ assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
- MVT::ValueType EltType = MVT::getVectorElementType(VT);
+ MVT EltType = VT.getVectorElementType();
SDOperand LHS = N->getOperand(0);
SDOperand RHS = N->getOperand(1);
SDOperand Shuffle = XformToShuffleWithZero(N);
@@ -5095,7 +5095,7 @@ SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
}
if (Ops.size() == LHS.getNumOperands()) {
- MVT::ValueType VT = LHS.getValueType();
+ MVT VT = LHS.getValueType();
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
}
@@ -5217,7 +5217,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
SDOperand N2, SDOperand N3,
ISD::CondCode CC, bool NotExtCompare) {
- MVT::ValueType VT = N2.getValueType();
+ MVT VT = N2.getValueType();
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
@@ -5255,18 +5255,18 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// Check to see if we can perform the "gzip trick", transforming
// select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT &&
- MVT::isInteger(N0.getValueType()) &&
- MVT::isInteger(N2.getValueType()) &&
+ N0.getValueType().isInteger() &&
+ N2.getValueType().isInteger() &&
(N1C->isNullValue() || // (a < 0) ? b : 0
(N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
- MVT::ValueType XType = N0.getValueType();
- MVT::ValueType AType = N2.getValueType();
+ MVT XType = N0.getValueType();
+ MVT AType = N2.getValueType();
if (XType >= AType) {
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
// single-bit constant.
if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) {
unsigned ShCtV = N2C->getAPIntValue().logBase2();
- ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
+ ShCtV = XType.getSizeInBits()-ShCtV-1;
SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
AddToWorkList(Shift.Val);
@@ -5277,7 +5277,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
return DAG.getNode(ISD::AND, AType, Shift, N2);
}
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
- DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
AddToWorkList(Shift.Val);
if (XType > AType) {
@@ -5327,7 +5327,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// FIXME: Turn all of these into setcc if setcc if setcc is legal
// otherwise, go ahead with the folds.
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
- MVT::ValueType XType = N0.getValueType();
+ MVT XType = N0.getValueType();
if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) {
SDOperand Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC);
if (Res.getValueType() != VT)
@@ -5340,7 +5340,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
TLI.isOperationLegal(ISD::CTLZ, XType)) {
SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
return DAG.getNode(ISD::SRL, XType, Ctlz,
- DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
+ DAG.getConstant(Log2_32(XType.getSizeInBits()),
TLI.getShiftAmountTy()));
}
// setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
@@ -5351,13 +5351,13 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
DAG.getConstant(~0ULL, XType));
return DAG.getNode(ISD::SRL, XType,
DAG.getNode(ISD::AND, XType, NegN0, NotN0),
- DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
}
// setgt X, -1 -> xor (srl (X, size(X)-1), 1)
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
- DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
}
@@ -5367,10 +5367,10 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
- N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
- MVT::ValueType XType = N0.getValueType();
+ N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
+ MVT XType = N0.getValueType();
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
- DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
AddToWorkList(Shift.Val);
@@ -5382,10 +5382,10 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
- MVT::ValueType XType = N0.getValueType();
- if (SubC->isNullValue() && MVT::isInteger(XType)) {
+ MVT XType = N0.getValueType();
+ if (SubC->isNullValue() && XType.isInteger()) {
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
- DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ DAG.getConstant(XType.getSizeInBits()-1,
TLI.getShiftAmountTy()));
SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
AddToWorkList(Shift.Val);
@@ -5399,7 +5399,7 @@ SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
}
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
-SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
+SDOperand DAGCombiner::SimplifySetCC(MVT VT, SDOperand N0,
SDOperand N1, ISD::CondCode Cond,
bool foldBooleans) {
TargetLowering::DAGCombinerInfo
@@ -5502,13 +5502,13 @@ bool DAGCombiner::FindAliasInfo(SDNode *N,
const Value *&SrcValue, int &SrcValueOffset) {
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
Ptr = LD->getBasePtr();
- Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3;
+ Size = LD->getMemoryVT().getSizeInBits() >> 3;
SrcValue = LD->getSrcValue();
SrcValueOffset = LD->getSrcValueOffset();
return true;
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
Ptr = ST->getBasePtr();
- Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3;
+ Size = ST->getMemoryVT().getSizeInBits() >> 3;
SrcValue = ST->getSrcValue();
SrcValueOffset = ST->getSrcValueOffset();
} else {
generated by cgit v1.1 at 2025-06-12 22:53:57 +0000