diff options
Diffstat (limited to 'lib/Target/AArch64/AArch64TargetMachine.h')
-rw-r--r-- | lib/Target/AArch64/AArch64TargetMachine.h | 74 |
1 files changed, 37 insertions, 37 deletions
diff --git a/lib/Target/AArch64/AArch64TargetMachine.h b/lib/Target/AArch64/AArch64TargetMachine.h index 4297c92..079b19b 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.h +++ b/lib/Target/AArch64/AArch64TargetMachine.h @@ -1,4 +1,4 @@ -//=== AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-===// +//==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -11,60 +11,60 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_AARCH64TARGETMACHINE_H -#define LLVM_AARCH64TARGETMACHINE_H +#ifndef AArch64TARGETMACHINE_H +#define AArch64TARGETMACHINE_H -#include "AArch64FrameLowering.h" -#include "AArch64ISelLowering.h" #include "AArch64InstrInfo.h" -#include "AArch64SelectionDAGInfo.h" +#include "AArch64ISelLowering.h" #include "AArch64Subtarget.h" +#include "AArch64FrameLowering.h" +#include "AArch64SelectionDAGInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/MC/MCStreamer.h" namespace llvm { class AArch64TargetMachine : public LLVMTargetMachine { - AArch64Subtarget Subtarget; - AArch64InstrInfo InstrInfo; - const DataLayout DL; - AArch64TargetLowering TLInfo; - AArch64SelectionDAGInfo TSInfo; - AArch64FrameLowering FrameLowering; +protected: + AArch64Subtarget Subtarget; + +private: + const DataLayout DL; + AArch64InstrInfo InstrInfo; + AArch64TargetLowering TLInfo; + AArch64FrameLowering FrameLowering; + AArch64SelectionDAGInfo TSInfo; public: AArch64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL, - bool LittleEndian); + CodeGenOpt::Level OL, bool IsLittleEndian); - const AArch64InstrInfo *getInstrInfo() const { - return &InstrInfo; + const AArch64Subtarget *getSubtargetImpl() const override { + return &Subtarget; } - - const AArch64FrameLowering *getFrameLowering() const { + const AArch64TargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const DataLayout *getDataLayout() const override { return &DL; } + const AArch64FrameLowering *getFrameLowering() const override { return &FrameLowering; } - - const AArch64TargetLowering *getTargetLowering() const { - return &TLInfo; + const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } + const AArch64RegisterInfo *getRegisterInfo() const override { + return &InstrInfo.getRegisterInfo(); } - - const AArch64SelectionDAGInfo *getSelectionDAGInfo() const { + const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } - const AArch64Subtarget *getSubtargetImpl() const { return &Subtarget; } - - const DataLayout *getDataLayout() const { return &DL; } - - const TargetRegisterInfo *getRegisterInfo() const { - return &InstrInfo.getRegisterInfo(); - } - TargetPassConfig *createPassConfig(PassManagerBase &PM); + // Pass Pipeline Configuration + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - virtual void addAnalysisPasses(PassManagerBase &PM); + /// \brief Register AArch64 analysis passes with a pass manager. + void addAnalysisPasses(PassManagerBase &PM) override; }; // AArch64leTargetMachine - AArch64 little endian target machine. @@ -72,8 +72,8 @@ public: class AArch64leTargetMachine : public AArch64TargetMachine { virtual void anchor(); public: - AArch64leTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, const TargetOptions &Options, + AArch64leTargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); }; @@ -83,12 +83,12 @@ public: class AArch64beTargetMachine : public AArch64TargetMachine { virtual void anchor(); public: - AArch64beTargetMachine(const Target &T, StringRef TT, - StringRef CPU, StringRef FS, const TargetOptions &Options, + AArch64beTargetMachine(const Target &T, StringRef TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); }; -} // End llvm namespace +} // end namespace llvm #endif |