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-rw-r--r--lib/Target/ARM/ARMSchedule.td11
1 files changed, 9 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMSchedule.td b/lib/Target/ARM/ARMSchedule.td
index ff1ff2f..7eb5ff6 100644
--- a/lib/Target/ARM/ARMSchedule.td
+++ b/lib/Target/ARM/ARMSchedule.td
@@ -56,13 +56,20 @@
// Basic ALU operation.
def WriteALU : SchedWrite;
-def ReadAdvanceALU : SchedRead;
+def ReadALU : SchedRead;
// Basic ALU with shifts.
def WriteALUsi : SchedWrite; // Shift by immediate.
def WriteALUsr : SchedWrite; // Shift by register.
def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
-def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
+def ReadALUsr : SchedRead; // Some operands are read later.
+
+// Define TII for use in SchedVariant Predicates.
+def : PredicateProlog<[{
+ const ARMBaseInstrInfo *TII =
+ static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
+ (void)TII;
+}]>;
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM