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-rw-r--r--lib/Target/ARM/ARMInstrNEON.td14
-rw-r--r--lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp5
2 files changed, 19 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index 7cceea2..2c18470 100644
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -1769,6 +1769,20 @@ def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>;
def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>;
def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>;
+def VDUPfdf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 0, 0,
+ (outs DPR:$dst), (ins SPR:$src),
+ "vdup.32\t$dst, ${src:lane}", "",
+ [(set DPR:$dst, (v2f32 (splat_lo
+ (scalar_to_vector SPR:$src),
+ undef)))]>;
+
+def VDUPfqf : N2V<0b11, 0b11, 0b01, 0b00, 0b11000, 1, 0,
+ (outs QPR:$dst), (ins SPR:$src),
+ "vdup.32\t$dst, ${src:lane}", "",
+ [(set QPR:$dst, (v4f32 (splat_lo
+ (scalar_to_vector SPR:$src),
+ undef)))]>;
+
// VMOVN : Vector Narrowing Move
defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i",
int_arm_neon_vmovn>;
diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 3bbb3b9..c817ee9 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -345,6 +345,11 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
O << '{'
<< TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
<< '}';
+ } else if (Modifier && strcmp(Modifier, "lane") == 0) {
+ unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
+ unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
+ &ARM::DPRRegClass);
+ O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
} else {
O << TRI->getAsmName(Reg);
}