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-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.cpp2
-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.h2
2 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp
index fe06d57..8b83791 100644
--- a/lib/Target/Blackfin/BlackfinISelLowering.cpp
+++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp
@@ -137,7 +137,7 @@ const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const {
}
}
-MVT BlackfinTargetLowering::getSetCCResultType(MVT VT) const {
+MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(MVT VT) const {
// SETCC always sets the CC register. Technically that is an i1 register, but
// that type is not legal, so we treat it as an i32 register.
return MVT::i32;
diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h
index fd0d30c..a0e88a9 100644
--- a/lib/Target/Blackfin/BlackfinISelLowering.h
+++ b/lib/Target/Blackfin/BlackfinISelLowering.h
@@ -33,7 +33,7 @@ namespace llvm {
int VarArgsFrameOffset; // Frame offset to start of varargs area.
public:
BlackfinTargetLowering(TargetMachine &TM);
- virtual MVT getSetCCResultType(MVT VT) const;
+ virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
virtual void ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue> &Results,