diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonInstrFormats.td')
| -rw-r--r-- | lib/Target/Hexagon/HexagonInstrFormats.td | 35 |
1 files changed, 13 insertions, 22 deletions
diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index cc27c4c..3d04678 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -28,20 +28,12 @@ def TypeXTYPE : IType<8>; def TypeENDLOOP: IType<31>; // Maintain list of valid subtargets for each instruction. -class SubTarget<bits<4> value> { - bits<4> Value = value; +class SubTarget<bits<6> value> { + bits<6> Value = value; } -def HasV2SubT : SubTarget<0xf>; -def HasV2SubTOnly : SubTarget<0x1>; -def NoV2SubT : SubTarget<0x0>; -def HasV3SubT : SubTarget<0xe>; -def HasV3SubTOnly : SubTarget<0x2>; -def NoV3SubT : SubTarget<0x1>; -def HasV4SubT : SubTarget<0xc>; -def NoV4SubT : SubTarget<0x3>; -def HasV5SubT : SubTarget<0x8>; -def NoV5SubT : SubTarget<0x7>; +def HasAnySubT : SubTarget<0x3f>; // 111111 +def HasV5SubT : SubTarget<0x3e>; // 111110 // Addressing modes for load/store instructions class AddrModeType<bits<3> value> { @@ -56,8 +48,8 @@ def BaseLongOffset : AddrModeType<4>; // Indirect with long offset def BaseRegOffset : AddrModeType<5>; // Indirect with register offset def PostInc : AddrModeType<6>; // Post increment addressing mode -class MemAccessSize<bits<3> value> { - bits<3> Value = value; +class MemAccessSize<bits<4> value> { + bits<4> Value = value; } def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction. @@ -157,11 +149,11 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, bits<2> opExtentAlign = 0; let TSFlags{33-32} = opExtentAlign; // Alignment exponent before extending. - // If an instruction is valid on a subtarget (v2-v5), set the corresponding - // bit from validSubTargets. v2 is the least significant bit. + // If an instruction is valid on a subtarget, set the corresponding + // bit from validSubTargets. // By default, instruction is valid on all subtargets. - SubTarget validSubTargets = HasV2SubT; - let TSFlags{37-34} = validSubTargets.Value; + SubTarget validSubTargets = HasAnySubT; + let TSFlags{39-34} = validSubTargets.Value; // Addressing mode for load/store instructions. AddrModeType addrMode = NoAddrMode; @@ -169,7 +161,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // Memory access size for mem access instructions (load/store) MemAccessSize accessSize = NoMemAccess; - let TSFlags{45-43} = accessSize.Value; + let TSFlags{46-43} = accessSize.Value; bits<1> isTaken = 0; let TSFlags {47} = isTaken; // Branch prediction. @@ -186,13 +178,12 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, string InputType = ""; // Input is "imm" or "reg" type. string isMEMri = "false"; // Set to "true" for load/store with MEMri operand. string isFloat = "false"; // Set to "true" for the floating-point load/store. - string isBrTaken = ""; // Set to "true"/"false" for jump instructions + string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"), ""); let PNewValue = !if(isPredicatedNew, "new", ""); let NValueST = !if(isNVStore, "true", "false"); - let isCodeGenOnly = 1; // *** Must match MCTargetDesc/HexagonBaseInfo.h *** } @@ -203,6 +194,7 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. +let mayLoad = 1 in class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01> : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>; @@ -365,7 +357,6 @@ class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [], string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123> : ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>; - // // ALU64 patterns. // |