diff options
Diffstat (limited to 'lib/Target/Hexagon/HexagonTargetMachine.cpp')
-rw-r--r-- | lib/Target/Hexagon/HexagonTargetMachine.cpp | 16 |
1 files changed, 12 insertions, 4 deletions
diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index cd96b58..bb950a0 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -102,17 +102,25 @@ class HexagonPassConfig : public TargetPassConfig { public: HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) : TargetPassConfig(TM, PM) { - // Enable MI scheduler. - if (!DisableHexagonMISched) { + // FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define + // HexagonSubtarget::enableMachineScheduler() { return true; }. + // That will bypass the SelectionDAG VLIW scheduler, which is probably just + // hurting compile time and will be removed eventually anyway. + if (DisableHexagonMISched) + disablePass(&MachineSchedulerID); + else enablePass(&MachineSchedulerID); - MachineSchedRegistry::setDefault(createVLIWMachineSched); - } } HexagonTargetMachine &getHexagonTargetMachine() const { return getTM<HexagonTargetMachine>(); } + virtual ScheduleDAGInstrs * + createMachineScheduler(MachineSchedContext *C) const { + return createVLIWMachineSched(C); + } + virtual bool addInstSelector(); virtual bool addPreRegAlloc(); virtual bool addPostRegAlloc(); |