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-rw-r--r--lib/Target/Hexagon/HexagonVLIWPacketizer.cpp114
1 files changed, 55 insertions, 59 deletions
diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
index 87ce960..e7296d6 100644
--- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -118,7 +118,6 @@ namespace {
public:
// Ctor.
HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
- MachineDominatorTree &MDT,
const MachineBranchProbabilityInfo *MBPI);
// initPacketizerState - initialize some internal flags.
@@ -146,23 +145,23 @@ namespace {
bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,
MachineBasicBlock::iterator &MII,
const TargetRegisterClass* RC);
- bool CanPromoteToDotNew(MachineInstr* MI, SUnit* PacketSU,
- unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit,
+ bool CanPromoteToDotNew(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit,
MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC);
- bool CanPromoteToNewValue(MachineInstr* MI, SUnit* PacketSU,
- unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit,
- MachineBasicBlock::iterator &MII);
- bool CanPromoteToNewValueStore(MachineInstr* MI, MachineInstr* PacketMI,
- unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit);
- bool DemoteToDotOld(MachineInstr* MI);
- bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
- std::map <MachineInstr*, SUnit*> MIToSUnit);
- bool RestrictingDepExistInPacket(MachineInstr*,
- unsigned, std::map <MachineInstr*, SUnit*>);
+ const TargetRegisterClass *RC);
+ bool
+ CanPromoteToNewValue(MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit,
+ MachineBasicBlock::iterator &MII);
+ bool CanPromoteToNewValueStore(
+ MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit);
+ bool DemoteToDotOld(MachineInstr *MI);
+ bool ArePredicatesComplements(
+ MachineInstr *MI1, MachineInstr *MI2,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit);
+ bool RestrictingDepExistInPacket(MachineInstr *, unsigned,
+ const std::map<MachineInstr *, SUnit *> &);
bool isNewifiable(MachineInstr* MI);
bool isCondInst(MachineInstr* MI);
bool tryAllocateResourcesForConstExt(MachineInstr* MI);
@@ -184,20 +183,19 @@ INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer",
// HexagonPacketizerList Ctor.
HexagonPacketizerList::HexagonPacketizerList(
- MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT,
- const MachineBranchProbabilityInfo *MBPI)
- : VLIWPacketizerList(MF, MLI, MDT, true){
+ MachineFunction &MF, MachineLoopInfo &MLI,
+ const MachineBranchProbabilityInfo *MBPI)
+ : VLIWPacketizerList(MF, MLI, true) {
this->MBPI = MBPI;
}
bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) {
- const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo();
MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
- MachineDominatorTree &MDT = getAnalysis<MachineDominatorTree>();
const MachineBranchProbabilityInfo *MBPI =
&getAnalysis<MachineBranchProbabilityInfo>();
// Instantiate the packetizer.
- HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI);
+ HexagonPacketizerList Packetizer(Fn, MLI, MBPI);
// DFA state table should not be empty.
assert(Packetizer.getResourceTracker() && "Empty DFA table!");
@@ -324,8 +322,8 @@ bool HexagonPacketizerList::IsCallDependent(MachineInstr* MI,
unsigned DepReg) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
- const HexagonRegisterInfo* QRI =
- (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo *QRI =
+ (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
// Check for lr dependence
if (DepReg == QRI->getRARegister()) {
@@ -536,9 +534,9 @@ static MachineOperand& GetStoreValueOperand(MachineInstr *MI) {
// if there is a new value store in the packet. Corollary, if there is
// already a store in a packet, there can not be a new value store.
// Arch Spec: 3.4.4.2
-bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
- MachineInstr *PacketMI, unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit) {
+bool HexagonPacketizerList::CanPromoteToNewValueStore(
+ MachineInstr *MI, MachineInstr *PacketMI, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
// Make sure we are looking at the store, that can be promoted.
if (!QII->mayBeNewStore(MI))
@@ -549,8 +547,8 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
GetStoreValueOperand(MI).getReg() != DepReg)
return false;
- const HexagonRegisterInfo* QRI =
- (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo *QRI =
+ (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
const MCInstrDesc& MCID = PacketMI->getDesc();
// first operand is always the result
@@ -561,7 +559,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(),
VE = CurrentPacketMIs.end();
(VI != VE); ++VI) {
- SUnit* PacketSU = MIToSUnit[*VI];
+ SUnit *PacketSU = MIToSUnit.find(*VI)->second;
if (PacketSU->getInstr()->getDesc().mayStore() ||
// if we have mayStore = 1 set on ALLOCFRAME and DEALLOCFRAME,
// then we don't need this
@@ -661,7 +659,7 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
for (VI=CurrentPacketMIs.begin(), VE = CurrentPacketMIs.end();
(VI != VE); ++VI) {
- SUnit* TempSU = MIToSUnit[*VI];
+ SUnit *TempSU = MIToSUnit.find(*VI)->second;
MachineInstr* TempMI = TempSU->getInstr();
// Following condition is true for all the instructions until PacketMI is
@@ -717,15 +715,14 @@ bool HexagonPacketizerList::CanPromoteToNewValueStore( MachineInstr *MI,
// can this MI to promoted to either
// new value store or new value jump
-bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
- SUnit *PacketSU, unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit,
- MachineBasicBlock::iterator &MII)
-{
+bool HexagonPacketizerList::CanPromoteToNewValue(
+ MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit,
+ MachineBasicBlock::iterator &MII) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
- const HexagonRegisterInfo* QRI =
- (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo *QRI =
+ (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
if (!QRI->Subtarget.hasV4TOps() ||
!QII->mayBeNewStore(MI))
return false;
@@ -746,12 +743,10 @@ bool HexagonPacketizerList::CanPromoteToNewValue( MachineInstr *MI,
// 1. dot new on predicate - V2/V3/V4
// 2. dot new on stores NV/ST - V4
// 3. dot new on jump NV/J - V4 -- This is generated in a pass.
-bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
- SUnit *PacketSU, unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit,
- MachineBasicBlock::iterator &MII,
- const TargetRegisterClass* RC )
-{
+bool HexagonPacketizerList::CanPromoteToDotNew(
+ MachineInstr *MI, SUnit *PacketSU, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit,
+ MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
// Already a dot new instruction.
if (QII->isDotNewInst(MI) && !QII->mayBeNewStore(MI))
@@ -803,12 +798,12 @@ bool HexagonPacketizerList::CanPromoteToDotNew( MachineInstr *MI,
// The P3 from a) and d) will be complements after
// a)'s P3 is converted to .new form
// Anti Dep between c) and b) is irrelevant for this case
-bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
- unsigned DepReg,
- std::map <MachineInstr*, SUnit*> MIToSUnit) {
+bool HexagonPacketizerList::RestrictingDepExistInPacket(
+ MachineInstr *MI, unsigned DepReg,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
- SUnit* PacketSUDep = MIToSUnit[MI];
+ SUnit *PacketSUDep = MIToSUnit.find(MI)->second;
for (std::vector<MachineInstr*>::iterator VIN = CurrentPacketMIs.begin(),
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
@@ -817,7 +812,7 @@ bool HexagonPacketizerList::RestrictingDepExistInPacket (MachineInstr* MI,
if(!QII->isPredicated(*VIN)) continue;
// Scheduling Unit for current insn in the packet
- SUnit* PacketSU = MIToSUnit[*VIN];
+ SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
// Look at dependencies between current members of the packet
// and predicate defining instruction MI.
@@ -861,8 +856,9 @@ static unsigned getPredicatedRegister(MachineInstr *MI,
// Given two predicated instructions, this function detects whether
// the predicates are complements
-bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
- MachineInstr* MI2, std::map <MachineInstr*, SUnit*> MIToSUnit) {
+bool HexagonPacketizerList::ArePredicatesComplements(
+ MachineInstr *MI1, MachineInstr *MI2,
+ const std::map<MachineInstr *, SUnit *> &MIToSUnit) {
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
@@ -873,7 +869,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
return false;
// Scheduling unit for candidate
- SUnit* SU = MIToSUnit[MI1];
+ SUnit *SU = MIToSUnit.find(MI1)->second;
// One corner case deals with the following scenario:
// Trying to add
@@ -898,7 +894,7 @@ bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1,
VEN = CurrentPacketMIs.end(); (VIN != VEN); ++VIN) {
// Scheduling Unit for current insn in the packet
- SUnit* PacketSU = MIToSUnit[*VIN];
+ SUnit *PacketSU = MIToSUnit.find(*VIN)->second;
// If this instruction in the packet is succeeded by the candidate...
if (PacketSU->isSucc(SU)) {
@@ -1007,8 +1003,8 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
MachineBasicBlock::iterator II = I;
const unsigned FrameSize = MF.getFrameInfo()->getStackSize();
- const HexagonRegisterInfo* QRI =
- (const HexagonRegisterInfo *) TM.getRegisterInfo();
+ const HexagonRegisterInfo *QRI =
+ (const HexagonRegisterInfo *)MF.getSubtarget().getRegisterInfo();
const HexagonInstrInfo *QII = (const HexagonInstrInfo *) TII;
// Inline asm cannot go in the packet.
@@ -1103,7 +1099,7 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
VI = CurrentPacketMIs.begin(),
VE = CurrentPacketMIs.end();
(VI != VE && maintainNewValueJump); ++VI) {
- SUnit* PacketSU = MIToSUnit[*VI];
+ SUnit *PacketSU = MIToSUnit.find(*VI)->second;
// NVJ can not be part of the dual jump - Arch Spec: section 7.8
if (PacketSU->getInstr()->getDesc().isCall()) {
@@ -1278,9 +1274,9 @@ bool HexagonPacketizerList::isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
}
// For V4, special case ALLOCFRAME. Even though there is dependency
- // between ALLOCAFRAME and subsequent store, allow it to be
+ // between ALLOCFRAME and subsequent store, allow it to be
// packetized in a same packet. This implies that the store is using
- // caller's SP. Hense, offset needs to be updated accordingly.
+ // caller's SP. Hence, offset needs to be updated accordingly.
else if (DepType == SDep::Data
&& QRI->Subtarget.hasV4TOps()
&& J->getOpcode() == Hexagon::ALLOCFRAME
generated by cgit v1.1 at 2024-12-22 18:38:43 +0000