diff options
Diffstat (limited to 'lib/Target/Hexagon')
41 files changed, 1516 insertions, 819 deletions
diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index f8705ee..6c5da72 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -6,7 +6,7 @@ tablegen(LLVM HexagonGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM HexagonGenDAGISel.inc -gen-dag-isel) tablegen(LLVM HexagonGenCallingConv.inc -gen-callingconv) tablegen(LLVM HexagonGenSubtargetInfo.inc -gen-subtarget) -tablegen(LLVM HexagonGenIntrinsics.inc -gen-tgt-intrinsic) +tablegen(LLVM HexagonGenDFAPacketizer.inc -gen-dfa-packetizer) add_public_tablegen_target(HexagonCommonTableGen) add_llvm_target(HexagonCodeGen @@ -19,8 +19,7 @@ add_llvm_target(HexagonCodeGen HexagonInstrInfo.cpp HexagonISelDAGToDAG.cpp HexagonISelLowering.cpp - HexagonMCAsmInfo.cpp - HexagonOptimizeSZExtends.cpp + HexagonPeephole.cpp HexagonRegisterInfo.cpp HexagonRemoveSZExtArgs.cpp HexagonSelectionDAGInfo.cpp diff --git a/lib/Target/Hexagon/Hexagon.h b/lib/Target/Hexagon/Hexagon.h index a5f2279..bbefcaf 100644 --- a/lib/Target/Hexagon/Hexagon.h +++ b/lib/Target/Hexagon/Hexagon.h @@ -35,7 +35,7 @@ namespace llvm { FunctionPass* createHexagonExpandPredSpillCode(HexagonTargetMachine &TM); FunctionPass *createHexagonHardwareLoops(); - FunctionPass *createHexagonOptimizeSZExtends(); + FunctionPass *createHexagonPeephole(); FunctionPass *createHexagonFixupHwLoops(); } // end namespace llvm; diff --git a/lib/Target/Hexagon/Hexagon.td b/lib/Target/Hexagon/Hexagon.td index 72939e6..ab5093d 100644 --- a/lib/Target/Hexagon/Hexagon.td +++ b/lib/Target/Hexagon/Hexagon.td @@ -1,4 +1,4 @@ -//===- Hexagon.td - Describe the Hexagon Target Machine ---------*- C++ -*-===// +//===-- Hexagon.td - Describe the Hexagon Target Machine --*- tablegen -*--===// // // The LLVM Compiler Infrastructure // @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// // +// This is the top level entry point for the Hexagon target. // //===----------------------------------------------------------------------===// @@ -18,8 +19,7 @@ include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // Hexagon Subtarget features. -// - +//===----------------------------------------------------------------------===// // Hexagon Archtectures def ArchV2 : SubtargetFeature<"v2", "HexagonArchVersion", "V2", diff --git a/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/lib/Target/Hexagon/HexagonAsmPrinter.cpp index 8f8e804..688b8e3 100644 --- a/lib/Target/Hexagon/HexagonAsmPrinter.cpp +++ b/lib/Target/Hexagon/HexagonAsmPrinter.cpp @@ -1,4 +1,4 @@ -//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly ----=// +//===-- HexagonAsmPrinter.cpp - Print machine instrs to Hexagon assembly --===// // // The LLVM Compiler Infrastructure // @@ -11,9 +11,6 @@ // of machine-dependent LLVM code to Hexagon assembly language. This printer is // the output mechanism used by `llc'. // -// Documentation at http://developer.apple.com/documentation/DeveloperTools/ -// Reference/Assembler/ASMIntroduction/chapter_1_section_1.html -// //===----------------------------------------------------------------------===// @@ -125,6 +122,11 @@ namespace { O << -value; } + void printHexagonNOneImmOperand(const MachineInstr *MI, unsigned OpNo, + raw_ostream &O) const { + O << -1; + } + void printHexagonMEMriOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { const MachineOperand &MO1 = MI->getOperand(OpNo); @@ -223,7 +225,6 @@ void HexagonAsmPrinter::printOp(const MachineOperand &MO, raw_ostream &O) { case MachineOperand::MO_Immediate: dbgs() << "printOp() does not handle immediate values\n"; abort(); - return; case MachineOperand::MO_MachineBasicBlock: O << *MO.getMBB()->getSymbol(); @@ -319,14 +320,14 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, if (Base.isReg()) printOperand(MI, OpNo, O); else - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); if (Offset.isImm()) { if (Offset.getImm()) O << " + #" << Offset.getImm(); } else - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); return false; } @@ -334,7 +335,7 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, void HexagonAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); } @@ -370,19 +371,6 @@ void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) { O << "}"; } printInstruction(MI, O); - } else if (MI->getOpcode() == Hexagon::STriwt) { - // - // Handle truncated store on Hexagon. - // - O << "\tmemw("; - printHexagonMEMriOperand(MI, 0, O); - - O << ") = "; - unsigned SubRegNum = - TM.getRegisterInfo()->getSubReg(MI->getOperand(2) - .getReg(), Hexagon::subreg_loreg); - const char *SubRegName = getRegisterName(SubRegNum); - O << SubRegName << '\n'; } else if (MI->getOpcode() == Hexagon::MPYI_rin) { // Handle multipy with -ve constant on Hexagon: // "$dst =- mpyi($src1, #$src2)" diff --git a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp index 38000e7..9bca9e0 100644 --- a/lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ b/lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -1,4 +1,4 @@ -//===---- HexagonCFGOptimizer.cpp - CFG optimizations ---------------------===// +//===-- HexagonCFGOptimizer.cpp - CFG optimizations -----------------------===// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source @@ -6,27 +6,22 @@ // //===----------------------------------------------------------------------===// - #define DEBUG_TYPE "hexagon_cfg" -#include "llvm/CodeGen/Passes.h" +#include "HexagonTargetMachine.h" +#include "HexagonSubtarget.h" +#include "HexagonMachineFunctionInfo.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" -#include "llvm/ADT/Statistic.h" #include "llvm/Support/MathExtras.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "HexagonTargetMachine.h" -#include "HexagonSubtarget.h" -#include "HexagonMachineFunctionInfo.h" -#include <iostream> - -#include "llvm/Support/CommandLine.h" using namespace llvm; @@ -56,8 +51,8 @@ private: char HexagonCFGOptimizer::ID = 0; static bool IsConditionalBranch(int Opc) { - return (Opc == Hexagon::JMP_Pred) || (Opc == Hexagon::JMP_PredNot) - || (Opc == Hexagon::JMP_PredPt) || (Opc == Hexagon::JMP_PredNotPt); + return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot) + || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt); } @@ -72,24 +67,24 @@ HexagonCFGOptimizer::InvertAndChangeJumpTarget(MachineInstr* MI, const HexagonInstrInfo *QII = QTM.getInstrInfo(); int NewOpcode = 0; switch(MI->getOpcode()) { - case Hexagon::JMP_Pred: - NewOpcode = Hexagon::JMP_PredNot; + case Hexagon::JMP_c: + NewOpcode = Hexagon::JMP_cNot; break; - case Hexagon::JMP_PredNot: - NewOpcode = Hexagon::JMP_Pred; + case Hexagon::JMP_cNot: + NewOpcode = Hexagon::JMP_c; break; - case Hexagon::JMP_PredPt: - NewOpcode = Hexagon::JMP_PredNotPt; + case Hexagon::JMP_cdnPt: + NewOpcode = Hexagon::JMP_cdnNotPt; break; - case Hexagon::JMP_PredNotPt: - NewOpcode = Hexagon::JMP_PredPt; + case Hexagon::JMP_cdnNotPt: + NewOpcode = Hexagon::JMP_cdnPt; break; default: - assert(0 && "Cannot handle this case"); + llvm_unreachable("Cannot handle this case"); } MI->setDesc(QII->get(NewOpcode)); @@ -160,8 +155,8 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) { // The target of the unconditional branch must be JumpAroundTarget. // TODO: If not, we should not invert the unconditional branch. MachineBasicBlock* CondBranchTarget = NULL; - if ((MI->getOpcode() == Hexagon::JMP_Pred) || - (MI->getOpcode() == Hexagon::JMP_PredNot)) { + if ((MI->getOpcode() == Hexagon::JMP_c) || + (MI->getOpcode() == Hexagon::JMP_cNot)) { CondBranchTarget = MI->getOperand(1).getMBB(); } diff --git a/lib/Target/Hexagon/HexagonCallingConvLower.cpp b/lib/Target/Hexagon/HexagonCallingConvLower.cpp index 2e51dbf..71787de 100644 --- a/lib/Target/Hexagon/HexagonCallingConvLower.cpp +++ b/lib/Target/Hexagon/HexagonCallingConvLower.cpp @@ -58,7 +58,7 @@ void Hexagon_CCState::HandleByVal(unsigned ValNo, EVT ValVT, void Hexagon_CCState::MarkAllocated(unsigned Reg) { UsedRegs[Reg/32] |= 1 << (Reg&31); - if (const unsigned *RegAliases = TRI.getAliasSet(Reg)) + if (const uint16_t *RegAliases = TRI.getAliasSet(Reg)) for (; (Reg = *RegAliases); ++RegAliases) UsedRegs[Reg/32] |= 1 << (Reg&31); } diff --git a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp index cb73ae0..2100474 100644 --- a/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp +++ b/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp @@ -1,11 +1,11 @@ -//===--- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ----===// +//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===//// +//===----------------------------------------------------------------------===// // The Hexagon processor has no instructions that load or store predicate // registers directly. So, when these registers must be spilled a general // purpose register must be found and the value copied to/from it from/to @@ -17,31 +17,25 @@ // //===----------------------------------------------------------------------===// - -#include "llvm/CodeGen/Passes.h" +#include "HexagonTargetMachine.h" +#include "HexagonSubtarget.h" +#include "HexagonMachineFunctionInfo.h" +#include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/LatencyPriorityQueue.h" -#include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" +#include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" -#include "llvm/ADT/Statistic.h" #include "llvm/Support/MathExtras.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "HexagonTargetMachine.h" -#include "HexagonSubtarget.h" -#include "HexagonMachineFunctionInfo.h" -#include <map> -#include <iostream> - -#include "llvm/Support/CommandLine.h" - using namespace llvm; @@ -70,7 +64,6 @@ char HexagonExpandPredSpillCode::ID = 0; bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { const HexagonInstrInfo *TII = QTM.getInstrInfo(); - const HexagonRegisterInfo *RegInfo = QTM.getRegisterInfo(); // Loop over all of the basic blocks. for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); @@ -84,7 +77,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { if (Opc == Hexagon::STriw_pred) { // STriw_pred [R30], ofst, SrcReg; unsigned FP = MI->getOperand(0).getReg(); - assert(FP == RegInfo->getFrameRegister() && + assert(FP == QTM.getRegisterInfo()->getFrameRegister() && "Not a Frame Pointer, Nor a Spill Slot"); assert(MI->getOperand(1).isImm() && "Not an offset"); int Offset = MI->getOperand(1).getImm(); @@ -129,7 +122,7 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { assert(Hexagon::PredRegsRegClass.contains(DstReg) && "Not a predicate register"); unsigned FP = MI->getOperand(1).getReg(); - assert(FP == RegInfo->getFrameRegister() && + assert(FP == QTM.getRegisterInfo()->getFrameRegister() && "Not a Frame Pointer, Nor a Spill Slot"); assert(MI->getOperand(2).isImm() && "Not an offset"); int Offset = MI->getOperand(2).getImm(); diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index 78e0b1c..49c6cdf 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1,4 +1,4 @@ -//==-- HexagonFrameLowering.cpp - Define frame lowering --*- C++ -*-==// +//===-- HexagonFrameLowering.cpp - Define frame lowering ------------------===// // // The LLVM Compiler Infrastructure // @@ -7,6 +7,7 @@ // // //===----------------------------------------------------------------------===// + #include "Hexagon.h" #include "HexagonInstrInfo.h" #include "HexagonRegisterInfo.h" @@ -14,27 +15,25 @@ #include "HexagonTargetMachine.h" #include "HexagonMachineFunctionInfo.h" #include "HexagonFrameLowering.h" - +#include "llvm/Function.h" +#include "llvm/Type.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/AsmPrinter.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/MC/MachineLocation.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Type.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include <iostream> +#include "llvm/Support/CommandLine.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/Function.h" using namespace llvm; static cl::opt<bool> DisableDeallocRet( @@ -236,7 +235,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( // // Check if we can use a double-word store. // - const unsigned* SuperReg = TRI->getSuperRegisters(Reg); + const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); // Assume that there is exactly one superreg. assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); @@ -244,7 +243,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( const TargetRegisterClass* SuperRegClass = 0; if (ContiguousRegs && (i < CSI.size()-1)) { - const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); + const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); assert(SuperRegNext[0] && !SuperRegNext[1] && "Expected exactly one superreg"); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); @@ -296,14 +295,14 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters( // // Check if we can use a double-word load. // - const unsigned* SuperReg = TRI->getSuperRegisters(Reg); + const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); const TargetRegisterClass* SuperRegClass = 0; // Assume that there is exactly one superreg. assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); bool CanUseDblLoad = false; if (ContiguousRegs && (i < CSI.size()-1)) { - const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); + const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); assert(SuperRegNext[0] && !SuperRegNext[1] && "Expected exactly one superreg"); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); diff --git a/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/lib/Target/Hexagon/HexagonHardwareLoops.cpp index c1abc4a..04ea4ed 100644 --- a/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -517,8 +517,8 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) { // The loop ends with either: // - a conditional branch followed by an unconditional branch, or // - a conditional branch to the loop start. - if (LastI->getOpcode() == Hexagon::JMP_Pred || - LastI->getOpcode() == Hexagon::JMP_PredNot) { + if (LastI->getOpcode() == Hexagon::JMP_c || + LastI->getOpcode() == Hexagon::JMP_cNot) { // delete one and change/add an uncond. branch to out of the loop MachineBasicBlock *BranchTarget = LastI->getOperand(1).getMBB(); LastI = LastMBB->erase(LastI); diff --git a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp index 4deab9f..9df965e 100644 --- a/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp +++ b/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp @@ -1,4 +1,4 @@ -//==-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon ----==// +//===-- HexagonISelDAGToDAG.cpp - A dag to dag inst selector for Hexagon --===// // // The LLVM Compiler Infrastructure // @@ -238,7 +238,7 @@ static unsigned doesIntrinsicContainPredicate(unsigned ID) case Intrinsic::hexagon_C2_or: return Hexagon::OR_pp; case Intrinsic::hexagon_C2_not: - return Hexagon::NOT_pp; + return Hexagon::NOT_p; case Intrinsic::hexagon_C2_any8: return Hexagon::ANY_pp; case Intrinsic::hexagon_C2_all8: @@ -295,7 +295,6 @@ static bool OffsetFitsS11(EVT MemType, int64_t Offset) { // CONST32. // SDNode *HexagonDAGToDAGISel::SelectBaseOffsetLoad(LoadSDNode *LD, DebugLoc dl) { - EVT LoadedVT = LD->getMemoryVT(); SDValue Chain = LD->getChain(); SDNode* Const32 = LD->getBasePtr().getNode(); unsigned Opcode = 0; @@ -572,8 +571,6 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, DebugLoc dl) { ReplaceUses(Froms, Tos, 3); return Result_1; } - - return SelectCode(LD); } @@ -767,7 +764,6 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) { SelectCode(N); } - SDValue Base = LD->getBasePtr(); SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, @@ -794,7 +790,6 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) { return SelectCode(N); } - SDValue Base = LD->getBasePtr(); SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, @@ -949,7 +944,6 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) { return SelectCode(N); } - SDValue Base = LD->getBasePtr(); SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, @@ -975,7 +969,6 @@ SDNode *HexagonDAGToDAGISel::SelectTruncate(SDNode *N) { return SelectCode(N); } - SDValue Base = LD->getBasePtr(); SDValue Chain = LD->getChain(); SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32); OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32, @@ -1106,7 +1099,7 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) { ReplaceUses(N, RsPd); return RsPd; } - assert(0 && "Unexpected value type"); + llvm_unreachable("Unexpected value type"); } } return SelectCode(N); @@ -1152,7 +1145,7 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) { SDValue SDVal = CurDAG->getTargetConstant(Val, MVT::i32); Ops.push_back(SDVal); } else { - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); } } EVT ReturnValueVT = N->getValueType(0); @@ -1175,9 +1168,6 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) { SDNode* Result; int32_t Val = cast<ConstantSDNode>(N)->getSExtValue(); if (Val == -1) { - unsigned NewIntReg = TM.getInstrInfo()->createVR(MF, MVT(MVT::i32)); - SDValue Reg = CurDAG->getRegister(NewIntReg, MVT::i32); - // Create the IntReg = 1 node. SDNode* IntRegTFR = CurDAG->getMachineNode(Hexagon::TFRI, dl, MVT::i32, @@ -1188,7 +1178,7 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) { SDValue(IntRegTFR, 0)); // not(Pd) - SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_pp, dl, MVT::i1, + SDNode* NotPd = CurDAG->getMachineNode(Hexagon::NOT_p, dl, MVT::i1, SDValue(Pd, 0)); // xor(not(Pd)) diff --git a/lib/Target/Hexagon/HexagonISelLowering.cpp b/lib/Target/Hexagon/HexagonISelLowering.cpp index 0ac3cf0..ed4b840 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.cpp +++ b/lib/Target/Hexagon/HexagonISelLowering.cpp @@ -113,8 +113,6 @@ CC_Hexagon_VarArg (unsigned ValNo, MVT ValVT, return false; } llvm_unreachable(0); - - return true; } @@ -305,9 +303,6 @@ HexagonTargetLowering::LowerReturn(SDValue Chain, // Analyze return values of ISD::RET CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); - SDValue StackPtr = DAG.getRegister(TM.getRegisterInfo()->getStackRegister(), - MVT::i32); - // If this is the first return lowered for this function, add the regs to the // liveout set for the function. if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { @@ -320,8 +315,6 @@ HexagonTargetLowering::LowerReturn(SDValue Chain, // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; - SDValue Ret = OutVals[i]; - ISD::ArgFlagsTy Flags = Outs[i].Flags; Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag); @@ -378,7 +371,7 @@ HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, SDValue HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -456,7 +449,7 @@ HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee, switch (VA.getLocInfo()) { default: // Loc info must be one of Full, SExt, ZExt, or AExt. - assert(0 && "Unknown loc info!"); + llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: break; case CCValAssign::SExt: @@ -650,7 +643,7 @@ bool HexagonTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, return false; } - bool isInc; + bool isInc = false; bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, isInc, DAG); // ShiftAmount = number of left-shifted bits in the Hexagon instruction. @@ -1305,6 +1298,7 @@ HexagonTargetLowering::HexagonTargetLowering(HexagonTargetMachine // Needed for DYNAMIC_STACKALLOC expansion. unsigned StackRegister = TM.getRegisterInfo()->getStackRegister(); setStackPointerRegisterToSaveRestore(StackRegister); + setSchedulingPreference(Sched::VLIW); } @@ -1351,12 +1345,12 @@ bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { SDValue HexagonTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - default: assert(0 && "Should not custom lower this!"); + default: llvm_unreachable("Should not custom lower this!"); // Frame & Return address. Currently unimplemented. case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::GlobalTLSAddress: - assert(0 && "TLS not implemented for Hexagon."); + llvm_unreachable("TLS not implemented for Hexagon."); case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); case ISD::GlobalAddress: return LowerGLOBALADDRESS(Op, DAG); @@ -1388,10 +1382,8 @@ const { FuncInfo->addAllocaAdjustInst(MI); return BB; } - default: - assert(false && "Unexpected instr type to insert"); + default: llvm_unreachable("Unexpected instr type to insert"); } // switch - return NULL; } //===----------------------------------------------------------------------===// @@ -1407,7 +1399,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const case 'r': // R0-R31 switch (VT.getSimpleVT().SimpleTy) { default: - assert(0 && "getRegForInlineAsmConstraint Unhandled data type"); + llvm_unreachable("getRegForInlineAsmConstraint Unhandled data type"); case MVT::i32: case MVT::i16: case MVT::i8: @@ -1416,7 +1408,7 @@ HexagonTargetLowering::getRegForInlineAsmConstraint(const return std::make_pair(0U, Hexagon::DoubleRegsRegisterClass); } default: - assert(0 && "Unknown asm register class"); + llvm_unreachable("Unknown asm register class"); } } diff --git a/lib/Target/Hexagon/HexagonISelLowering.h b/lib/Target/Hexagon/HexagonISelLowering.h index b327615..5396486 100644 --- a/lib/Target/Hexagon/HexagonISelLowering.h +++ b/lib/Target/Hexagon/HexagonISelLowering.h @@ -1,4 +1,4 @@ -//==-- HexagonISelLowering.h - Hexagon DAG Lowering Interface ----*- C++ -*-==// +//===-- HexagonISelLowering.h - Hexagon DAG Lowering Interface --*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -96,7 +96,7 @@ namespace llvm { SDValue LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, diff --git a/lib/Target/Hexagon/HexagonImmediates.td b/lib/Target/Hexagon/HexagonImmediates.td index 1e3fcb8..18589a2 100644 --- a/lib/Target/Hexagon/HexagonImmediates.td +++ b/lib/Target/Hexagon/HexagonImmediates.td @@ -1,4 +1,4 @@ -//=- HexagonImmediates.td - Hexagon immediate processing --*- tablegen -*-=// +//===- HexagonImmediates.td - Hexagon immediate processing -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -52,12 +52,12 @@ def s10Imm : Operand<i32> { let PrintMethod = "printHexagonImmOperand"; } -def s8Imm : Operand<i32> { +def s9Imm : Operand<i32> { // For now, we use a generic print function for all operands. let PrintMethod = "printHexagonImmOperand"; } -def s9Imm : Operand<i32> { +def s8Imm : Operand<i32> { // For now, we use a generic print function for all operands. let PrintMethod = "printHexagonImmOperand"; } @@ -197,6 +197,11 @@ def u2Imm : Operand<i32> { let PrintMethod = "printHexagonImmOperand"; } +def u1Imm : Operand<i32> { + // For now, we use a generic print function for all operands. + let PrintMethod = "printHexagonImmOperand"; +} + def n8Imm : Operand<i32> { // For now, we use a generic print function for all operands. let PrintMethod = "printHexagonImmOperand"; @@ -207,6 +212,11 @@ def m6Imm : Operand<i32> { let PrintMethod = "printHexagonImmOperand"; } +def nOneImm : Operand<i32> { + // For now, we use a generic print function for all operands. + let PrintMethod = "printHexagonNOneImmOperand"; +} + // // Immediate predicates // @@ -489,3 +499,10 @@ def n8ImmPred : PatLeaf<(i32 imm), [{ int64_t v = (int64_t)N->getSExtValue(); return (-255 <= v && v <= 0); }]>; + +def nOneImmPred : PatLeaf<(i32 imm), [{ + // nOneImmPred predicate - True if the immediate is -1. + int64_t v = (int64_t)N->getSExtValue(); + return (-1 == v); +}]>; + diff --git a/lib/Target/Hexagon/HexagonInstrFormats.td b/lib/Target/Hexagon/HexagonInstrFormats.td index 7e92776..c9f16fb 100644 --- a/lib/Target/Hexagon/HexagonInstrFormats.td +++ b/lib/Target/Hexagon/HexagonInstrFormats.td @@ -7,28 +7,42 @@ // //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Hexagon Intruction Flags + +// +// *** Must match HexagonBaseInfo.h *** +//===----------------------------------------------------------------------===// + + +//===----------------------------------------------------------------------===// +// Intruction Class Declaration + +//===----------------------------------------------------------------------===// + class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern, - string cstr, - InstrItinClass itin> : Instruction { + string cstr, InstrItinClass itin> : Instruction { field bits<32> Inst; let Namespace = "Hexagon"; -/* Commented out for Hexagon - bits<2> op; - let Inst{31-30} = op; */ // Top two bits are the 'op' field - dag OutOperandList = outs; dag InOperandList = ins; let AsmString = asmstr; let Pattern = pattern; let Constraints = cstr; let Itinerary = itin; + + // *** The code below must match HexagonBaseInfo.h *** + + // Predicated instructions. + bits<1> isPredicated = 0; + let TSFlags{1} = isPredicated; + + // *** The code above must match HexagonBaseInfo.h *** } -//----------------------------------------------------------------------------// +//===----------------------------------------------------------------------===// // Intruction Classes Definitions + -//----------------------------------------------------------------------------// +//===----------------------------------------------------------------------===// // LD Instruction Class in V2/V3/V4. // Definition of the instruction class NOT CHANGED. @@ -174,9 +188,9 @@ class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> : InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO>; -//----------------------------------------------------------------------------// +//===----------------------------------------------------------------------===// // Intruction Classes Definitions - -//----------------------------------------------------------------------------// +//===----------------------------------------------------------------------===// // diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 69a50d7..07872d4 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1,4 +1,4 @@ -//=- HexagonInstrInfo.cpp - Hexagon Instruction Information -------*- C++ -*-=// +//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===// // // The LLVM Compiler Infrastructure // @@ -15,19 +15,18 @@ #include "HexagonInstrInfo.h" #include "HexagonSubtarget.h" #include "Hexagon.h" -#include "llvm/Support/MathExtras.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/Support/MathExtras.h" #define GET_INSTRINFO_CTOR #include "HexagonGenInstrInfo.inc" - -#include <iostream> - +#include "HexagonGenDFAPacketizer.inc" using namespace llvm; @@ -125,16 +124,16 @@ HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, DebugLoc DL) const{ int BOpc = Hexagon::JMP; - int BccOpc = Hexagon::JMP_Pred; + int BccOpc = Hexagon::JMP_c; assert(TBB && "InsertBranch must not be told to insert a fallthrough"); int regPos = 0; // Check if ReverseBranchCondition has asked to reverse this branch // If we want to reverse the branch an odd number of times, we want - // JMP_PredNot. + // JMP_cNot. if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) { - BccOpc = Hexagon::JMP_PredNot; + BccOpc = Hexagon::JMP_cNot; regPos = 1; } @@ -222,13 +221,13 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, TBB = LastInst->getOperand(0).getMBB(); return false; } - if (LastInst->getOpcode() == Hexagon::JMP_Pred) { + if (LastInst->getOpcode() == Hexagon::JMP_c) { // Block ends with fall-through true condbranch. TBB = LastInst->getOperand(1).getMBB(); Cond.push_back(LastInst->getOperand(0)); return false; } - if (LastInst->getOpcode() == Hexagon::JMP_PredNot) { + if (LastInst->getOpcode() == Hexagon::JMP_cNot) { // Block ends with fall-through false condbranch. TBB = LastInst->getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -249,7 +248,7 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it. if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) || - (SecondLastInst->getOpcode() == Hexagon::JMP_Pred)) && + (SecondLastInst->getOpcode() == Hexagon::JMP_c)) && LastInst->getOpcode() == Hexagon::JMP) { TBB = SecondLastInst->getOperand(1).getMBB(); Cond.push_back(SecondLastInst->getOperand(0)); @@ -257,8 +256,8 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, return false; } - // If the block ends with Hexagon::JMP_PredNot and Hexagon:JMP, handle it. - if ((SecondLastInst->getOpcode() == Hexagon::JMP_PredNot) && + // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it. + if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) && LastInst->getOpcode() == Hexagon::JMP) { TBB = SecondLastInst->getOperand(1).getMBB(); Cond.push_back(MachineOperand::CreateImm(0)); @@ -285,8 +284,8 @@ bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { int BOpc = Hexagon::JMP; - int BccOpc = Hexagon::JMP_Pred; - int BccOpcNot = Hexagon::JMP_PredNot; + int BccOpc = Hexagon::JMP_c; + int BccOpcNot = Hexagon::JMP_cNot; MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin()) return 0; @@ -347,9 +346,9 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB, if (Hexagon::CRRegsRegClass.contains(DestReg, SrcReg)) { BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg); return; - } - - assert (0 && "Unimplemented"); + } + + llvm_unreachable("Unimplemented"); } @@ -384,7 +383,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); } else { - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); } } @@ -396,8 +395,7 @@ void HexagonInstrInfo::storeRegToAddr( const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - assert(0 && "Unimplemented"); - return; + llvm_unreachable("Unimplemented"); } @@ -428,7 +426,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO); } else { - assert(0 && "Can't store this register to stack slot"); + llvm_unreachable("Can't store this register to stack slot"); } } @@ -437,7 +435,7 @@ void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { - assert(0 && "Unimplemented"); + llvm_unreachable("Unimplemented"); } @@ -461,7 +459,7 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { } else if (VT == MVT::i64) { TRC = Hexagon::DoubleRegsRegisterClass; } else { - assert(0 && "Cannot handle this register class"); + llvm_unreachable("Cannot handle this register class"); } unsigned NewReg = RegInfo.createVirtualRegister(TRC); @@ -469,6 +467,7 @@ unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const { } + bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { bool isPred = MI->getDesc().isPredicable(); @@ -553,15 +552,469 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const { case Hexagon::JMPR: return false; - return true; - - default: - return true; } return true; } +unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const { + switch(Opc) { + case Hexagon::TFR_cPt: + return Hexagon::TFR_cNotPt; + case Hexagon::TFR_cNotPt: + return Hexagon::TFR_cPt; + + case Hexagon::TFRI_cPt: + return Hexagon::TFRI_cNotPt; + case Hexagon::TFRI_cNotPt: + return Hexagon::TFRI_cPt; + + case Hexagon::JMP_c: + return Hexagon::JMP_cNot; + case Hexagon::JMP_cNot: + return Hexagon::JMP_c; + + case Hexagon::ADD_ri_cPt: + return Hexagon::ADD_ri_cNotPt; + case Hexagon::ADD_ri_cNotPt: + return Hexagon::ADD_ri_cPt; + + case Hexagon::ADD_rr_cPt: + return Hexagon::ADD_rr_cNotPt; + case Hexagon::ADD_rr_cNotPt: + return Hexagon::ADD_rr_cPt; + + case Hexagon::XOR_rr_cPt: + return Hexagon::XOR_rr_cNotPt; + case Hexagon::XOR_rr_cNotPt: + return Hexagon::XOR_rr_cPt; + + case Hexagon::AND_rr_cPt: + return Hexagon::AND_rr_cNotPt; + case Hexagon::AND_rr_cNotPt: + return Hexagon::AND_rr_cPt; + + case Hexagon::OR_rr_cPt: + return Hexagon::OR_rr_cNotPt; + case Hexagon::OR_rr_cNotPt: + return Hexagon::OR_rr_cPt; + + case Hexagon::SUB_rr_cPt: + return Hexagon::SUB_rr_cNotPt; + case Hexagon::SUB_rr_cNotPt: + return Hexagon::SUB_rr_cPt; + + case Hexagon::COMBINE_rr_cPt: + return Hexagon::COMBINE_rr_cNotPt; + case Hexagon::COMBINE_rr_cNotPt: + return Hexagon::COMBINE_rr_cPt; + + case Hexagon::ASLH_cPt_V4: + return Hexagon::ASLH_cNotPt_V4; + case Hexagon::ASLH_cNotPt_V4: + return Hexagon::ASLH_cPt_V4; + + case Hexagon::ASRH_cPt_V4: + return Hexagon::ASRH_cNotPt_V4; + case Hexagon::ASRH_cNotPt_V4: + return Hexagon::ASRH_cPt_V4; + + case Hexagon::SXTB_cPt_V4: + return Hexagon::SXTB_cNotPt_V4; + case Hexagon::SXTB_cNotPt_V4: + return Hexagon::SXTB_cPt_V4; + + case Hexagon::SXTH_cPt_V4: + return Hexagon::SXTH_cNotPt_V4; + case Hexagon::SXTH_cNotPt_V4: + return Hexagon::SXTH_cPt_V4; + + case Hexagon::ZXTB_cPt_V4: + return Hexagon::ZXTB_cNotPt_V4; + case Hexagon::ZXTB_cNotPt_V4: + return Hexagon::ZXTB_cPt_V4; + + case Hexagon::ZXTH_cPt_V4: + return Hexagon::ZXTH_cNotPt_V4; + case Hexagon::ZXTH_cNotPt_V4: + return Hexagon::ZXTH_cPt_V4; + + + case Hexagon::JMPR_cPt: + return Hexagon::JMPR_cNotPt; + case Hexagon::JMPR_cNotPt: + return Hexagon::JMPR_cPt; + + // V4 indexed+scaled load. + case Hexagon::LDrid_indexed_cPt_V4: + return Hexagon::LDrid_indexed_cNotPt_V4; + case Hexagon::LDrid_indexed_cNotPt_V4: + return Hexagon::LDrid_indexed_cPt_V4; + + case Hexagon::LDrid_indexed_shl_cPt_V4: + return Hexagon::LDrid_indexed_shl_cNotPt_V4; + case Hexagon::LDrid_indexed_shl_cNotPt_V4: + return Hexagon::LDrid_indexed_shl_cPt_V4; + + case Hexagon::LDrib_indexed_cPt_V4: + return Hexagon::LDrib_indexed_cNotPt_V4; + case Hexagon::LDrib_indexed_cNotPt_V4: + return Hexagon::LDrib_indexed_cPt_V4; + + case Hexagon::LDriub_indexed_cPt_V4: + return Hexagon::LDriub_indexed_cNotPt_V4; + case Hexagon::LDriub_indexed_cNotPt_V4: + return Hexagon::LDriub_indexed_cPt_V4; + + case Hexagon::LDrib_indexed_shl_cPt_V4: + return Hexagon::LDrib_indexed_shl_cNotPt_V4; + case Hexagon::LDrib_indexed_shl_cNotPt_V4: + return Hexagon::LDrib_indexed_shl_cPt_V4; + + case Hexagon::LDriub_indexed_shl_cPt_V4: + return Hexagon::LDriub_indexed_shl_cNotPt_V4; + case Hexagon::LDriub_indexed_shl_cNotPt_V4: + return Hexagon::LDriub_indexed_shl_cPt_V4; + + case Hexagon::LDrih_indexed_cPt_V4: + return Hexagon::LDrih_indexed_cNotPt_V4; + case Hexagon::LDrih_indexed_cNotPt_V4: + return Hexagon::LDrih_indexed_cPt_V4; + + case Hexagon::LDriuh_indexed_cPt_V4: + return Hexagon::LDriuh_indexed_cNotPt_V4; + case Hexagon::LDriuh_indexed_cNotPt_V4: + return Hexagon::LDriuh_indexed_cPt_V4; + + case Hexagon::LDrih_indexed_shl_cPt_V4: + return Hexagon::LDrih_indexed_shl_cNotPt_V4; + case Hexagon::LDrih_indexed_shl_cNotPt_V4: + return Hexagon::LDrih_indexed_shl_cPt_V4; + + case Hexagon::LDriuh_indexed_shl_cPt_V4: + return Hexagon::LDriuh_indexed_shl_cNotPt_V4; + case Hexagon::LDriuh_indexed_shl_cNotPt_V4: + return Hexagon::LDriuh_indexed_shl_cPt_V4; + + case Hexagon::LDriw_indexed_cPt_V4: + return Hexagon::LDriw_indexed_cNotPt_V4; + case Hexagon::LDriw_indexed_cNotPt_V4: + return Hexagon::LDriw_indexed_cPt_V4; + + case Hexagon::LDriw_indexed_shl_cPt_V4: + return Hexagon::LDriw_indexed_shl_cNotPt_V4; + case Hexagon::LDriw_indexed_shl_cNotPt_V4: + return Hexagon::LDriw_indexed_shl_cPt_V4; + + // Byte. + case Hexagon::POST_STbri_cPt: + return Hexagon::POST_STbri_cNotPt; + case Hexagon::POST_STbri_cNotPt: + return Hexagon::POST_STbri_cPt; + + case Hexagon::STrib_cPt: + return Hexagon::STrib_cNotPt; + case Hexagon::STrib_cNotPt: + return Hexagon::STrib_cPt; + + case Hexagon::STrib_indexed_cPt: + return Hexagon::STrib_indexed_cNotPt; + case Hexagon::STrib_indexed_cNotPt: + return Hexagon::STrib_indexed_cPt; + + case Hexagon::STrib_imm_cPt_V4: + return Hexagon::STrib_imm_cNotPt_V4; + case Hexagon::STrib_imm_cNotPt_V4: + return Hexagon::STrib_imm_cPt_V4; + + case Hexagon::STrib_indexed_shl_cPt_V4: + return Hexagon::STrib_indexed_shl_cNotPt_V4; + case Hexagon::STrib_indexed_shl_cNotPt_V4: + return Hexagon::STrib_indexed_shl_cPt_V4; + + // Halfword. + case Hexagon::POST_SThri_cPt: + return Hexagon::POST_SThri_cNotPt; + case Hexagon::POST_SThri_cNotPt: + return Hexagon::POST_SThri_cPt; + + case Hexagon::STrih_cPt: + return Hexagon::STrih_cNotPt; + case Hexagon::STrih_cNotPt: + return Hexagon::STrih_cPt; + + case Hexagon::STrih_indexed_cPt: + return Hexagon::STrih_indexed_cNotPt; + case Hexagon::STrih_indexed_cNotPt: + return Hexagon::STrih_indexed_cPt; + + case Hexagon::STrih_imm_cPt_V4: + return Hexagon::STrih_imm_cNotPt_V4; + case Hexagon::STrih_imm_cNotPt_V4: + return Hexagon::STrih_imm_cPt_V4; + + case Hexagon::STrih_indexed_shl_cPt_V4: + return Hexagon::STrih_indexed_shl_cNotPt_V4; + case Hexagon::STrih_indexed_shl_cNotPt_V4: + return Hexagon::STrih_indexed_shl_cPt_V4; + + // Word. + case Hexagon::POST_STwri_cPt: + return Hexagon::POST_STwri_cNotPt; + case Hexagon::POST_STwri_cNotPt: + return Hexagon::POST_STwri_cPt; + + case Hexagon::STriw_cPt: + return Hexagon::STriw_cNotPt; + case Hexagon::STriw_cNotPt: + return Hexagon::STriw_cPt; + + case Hexagon::STriw_indexed_cPt: + return Hexagon::STriw_indexed_cNotPt; + case Hexagon::STriw_indexed_cNotPt: + return Hexagon::STriw_indexed_cPt; + + case Hexagon::STriw_indexed_shl_cPt_V4: + return Hexagon::STriw_indexed_shl_cNotPt_V4; + case Hexagon::STriw_indexed_shl_cNotPt_V4: + return Hexagon::STriw_indexed_shl_cPt_V4; + + case Hexagon::STriw_imm_cPt_V4: + return Hexagon::STriw_imm_cNotPt_V4; + case Hexagon::STriw_imm_cNotPt_V4: + return Hexagon::STriw_imm_cPt_V4; + + // Double word. + case Hexagon::POST_STdri_cPt: + return Hexagon::POST_STdri_cNotPt; + case Hexagon::POST_STdri_cNotPt: + return Hexagon::POST_STdri_cPt; + + case Hexagon::STrid_cPt: + return Hexagon::STrid_cNotPt; + case Hexagon::STrid_cNotPt: + return Hexagon::STrid_cPt; + + case Hexagon::STrid_indexed_cPt: + return Hexagon::STrid_indexed_cNotPt; + case Hexagon::STrid_indexed_cNotPt: + return Hexagon::STrid_indexed_cPt; + + case Hexagon::STrid_indexed_shl_cPt_V4: + return Hexagon::STrid_indexed_shl_cNotPt_V4; + case Hexagon::STrid_indexed_shl_cNotPt_V4: + return Hexagon::STrid_indexed_shl_cPt_V4; + + // Load. + case Hexagon::LDrid_cPt: + return Hexagon::LDrid_cNotPt; + case Hexagon::LDrid_cNotPt: + return Hexagon::LDrid_cPt; + + case Hexagon::LDriw_cPt: + return Hexagon::LDriw_cNotPt; + case Hexagon::LDriw_cNotPt: + return Hexagon::LDriw_cPt; + + case Hexagon::LDrih_cPt: + return Hexagon::LDrih_cNotPt; + case Hexagon::LDrih_cNotPt: + return Hexagon::LDrih_cPt; + + case Hexagon::LDriuh_cPt: + return Hexagon::LDriuh_cNotPt; + case Hexagon::LDriuh_cNotPt: + return Hexagon::LDriuh_cPt; + + case Hexagon::LDrib_cPt: + return Hexagon::LDrib_cNotPt; + case Hexagon::LDrib_cNotPt: + return Hexagon::LDrib_cPt; + + case Hexagon::LDriub_cPt: + return Hexagon::LDriub_cNotPt; + case Hexagon::LDriub_cNotPt: + return Hexagon::LDriub_cPt; + + // Load Indexed. + case Hexagon::LDrid_indexed_cPt: + return Hexagon::LDrid_indexed_cNotPt; + case Hexagon::LDrid_indexed_cNotPt: + return Hexagon::LDrid_indexed_cPt; + + case Hexagon::LDriw_indexed_cPt: + return Hexagon::LDriw_indexed_cNotPt; + case Hexagon::LDriw_indexed_cNotPt: + return Hexagon::LDriw_indexed_cPt; + + case Hexagon::LDrih_indexed_cPt: + return Hexagon::LDrih_indexed_cNotPt; + case Hexagon::LDrih_indexed_cNotPt: + return Hexagon::LDrih_indexed_cPt; + + case Hexagon::LDriuh_indexed_cPt: + return Hexagon::LDriuh_indexed_cNotPt; + case Hexagon::LDriuh_indexed_cNotPt: + return Hexagon::LDriuh_indexed_cPt; + + case Hexagon::LDrib_indexed_cPt: + return Hexagon::LDrib_indexed_cNotPt; + case Hexagon::LDrib_indexed_cNotPt: + return Hexagon::LDrib_indexed_cPt; + + case Hexagon::LDriub_indexed_cPt: + return Hexagon::LDriub_indexed_cNotPt; + case Hexagon::LDriub_indexed_cNotPt: + return Hexagon::LDriub_indexed_cPt; + + // Post Inc Load. + case Hexagon::POST_LDrid_cPt: + return Hexagon::POST_LDrid_cNotPt; + case Hexagon::POST_LDriw_cNotPt: + return Hexagon::POST_LDriw_cPt; + + case Hexagon::POST_LDrih_cPt: + return Hexagon::POST_LDrih_cNotPt; + case Hexagon::POST_LDrih_cNotPt: + return Hexagon::POST_LDrih_cPt; + + case Hexagon::POST_LDriuh_cPt: + return Hexagon::POST_LDriuh_cNotPt; + case Hexagon::POST_LDriuh_cNotPt: + return Hexagon::POST_LDriuh_cPt; + + case Hexagon::POST_LDrib_cPt: + return Hexagon::POST_LDrib_cNotPt; + case Hexagon::POST_LDrib_cNotPt: + return Hexagon::POST_LDrib_cPt; + + case Hexagon::POST_LDriub_cPt: + return Hexagon::POST_LDriub_cNotPt; + case Hexagon::POST_LDriub_cNotPt: + return Hexagon::POST_LDriub_cPt; + + // Dealloc_return. + case Hexagon::DEALLOC_RET_cPt_V4: + return Hexagon::DEALLOC_RET_cNotPt_V4; + case Hexagon::DEALLOC_RET_cNotPt_V4: + return Hexagon::DEALLOC_RET_cPt_V4; + + // New Value Jump. + // JMPEQ_ri - with -1. + case Hexagon::JMP_EQriPtneg_nv_V4: + return Hexagon::JMP_EQriNotPtneg_nv_V4; + case Hexagon::JMP_EQriNotPtneg_nv_V4: + return Hexagon::JMP_EQriPtneg_nv_V4; + + case Hexagon::JMP_EQriPntneg_nv_V4: + return Hexagon::JMP_EQriNotPntneg_nv_V4; + case Hexagon::JMP_EQriNotPntneg_nv_V4: + return Hexagon::JMP_EQriPntneg_nv_V4; + + // JMPEQ_ri. + case Hexagon::JMP_EQriPt_nv_V4: + return Hexagon::JMP_EQriNotPt_nv_V4; + case Hexagon::JMP_EQriNotPt_nv_V4: + return Hexagon::JMP_EQriPt_nv_V4; + + case Hexagon::JMP_EQriPnt_nv_V4: + return Hexagon::JMP_EQriNotPnt_nv_V4; + case Hexagon::JMP_EQriNotPnt_nv_V4: + return Hexagon::JMP_EQriPnt_nv_V4; + + // JMPEQ_rr. + case Hexagon::JMP_EQrrPt_nv_V4: + return Hexagon::JMP_EQrrNotPt_nv_V4; + case Hexagon::JMP_EQrrNotPt_nv_V4: + return Hexagon::JMP_EQrrPt_nv_V4; + + case Hexagon::JMP_EQrrPnt_nv_V4: + return Hexagon::JMP_EQrrNotPnt_nv_V4; + case Hexagon::JMP_EQrrNotPnt_nv_V4: + return Hexagon::JMP_EQrrPnt_nv_V4; + + // JMPGT_ri - with -1. + case Hexagon::JMP_GTriPtneg_nv_V4: + return Hexagon::JMP_GTriNotPtneg_nv_V4; + case Hexagon::JMP_GTriNotPtneg_nv_V4: + return Hexagon::JMP_GTriPtneg_nv_V4; + + case Hexagon::JMP_GTriPntneg_nv_V4: + return Hexagon::JMP_GTriNotPntneg_nv_V4; + case Hexagon::JMP_GTriNotPntneg_nv_V4: + return Hexagon::JMP_GTriPntneg_nv_V4; + + // JMPGT_ri. + case Hexagon::JMP_GTriPt_nv_V4: + return Hexagon::JMP_GTriNotPt_nv_V4; + case Hexagon::JMP_GTriNotPt_nv_V4: + return Hexagon::JMP_GTriPt_nv_V4; + + case Hexagon::JMP_GTriPnt_nv_V4: + return Hexagon::JMP_GTriNotPnt_nv_V4; + case Hexagon::JMP_GTriNotPnt_nv_V4: + return Hexagon::JMP_GTriPnt_nv_V4; + + // JMPGT_rr. + case Hexagon::JMP_GTrrPt_nv_V4: + return Hexagon::JMP_GTrrNotPt_nv_V4; + case Hexagon::JMP_GTrrNotPt_nv_V4: + return Hexagon::JMP_GTrrPt_nv_V4; + + case Hexagon::JMP_GTrrPnt_nv_V4: + return Hexagon::JMP_GTrrNotPnt_nv_V4; + case Hexagon::JMP_GTrrNotPnt_nv_V4: + return Hexagon::JMP_GTrrPnt_nv_V4; + + // JMPGT_rrdn. + case Hexagon::JMP_GTrrdnPt_nv_V4: + return Hexagon::JMP_GTrrdnNotPt_nv_V4; + case Hexagon::JMP_GTrrdnNotPt_nv_V4: + return Hexagon::JMP_GTrrdnPt_nv_V4; + + case Hexagon::JMP_GTrrdnPnt_nv_V4: + return Hexagon::JMP_GTrrdnNotPnt_nv_V4; + case Hexagon::JMP_GTrrdnNotPnt_nv_V4: + return Hexagon::JMP_GTrrdnPnt_nv_V4; + + // JMPGTU_ri. + case Hexagon::JMP_GTUriPt_nv_V4: + return Hexagon::JMP_GTUriNotPt_nv_V4; + case Hexagon::JMP_GTUriNotPt_nv_V4: + return Hexagon::JMP_GTUriPt_nv_V4; + + case Hexagon::JMP_GTUriPnt_nv_V4: + return Hexagon::JMP_GTUriNotPnt_nv_V4; + case Hexagon::JMP_GTUriNotPnt_nv_V4: + return Hexagon::JMP_GTUriPnt_nv_V4; + + // JMPGTU_rr. + case Hexagon::JMP_GTUrrPt_nv_V4: + return Hexagon::JMP_GTUrrNotPt_nv_V4; + case Hexagon::JMP_GTUrrNotPt_nv_V4: + return Hexagon::JMP_GTUrrPt_nv_V4; + + case Hexagon::JMP_GTUrrPnt_nv_V4: + return Hexagon::JMP_GTUrrNotPnt_nv_V4; + case Hexagon::JMP_GTUrrNotPnt_nv_V4: + return Hexagon::JMP_GTUrrPnt_nv_V4; + + // JMPGTU_rrdn. + case Hexagon::JMP_GTUrrdnPt_nv_V4: + return Hexagon::JMP_GTUrrdnNotPt_nv_V4; + case Hexagon::JMP_GTUrrdnNotPt_nv_V4: + return Hexagon::JMP_GTUrrdnPt_nv_V4; + + case Hexagon::JMP_GTUrrdnPnt_nv_V4: + return Hexagon::JMP_GTUrrdnNotPnt_nv_V4; + case Hexagon::JMP_GTUrrdnNotPnt_nv_V4: + return Hexagon::JMP_GTUrrdnPnt_nv_V4; + + default: + llvm_unreachable("Unexpected predicated instruction"); + } +} + int HexagonInstrInfo:: getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { @@ -573,8 +1026,8 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { return !invertPredicate ? Hexagon::TFRI_cPt : Hexagon::TFRI_cNotPt; case Hexagon::JMP: - return !invertPredicate ? Hexagon::JMP_Pred : - Hexagon::JMP_PredNot; + return !invertPredicate ? Hexagon::JMP_c : + Hexagon::JMP_cNot; case Hexagon::ADD_ri: return !invertPredicate ? Hexagon::ADD_ri_cPt : Hexagon::ADD_ri_cNotPt; @@ -793,9 +1246,8 @@ getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const { case Hexagon::DEALLOC_RET_V4: return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 : Hexagon::DEALLOC_RET_cNotPt_V4; - default: - assert(false && "Unexpected predicable instruction"); } + llvm_unreachable("Unexpected predicable instruction"); } @@ -827,7 +1279,7 @@ PredicateInstruction(MachineInstr *MI, } else if (MO.isImm()) { MI->getOperand(oper+1).ChangeToImmediate(MO.getImm()); } else { - assert(false && "Unexpected operand type"); + llvm_unreachable("Unexpected operand type"); } } @@ -866,213 +1318,9 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB, bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const { - switch (MI->getOpcode()) { - case Hexagon::TFR_cPt: - case Hexagon::TFR_cNotPt: - case Hexagon::TFRI_cPt: - case Hexagon::TFRI_cNotPt: - case Hexagon::TFR_cdnPt: - case Hexagon::TFR_cdnNotPt: - case Hexagon::TFRI_cdnPt: - case Hexagon::TFRI_cdnNotPt: - return true; - - case Hexagon::JMP_Pred: - case Hexagon::JMP_PredNot: - case Hexagon::BRCOND: - case Hexagon::JMP_PredPt: - case Hexagon::JMP_PredNotPt: - case Hexagon::JMP_PredPnt: - case Hexagon::JMP_PredNotPnt: - return true; + const uint64_t F = MI->getDesc().TSFlags; - case Hexagon::LDrid_indexed_cPt_V4 : - case Hexagon::LDrid_indexed_cdnPt_V4 : - case Hexagon::LDrid_indexed_cNotPt_V4 : - case Hexagon::LDrid_indexed_cdnNotPt_V4 : - case Hexagon::LDrid_indexed_shl_cPt_V4 : - case Hexagon::LDrid_indexed_shl_cdnPt_V4 : - case Hexagon::LDrid_indexed_shl_cNotPt_V4 : - case Hexagon::LDrid_indexed_shl_cdnNotPt_V4 : - case Hexagon::LDrib_indexed_cPt_V4 : - case Hexagon::LDrib_indexed_cdnPt_V4 : - case Hexagon::LDrib_indexed_cNotPt_V4 : - case Hexagon::LDrib_indexed_cdnNotPt_V4 : - case Hexagon::LDrib_indexed_shl_cPt_V4 : - case Hexagon::LDrib_indexed_shl_cdnPt_V4 : - case Hexagon::LDrib_indexed_shl_cNotPt_V4 : - case Hexagon::LDrib_indexed_shl_cdnNotPt_V4 : - case Hexagon::LDriub_indexed_cPt_V4 : - case Hexagon::LDriub_indexed_cdnPt_V4 : - case Hexagon::LDriub_indexed_cNotPt_V4 : - case Hexagon::LDriub_indexed_cdnNotPt_V4 : - case Hexagon::LDriub_indexed_shl_cPt_V4 : - case Hexagon::LDriub_indexed_shl_cdnPt_V4 : - case Hexagon::LDriub_indexed_shl_cNotPt_V4 : - case Hexagon::LDriub_indexed_shl_cdnNotPt_V4 : - case Hexagon::LDrih_indexed_cPt_V4 : - case Hexagon::LDrih_indexed_cdnPt_V4 : - case Hexagon::LDrih_indexed_cNotPt_V4 : - case Hexagon::LDrih_indexed_cdnNotPt_V4 : - case Hexagon::LDrih_indexed_shl_cPt_V4 : - case Hexagon::LDrih_indexed_shl_cdnPt_V4 : - case Hexagon::LDrih_indexed_shl_cNotPt_V4 : - case Hexagon::LDrih_indexed_shl_cdnNotPt_V4 : - case Hexagon::LDriuh_indexed_cPt_V4 : - case Hexagon::LDriuh_indexed_cdnPt_V4 : - case Hexagon::LDriuh_indexed_cNotPt_V4 : - case Hexagon::LDriuh_indexed_cdnNotPt_V4 : - case Hexagon::LDriuh_indexed_shl_cPt_V4 : - case Hexagon::LDriuh_indexed_shl_cdnPt_V4 : - case Hexagon::LDriuh_indexed_shl_cNotPt_V4 : - case Hexagon::LDriuh_indexed_shl_cdnNotPt_V4 : - case Hexagon::LDriw_indexed_cPt_V4 : - case Hexagon::LDriw_indexed_cdnPt_V4 : - case Hexagon::LDriw_indexed_cNotPt_V4 : - case Hexagon::LDriw_indexed_cdnNotPt_V4 : - case Hexagon::LDriw_indexed_shl_cPt_V4 : - case Hexagon::LDriw_indexed_shl_cdnPt_V4 : - case Hexagon::LDriw_indexed_shl_cNotPt_V4 : - case Hexagon::LDriw_indexed_shl_cdnNotPt_V4 : - return true; - - case Hexagon::LDrid_cPt : - case Hexagon::LDrid_cNotPt : - case Hexagon::LDrid_indexed_cPt : - case Hexagon::LDrid_indexed_cNotPt : - case Hexagon::POST_LDrid_cPt : - case Hexagon::POST_LDrid_cNotPt : - case Hexagon::LDriw_cPt : - case Hexagon::LDriw_cNotPt : - case Hexagon::LDriw_indexed_cPt : - case Hexagon::LDriw_indexed_cNotPt : - case Hexagon::POST_LDriw_cPt : - case Hexagon::POST_LDriw_cNotPt : - case Hexagon::LDrih_cPt : - case Hexagon::LDrih_cNotPt : - case Hexagon::LDrih_indexed_cPt : - case Hexagon::LDrih_indexed_cNotPt : - case Hexagon::POST_LDrih_cPt : - case Hexagon::POST_LDrih_cNotPt : - case Hexagon::LDrib_cPt : - case Hexagon::LDrib_cNotPt : - case Hexagon::LDrib_indexed_cPt : - case Hexagon::LDrib_indexed_cNotPt : - case Hexagon::POST_LDrib_cPt : - case Hexagon::POST_LDrib_cNotPt : - case Hexagon::LDriuh_cPt : - case Hexagon::LDriuh_cNotPt : - case Hexagon::LDriuh_indexed_cPt : - case Hexagon::LDriuh_indexed_cNotPt : - case Hexagon::POST_LDriuh_cPt : - case Hexagon::POST_LDriuh_cNotPt : - case Hexagon::LDriub_cPt : - case Hexagon::LDriub_cNotPt : - case Hexagon::LDriub_indexed_cPt : - case Hexagon::LDriub_indexed_cNotPt : - case Hexagon::POST_LDriub_cPt : - case Hexagon::POST_LDriub_cNotPt : - return true; - - case Hexagon::LDrid_cdnPt : - case Hexagon::LDrid_cdnNotPt : - case Hexagon::LDrid_indexed_cdnPt : - case Hexagon::LDrid_indexed_cdnNotPt : - case Hexagon::POST_LDrid_cdnPt_V4 : - case Hexagon::POST_LDrid_cdnNotPt_V4 : - case Hexagon::LDriw_cdnPt : - case Hexagon::LDriw_cdnNotPt : - case Hexagon::LDriw_indexed_cdnPt : - case Hexagon::LDriw_indexed_cdnNotPt : - case Hexagon::POST_LDriw_cdnPt_V4 : - case Hexagon::POST_LDriw_cdnNotPt_V4 : - case Hexagon::LDrih_cdnPt : - case Hexagon::LDrih_cdnNotPt : - case Hexagon::LDrih_indexed_cdnPt : - case Hexagon::LDrih_indexed_cdnNotPt : - case Hexagon::POST_LDrih_cdnPt_V4 : - case Hexagon::POST_LDrih_cdnNotPt_V4 : - case Hexagon::LDrib_cdnPt : - case Hexagon::LDrib_cdnNotPt : - case Hexagon::LDrib_indexed_cdnPt : - case Hexagon::LDrib_indexed_cdnNotPt : - case Hexagon::POST_LDrib_cdnPt_V4 : - case Hexagon::POST_LDrib_cdnNotPt_V4 : - case Hexagon::LDriuh_cdnPt : - case Hexagon::LDriuh_cdnNotPt : - case Hexagon::LDriuh_indexed_cdnPt : - case Hexagon::LDriuh_indexed_cdnNotPt : - case Hexagon::POST_LDriuh_cdnPt_V4 : - case Hexagon::POST_LDriuh_cdnNotPt_V4 : - case Hexagon::LDriub_cdnPt : - case Hexagon::LDriub_cdnNotPt : - case Hexagon::LDriub_indexed_cdnPt : - case Hexagon::LDriub_indexed_cdnNotPt : - case Hexagon::POST_LDriub_cdnPt_V4 : - case Hexagon::POST_LDriub_cdnNotPt_V4 : - return true; - - case Hexagon::ADD_ri_cPt: - case Hexagon::ADD_ri_cNotPt: - case Hexagon::ADD_ri_cdnPt: - case Hexagon::ADD_ri_cdnNotPt: - case Hexagon::ADD_rr_cPt: - case Hexagon::ADD_rr_cNotPt: - case Hexagon::ADD_rr_cdnPt: - case Hexagon::ADD_rr_cdnNotPt: - case Hexagon::XOR_rr_cPt: - case Hexagon::XOR_rr_cNotPt: - case Hexagon::XOR_rr_cdnPt: - case Hexagon::XOR_rr_cdnNotPt: - case Hexagon::AND_rr_cPt: - case Hexagon::AND_rr_cNotPt: - case Hexagon::AND_rr_cdnPt: - case Hexagon::AND_rr_cdnNotPt: - case Hexagon::OR_rr_cPt: - case Hexagon::OR_rr_cNotPt: - case Hexagon::OR_rr_cdnPt: - case Hexagon::OR_rr_cdnNotPt: - case Hexagon::SUB_rr_cPt: - case Hexagon::SUB_rr_cNotPt: - case Hexagon::SUB_rr_cdnPt: - case Hexagon::SUB_rr_cdnNotPt: - case Hexagon::COMBINE_rr_cPt: - case Hexagon::COMBINE_rr_cNotPt: - case Hexagon::COMBINE_rr_cdnPt: - case Hexagon::COMBINE_rr_cdnNotPt: - return true; - - case Hexagon::ASLH_cPt_V4: - case Hexagon::ASLH_cNotPt_V4: - case Hexagon::ASRH_cPt_V4: - case Hexagon::ASRH_cNotPt_V4: - case Hexagon::SXTB_cPt_V4: - case Hexagon::SXTB_cNotPt_V4: - case Hexagon::SXTH_cPt_V4: - case Hexagon::SXTH_cNotPt_V4: - case Hexagon::ZXTB_cPt_V4: - case Hexagon::ZXTB_cNotPt_V4: - case Hexagon::ZXTH_cPt_V4: - case Hexagon::ZXTH_cNotPt_V4: - return true; - - case Hexagon::ASLH_cdnPt_V4: - case Hexagon::ASLH_cdnNotPt_V4: - case Hexagon::ASRH_cdnPt_V4: - case Hexagon::ASRH_cdnNotPt_V4: - case Hexagon::SXTB_cdnPt_V4: - case Hexagon::SXTB_cdnNotPt_V4: - case Hexagon::SXTH_cdnPt_V4: - case Hexagon::SXTH_cdnNotPt_V4: - case Hexagon::ZXTB_cdnPt_V4: - case Hexagon::ZXTB_cdnNotPt_V4: - case Hexagon::ZXTH_cdnPt_V4: - case Hexagon::ZXTH_cdnNotPt_V4: - return true; - - default: - return false; - } + return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask); } @@ -1149,7 +1397,6 @@ isValidOffset(const int Opcode, const int Offset) const { case Hexagon::LDriw: case Hexagon::STriw: - case Hexagon::STriwt: assert((Offset % 4 == 0) && "Offset has incorrect alignment"); return (Offset >= Hexagon_MEMW_OFFSET_MIN) && (Offset <= Hexagon_MEMW_OFFSET_MAX); @@ -1243,8 +1490,8 @@ isValidOffset(const int Opcode, const int Offset) const { return true; } - assert(0 && "No offset range is defined for this opcode. Please define it in \ - the above switch statement!"); + llvm_unreachable("No offset range is defined for this opcode. " + "Please define it in the above switch statement!"); } @@ -1273,10 +1520,7 @@ isValidAutoIncImm(const EVT VT, const int Offset) const { return (Offset >= Hexagon_MEMB_AUTOINC_MIN && Offset <= Hexagon_MEMB_AUTOINC_MAX); } - - assert(0 && "Not an auto-inc opc!"); - - return false; + llvm_unreachable("Not an auto-inc opc!"); } @@ -1380,7 +1624,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { default: return false; } - return false; } @@ -1455,5 +1698,30 @@ isConditionalLoad (const MachineInstr* MI) const { default: return false; } +} + +DFAPacketizer *HexagonInstrInfo:: +CreateTargetScheduleState(const TargetMachine *TM, + const ScheduleDAG *DAG) const { + const InstrItineraryData *II = TM->getInstrItineraryData(); + return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II); +} + +bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI, + const MachineBasicBlock *MBB, + const MachineFunction &MF) const { + // Debug info is never a scheduling boundary. It's necessary to be explicit + // due to the special treatment of IT instructions below, otherwise a + // dbg_value followed by an IT will result in the IT instruction being + // considered a scheduling hazard, which is wrong. It should be the actual + // instruction preceding the dbg_value instruction(s), just like it is + // when debug info is not present. + if (MI->isDebugValue()) + return false; + + // Terminators and labels can't be scheduled around. + if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm()) + return true; + return false; } diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index d549c46..eb088c3 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -1,4 +1,4 @@ -//=- HexagonInstrInfo.h - Hexagon Instruction Information ---------*- C++ -*-=// +//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -14,6 +14,7 @@ #ifndef HexagonINSTRUCTIONINFO_H #define HexagonINSTRUCTIONINFO_H +#include "MCTargetDesc/HexagonBaseInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetFrameLowering.h" #include "HexagonRegisterInfo.h" @@ -135,6 +136,13 @@ public: isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, const BranchProbability &Probability) const; + virtual DFAPacketizer* + CreateTargetScheduleState(const TargetMachine *TM, + const ScheduleDAG *DAG) const; + + virtual bool isSchedulingBoundary(const MachineInstr *MI, + const MachineBasicBlock *MBB, + const MachineFunction &MF) const; bool isValidOffset(const int Opcode, const int Offset) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isMemOp(const MachineInstr *MI) const; @@ -155,6 +163,7 @@ public: bool isConditionalALU32 (const MachineInstr* MI) const; bool isConditionalLoad (const MachineInstr* MI) const; bool isDeallocRet(const MachineInstr *MI) const; + unsigned getInvertedPredicatedOpcode(const int Opc) const; private: int getMatchingCondBranchOpcode(int Opc, bool sense) const; diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index cc508b7..f3c6622 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -319,49 +319,49 @@ def ZXTH : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1), //===----------------------------------------------------------------------===// // Conditional add. -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_ri_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3), "if ($src1) $dst = add($src2, #$src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_ri_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3), "if (!$src1) $dst = add($src2, #$src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_ri_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3), "if ($src1.new) $dst = add($src2, #$src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_ri_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, s16Imm:$src3), "if (!$src1.new) $dst = add($src2, #$src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_rr_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = add($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = add($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = add($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = add($src2, $src3)", @@ -370,25 +370,25 @@ def ADD_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), // Conditional combine. -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def COMBINE_rr_cPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def COMBINE_rr_cNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def COMBINE_rr_cdnPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = combine($src2, $src3)", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = combine($src2, $src3)", @@ -396,61 +396,73 @@ def COMBINE_rr_cdnNotPt : ALU32_rr<(outs DoubleRegs:$dst), // Conditional logical operations. +let isPredicated = 1 in def XOR_rr_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = xor($src2, $src3)", []>; +let isPredicated = 1 in def XOR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = xor($src2, $src3)", []>; +let isPredicated = 1 in def XOR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = xor($src2, $src3)", []>; +let isPredicated = 1 in def XOR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = xor($src2, $src3)", []>; +let isPredicated = 1 in def AND_rr_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = and($src2, $src3)", []>; +let isPredicated = 1 in def AND_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = and($src2, $src3)", []>; +let isPredicated = 1 in def AND_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = and($src2, $src3)", []>; +let isPredicated = 1 in def AND_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = and($src2, $src3)", []>; +let isPredicated = 1 in def OR_rr_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = or($src2, $src3)", []>; +let isPredicated = 1 in def OR_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = or($src2, $src3)", []>; +let isPredicated = 1 in def OR_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = or($src2, $src3)", []>; +let isPredicated = 1 in def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = or($src2, $src3)", @@ -459,21 +471,25 @@ def OR_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), // Conditional subtract. +let isPredicated = 1 in def SUB_rr_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst = sub($src2, $src3)", []>; +let isPredicated = 1 in def SUB_rr_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst = sub($src2, $src3)", []>; +let isPredicated = 1 in def SUB_rr_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst = sub($src2, $src3)", []>; +let isPredicated = 1 in def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst = sub($src2, $src3)", @@ -482,47 +498,47 @@ def SUB_rr_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), // Conditional transfer. -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFR_cPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = $src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFR_cNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = $src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFRI_cPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2), "if ($src1) $dst = #$src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFRI_cNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2), "if (!$src1) $dst = #$src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFR_cdnPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = $src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFR_cdnNotPt : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = $src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFRI_cdnPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2), "if ($src1.new) $dst = #$src2", []>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def TFRI_cdnNotPt : ALU32_ri<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2), "if (!$src1.new) $dst = #$src2", @@ -679,10 +695,6 @@ def AND_pnotp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1, "$dst = and($src1, !$src2)", []>; -def NOT_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1), - "$dst = not($src1)", - [(set PredRegs:$dst, (not PredRegs:$src1))]>; - def ANY_pp : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1), "$dst = any8($src1)", []>; @@ -712,7 +724,7 @@ def MASK_p : SInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1), "$dst = mask($src1)", []>; -def NOT_Ps : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1), +def NOT_p : SInst<(outs PredRegs:$dst), (ins PredRegs:$src1), "$dst = not($src1)", [(set PredRegs:$dst, (not PredRegs:$src1))]>; @@ -743,22 +755,25 @@ let isBranch = 1, isTerminator=1, isBarrier = 1, isPredicable = 1 in { } // if (p0) jump -let isBranch = 1, isTerminator=1, Defs = [PC] in { - def JMP_Pred : JInst< (outs), +let isBranch = 1, isTerminator=1, Defs = [PC], + isPredicated = 1 in { + def JMP_c : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if ($src) jump $offset", [(brcond PredRegs:$src, bb:$offset)]>; } // if (!p0) jump -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { - def JMP_PredNot : JInst< (outs), +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { + def JMP_cNot : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if (!$src) jump $offset", []>; } -let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC] in { +let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { def BRCOND : JInst < (outs), (ins PredRegs:$pred, brtarget:$dst), "if ($pred) jump $dst", []>; @@ -766,32 +781,36 @@ let isTerminator = 1, isBranch = 1, neverHasSideEffects = 1, Defs = [PC] in { // Jump to address conditioned on new predicate. // if (p0) jump:t -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { - def JMP_PredPt : JInst< (outs), +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { + def JMP_cdnPt : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if ($src.new) jump:t $offset", []>; } // if (!p0) jump:t -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { - def JMP_PredNotPt : JInst< (outs), +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { + def JMP_cdnNotPt : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if (!$src.new) jump:t $offset", []>; } // Not taken. -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { - def JMP_PredPnt : JInst< (outs), +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { + def JMP_cdnPnt : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if ($src.new) jump:nt $offset", []>; } // Not taken. -let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { - def JMP_PredNotPnt : JInst< (outs), +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC], + isPredicated = 1 in { + def JMP_cdnNotPnt : JInst< (outs), (ins PredRegs:$src, brtarget:$offset), "if (!$src.new) jump:nt $offset", []>; @@ -1779,7 +1798,8 @@ def POST_STdri_cPt : STInstPI<(outs IntRegs:$dst), "$src3 = $dst">; // if (!Pv) memd(Rx++#s4:3)=Rtt -let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1 in +let AddedComplexity = 10, mayStore = 1, neverHasSideEffects = 1, + isPredicated = 1 in def POST_STdri_cNotPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, DoubleRegs:$src2, IntRegs:$src3, s4_3Imm:$offset), @@ -1859,14 +1879,14 @@ def STrib_indexed_cNotPt : STInst<(outs), // if ([!]Pv) memb(Rx++#s4:0)=Rt // if (Pv) memb(Rx++#s4:0)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_STbri_cPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), "if ($src1) memb($src3++#$offset) = $src2", [],"$src3 = $dst">; // if (!Pv) memb(Rx++#s4:0)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_STbri_cNotPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_0Imm:$offset), "if (!$src1) memb($src3++#$offset) = $src2", @@ -1944,14 +1964,14 @@ def STrih_indexed_cNotPt : STInst<(outs), // if ([!]Pv) memh(Rx++#s4:1)=Rt // if (Pv) memh(Rx++#s4:1)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_SThri_cPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), "if ($src1) memh($src3++#$offset) = $src2", [],"$src3 = $dst">; // if (!Pv) memh(Rx++#s4:1)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_SThri_cNotPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_1Imm:$offset), "if (!$src1) memh($src3++#$offset) = $src2", @@ -1979,11 +1999,6 @@ def STriw_indexed : STInst<(outs), "memw($src1+#$src2) = $src3", [(store IntRegs:$src3, (add IntRegs:$src1, s11_2ImmPred:$src2))]>; -def STriwt : STInst<(outs), - (ins MEMri:$addr, DoubleRegs:$src1), - "memw($addr) = $src1", - [(truncstorei32 DoubleRegs:$src1, ADDRriS11_2:$addr)]>; - let mayStore = 1, neverHasSideEffects = 1 in def STriw_GP : STInst<(outs), (ins globaladdress:$global, u16Imm:$offset, IntRegs:$src), @@ -2030,14 +2045,14 @@ def STriw_indexed_cNotPt : STInst<(outs), // if ([!]Pv) memw(Rx++#s4:2)=Rt // if (Pv) memw(Rx++#s4:2)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_STwri_cPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), "if ($src1) memw($src3++#$offset) = $src2", [],"$src3 = $dst">; // if (!Pv) memw(Rx++#s4:2)=Rt -let mayStore = 1, hasCtrlDep = 1 in +let mayStore = 1, hasCtrlDep = 1, isPredicated = 1 in def POST_STwri_cNotPt : STInstPI<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, s4_2Imm:$offset), "if (!$src1) memw($src3++#$offset) = $src2", @@ -2244,6 +2259,20 @@ def TFR_condset_rr : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src3))]>; let AddedComplexity = 100 in +def TFR_condset_ri : ALU32_rr<(outs IntRegs:$dst), + (ins PredRegs:$src1, IntRegs:$src2, s12Imm:$src3), + "Error; should not emit", + [(set IntRegs:$dst, + (select PredRegs:$src1, IntRegs:$src2, s12ImmPred:$src3))]>; + +let AddedComplexity = 100 in +def TFR_condset_ir : ALU32_rr<(outs IntRegs:$dst), + (ins PredRegs:$src1, s12Imm:$src2, IntRegs:$src3), + "Error; should not emit", + [(set IntRegs:$dst, + (select PredRegs:$src1, s12ImmPred:$src2, IntRegs:$src3))]>; + +let AddedComplexity = 100 in def TFR_condset_ii : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, s12Imm:$src2, s12Imm:$src3), "Error; should not emit", @@ -2436,7 +2465,7 @@ def : Pat <(and IntRegs:$src1, 255), // Add(p1, false) should never be produced, // if it does, it got to be mapped to NOOP. def : Pat <(add PredRegs:$src1, -1), - (NOT_pp PredRegs:$src1)>; + (NOT_p PredRegs:$src1)>; // Map from p0 = setlt(r0, r1) r2 = mux(p0, r3, r4) => // p0 = cmp.lt(r0, r1), r0 = mux(p0, r2, r1). @@ -2451,7 +2480,7 @@ def : Pat <(select (not PredRegs:$src1), s8ImmPred:$src2, s8ImmPred:$src3), // Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump. def : Pat <(brcond (not PredRegs:$src1), bb:$offset), - (JMP_PredNot PredRegs:$src1, bb:$offset)>; + (JMP_cNot PredRegs:$src1, bb:$offset)>; // Map from p2 = pnot(p2); p1 = and(p0, p2) => p1 = and(p0, !p2). def : Pat <(and PredRegs:$src1, (not PredRegs:$src2)), @@ -2650,39 +2679,39 @@ def : Pat <(i64 (sext_inreg DoubleRegs:$src1, i8)), (i64 (SXTW (SXTB (EXTRACT_SUBREG DoubleRegs:$src1, subreg_loreg))))>; // We want to prevent emiting pnot's as much as possible. -// Map brcond with an unsupported setcc to a JMP_PredNot. +// Map brcond with an unsupported setcc to a JMP_cNot. def : Pat <(brcond (i1 (setne IntRegs:$src1, IntRegs:$src2)), bb:$offset), - (JMP_PredNot (CMPEQrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; + (JMP_cNot (CMPEQrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; def : Pat <(brcond (i1 (setne IntRegs:$src1, s10ImmPred:$src2)), bb:$offset), - (JMP_PredNot (CMPEQri IntRegs:$src1, s10ImmPred:$src2), bb:$offset)>; + (JMP_cNot (CMPEQri IntRegs:$src1, s10ImmPred:$src2), bb:$offset)>; def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 -1))), bb:$offset), - (JMP_PredNot PredRegs:$src1, bb:$offset)>; + (JMP_cNot PredRegs:$src1, bb:$offset)>; def : Pat <(brcond (i1 (setne PredRegs:$src1, (i1 0))), bb:$offset), - (JMP_Pred PredRegs:$src1, bb:$offset)>; + (JMP_c PredRegs:$src1, bb:$offset)>; def : Pat <(brcond (i1 (setlt IntRegs:$src1, s8ImmPred:$src2)), bb:$offset), - (JMP_PredNot (CMPGEri IntRegs:$src1, s8ImmPred:$src2), bb:$offset)>; + (JMP_cNot (CMPGEri IntRegs:$src1, s8ImmPred:$src2), bb:$offset)>; def : Pat <(brcond (i1 (setlt IntRegs:$src1, IntRegs:$src2)), bb:$offset), - (JMP_Pred (CMPLTrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; + (JMP_c (CMPLTrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; def : Pat <(brcond (i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)), bb:$offset), - (JMP_PredNot (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1), + (JMP_cNot (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1), bb:$offset)>; def : Pat <(brcond (i1 (setule IntRegs:$src1, IntRegs:$src2)), bb:$offset), - (JMP_PredNot (CMPGTUrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; + (JMP_cNot (CMPGTUrr IntRegs:$src1, IntRegs:$src2), bb:$offset)>; def : Pat <(brcond (i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)), bb:$offset), - (JMP_PredNot (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2), + (JMP_cNot (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2), bb:$offset)>; -// Map from a 64-bit select to an emulated 64-bit mux. +// Map from a 64-bit select to an emulated 64-bit mux. // Hexagon does not support 64-bit MUXes; so emulate with combines. def : Pat <(select PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), (COMBINE_rr @@ -2697,7 +2726,7 @@ def : Pat <(select PredRegs:$src1, DoubleRegs:$src2, DoubleRegs:$src3), // From LegalizeDAG.cpp: (B1 ? B2 : B3) <=> (B1 & B2)|(!B1&B3). def : Pat <(select PredRegs:$src1, PredRegs:$src2, PredRegs:$src3), (OR_pp (AND_pp PredRegs:$src1, PredRegs:$src2), - (AND_pp (NOT_pp PredRegs:$src1), PredRegs:$src3))>; + (AND_pp (NOT_p PredRegs:$src1), PredRegs:$src3))>; // Map Pd = load(addr) -> Rs = load(addr); Pd = Rs. def : Pat<(i1 (load ADDRriS11_2:$addr)), @@ -2711,7 +2740,7 @@ def : Pat<(i32 (trunc DoubleRegs:$src)), def : Pat<(i1 (trunc DoubleRegs:$src)), (i1 (TFR_PdRs (i32(EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg))))>; -// Map memw(Rs) = Rdd -> memw(Rs) = Rt. +// Map memb(Rs) = Rdd -> memb(Rs) = Rt. def : Pat<(truncstorei8 DoubleRegs:$src, ADDRriS11_0:$addr), (STrib ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg)))>; @@ -2721,6 +2750,11 @@ def : Pat<(truncstorei16 DoubleRegs:$src, ADDRriS11_0:$addr), (STrih ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src, subreg_loreg)))>; +// Map memw(Rs) = Rdd -> memw(Rs) = Rt. +def : Pat<(truncstorei32 DoubleRegs:$src, ADDRriS11_0:$addr), + (STriw ADDRriS11_0:$addr, (i32 (EXTRACT_SUBREG DoubleRegs:$src, + subreg_loreg)))>; + // Map from i1 = constant<-1>; memw(addr) = i1 -> r0 = 1; memw(addr) = r0. def : Pat<(store (i1 -1), ADDRriS11_2:$addr), (STrib ADDRriS11_2:$addr, (TFRI 1))>; @@ -2749,26 +2783,26 @@ def : Pat<(i64 (anyext IntRegs:$src1)), // Map cmple -> cmpgt. // rs <= rt -> !(rs > rt). def : Pat<(i1 (setle IntRegs:$src1, s10ImmPred:$src2)), - (i1 (NOT_Ps (CMPGTri IntRegs:$src1, s10ImmPred:$src2)))>; + (i1 (NOT_p (CMPGTri IntRegs:$src1, s10ImmPred:$src2)))>; // rs <= rt -> !(rs > rt). def : Pat<(i1 (setle IntRegs:$src1, IntRegs:$src2)), - (i1 (NOT_Ps (CMPGTrr IntRegs:$src1, IntRegs:$src2)))>; + (i1 (NOT_p (CMPGTrr IntRegs:$src1, IntRegs:$src2)))>; // Rss <= Rtt -> !(Rss > Rtt). def : Pat<(i1 (setle DoubleRegs:$src1, DoubleRegs:$src2)), - (i1 (NOT_Ps (CMPGT64rr DoubleRegs:$src1, DoubleRegs:$src2)))>; + (i1 (NOT_p (CMPGT64rr DoubleRegs:$src1, DoubleRegs:$src2)))>; // Map cmpne -> cmpeq. // Hexagon_TODO: We should improve on this. // rs != rt -> !(rs == rt). def : Pat <(i1 (setne IntRegs:$src1, s10ImmPred:$src2)), - (i1 (NOT_Ps(i1 (CMPEQri IntRegs:$src1, s10ImmPred:$src2))))>; + (i1 (NOT_p(i1 (CMPEQri IntRegs:$src1, s10ImmPred:$src2))))>; // Map cmpne(Rs) -> !cmpeqe(Rs). // rs != rt -> !(rs == rt). def : Pat <(i1 (setne IntRegs:$src1, IntRegs:$src2)), - (i1 (NOT_Ps(i1 (CMPEQrr IntRegs:$src1, IntRegs:$src2))))>; + (i1 (NOT_p(i1 (CMPEQrr IntRegs:$src1, IntRegs:$src2))))>; // Convert setne back to xor for hexagon since we compute w/ pred registers. def : Pat <(i1 (setne PredRegs:$src1, PredRegs:$src2)), @@ -2777,12 +2811,12 @@ def : Pat <(i1 (setne PredRegs:$src1, PredRegs:$src2)), // Map cmpne(Rss) -> !cmpew(Rss). // rs != rt -> !(rs == rt). def : Pat <(i1 (setne DoubleRegs:$src1, DoubleRegs:$src2)), - (i1 (NOT_Ps(i1 (CMPEHexagon4rr DoubleRegs:$src1, DoubleRegs:$src2))))>; + (i1 (NOT_p(i1 (CMPEHexagon4rr DoubleRegs:$src1, DoubleRegs:$src2))))>; // Map cmpge(Rs, Rt) -> !(cmpgt(Rs, Rt). // rs >= rt -> !(rt > rs). def : Pat <(i1 (setge IntRegs:$src1, IntRegs:$src2)), - (i1 (NOT_Ps(i1 (CMPGTrr IntRegs:$src2, IntRegs:$src1))))>; + (i1 (NOT_p(i1 (CMPGTrr IntRegs:$src2, IntRegs:$src1))))>; def : Pat <(i1 (setge IntRegs:$src1, s8ImmPred:$src2)), (i1 (CMPGEri IntRegs:$src1, s8ImmPred:$src2))>; @@ -2790,12 +2824,12 @@ def : Pat <(i1 (setge IntRegs:$src1, s8ImmPred:$src2)), // Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss). // rss >= rtt -> !(rtt > rss). def : Pat <(i1 (setge DoubleRegs:$src1, DoubleRegs:$src2)), - (i1 (NOT_Ps(i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))))>; + (i1 (NOT_p(i1 (CMPGT64rr DoubleRegs:$src2, DoubleRegs:$src1))))>; // Map cmplt(Rs, Imm) -> !cmpge(Rs, Imm). // rs < rt -> !(rs >= rt). def : Pat <(i1 (setlt IntRegs:$src1, s8ImmPred:$src2)), - (i1 (NOT_Ps (CMPGEri IntRegs:$src1, s8ImmPred:$src2)))>; + (i1 (NOT_p (CMPGEri IntRegs:$src1, s8ImmPred:$src2)))>; // Map cmplt(Rs, Rt) -> cmplt(Rs, Rt). // rs < rt -> rs < rt. Let assembler map it. @@ -2820,22 +2854,22 @@ def : Pat <(i1 (setult DoubleRegs:$src1, DoubleRegs:$src2)), // Map from Rs >= Rt -> !(Rt > Rs). // rs >= rt -> !(rt > rs). def : Pat <(i1 (setuge IntRegs:$src1, IntRegs:$src2)), - (i1 (NOT_Ps (CMPGTUrr IntRegs:$src2, IntRegs:$src1)))>; + (i1 (NOT_p (CMPGTUrr IntRegs:$src2, IntRegs:$src1)))>; // Map from Rs >= Rt -> !(Rt > Rs). // rs >= rt -> !(rt > rs). def : Pat <(i1 (setuge DoubleRegs:$src1, DoubleRegs:$src2)), - (i1 (NOT_Ps (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1)))>; + (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src2, DoubleRegs:$src1)))>; // Map from cmpleu(Rs, Rs) -> !cmpgtu(Rs, Rs). // Map from (Rs <= Rt) -> !(Rs > Rt). def : Pat <(i1 (setule IntRegs:$src1, IntRegs:$src2)), - (i1 (NOT_Ps (CMPGTUrr IntRegs:$src1, IntRegs:$src2)))>; + (i1 (NOT_p (CMPGTUrr IntRegs:$src1, IntRegs:$src2)))>; // Map from cmpleu(Rss, Rtt) -> !cmpgtu(Rss, Rtt-1). // Map from (Rs <= Rt) -> !(Rs > Rt). def : Pat <(i1 (setule DoubleRegs:$src1, DoubleRegs:$src2)), - (i1 (NOT_Ps (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2)))>; + (i1 (NOT_p (CMPGTU64rr DoubleRegs:$src1, DoubleRegs:$src2)))>; // Sign extends. // i1 -> i32 diff --git a/lib/Target/Hexagon/HexagonInstrInfoV4.td b/lib/Target/Hexagon/HexagonInstrInfoV4.td index 24218d0..9e60cf2 100644 --- a/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -77,48 +77,56 @@ // Shift halfword. +let isPredicated = 1 in def ASLH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = aslh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASLH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = aslh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASLH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = aslh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASLH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = aslh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASRH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = asrh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASRH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = asrh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASRH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = asrh($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = asrh($src2)", @@ -127,24 +135,28 @@ def ASRH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), // Sign extend. +let isPredicated = 1 in def SXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = sxtb($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = sxtb($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = sxtb($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = sxtb($src2)", @@ -152,24 +164,28 @@ def SXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), Requires<[HasV4T]>; +let isPredicated = 1 in def SXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = sxth($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = sxth($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = sxth($src2)", []>, Requires<[HasV4T]>; +let isPredicated = 1 in def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = sxth($src2)", @@ -178,56 +194,56 @@ def SXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), // Zero exten. -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTB_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = zxtb($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTB_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = zxtb($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTB_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = zxtb($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTB_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = zxtb($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTH_cPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1) $dst = zxth($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTH_cNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1) $dst = zxth($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTH_cdnPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if ($src1.new) $dst = zxth($src2)", []>, Requires<[HasV4T]>; -let neverHasSideEffects = 1 in +let neverHasSideEffects = 1, isPredicated = 1 in def ZXTH_cdnNotPt_V4 : ALU32_rr<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2), "if (!$src1.new) $dst = zxth($src2)", @@ -276,7 +292,7 @@ def LDrid_indexed_shl_V4 : LDInst<(outs DoubleRegs:$dst), //// Load doubleword conditionally. // if ([!]Pv[.new]) Rd=memd(Rs+Rt<<#u2) // if (Pv) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memd($src2+$src3<<#0)", @@ -284,7 +300,7 @@ def LDrid_indexed_cPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memd($src2+$src3<<#0)", @@ -292,7 +308,7 @@ def LDrid_indexed_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memd($src2+$src3<<#0)", @@ -300,7 +316,7 @@ def LDrid_indexed_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memd($src2+$src3<<#0)", @@ -308,7 +324,7 @@ def LDrid_indexed_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -317,7 +333,7 @@ def LDrid_indexed_shl_cPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -326,7 +342,7 @@ def LDrid_indexed_shl_cdnPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -335,7 +351,7 @@ def LDrid_indexed_shl_cNotPt_V4 : LDInst<(outs DoubleRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memd(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrid_indexed_shl_cdnNotPt_V4 : LDInst<(outs DoubleRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -405,7 +421,7 @@ def LDriub_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), //// Load byte conditionally. // if ([!]Pv[.new]) Rd=memb(Rs+Rt<<#u2) // if (Pv) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memb($src2+$src3<<#0)", @@ -413,7 +429,7 @@ def LDrib_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memb($src2+$src3<<#0)", @@ -421,7 +437,7 @@ def LDrib_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memb($src2+$src3<<#0)", @@ -429,7 +445,7 @@ def LDrib_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memb($src2+$src3<<#0)", @@ -437,7 +453,7 @@ def LDrib_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -446,7 +462,7 @@ def LDrib_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -455,7 +471,7 @@ def LDrib_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -464,7 +480,7 @@ def LDrib_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memb(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -475,7 +491,7 @@ def LDrib_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), //// Load unsigned byte conditionally. // if ([!]Pv[.new]) Rd=memub(Rs+Rt<<#u2) // if (Pv) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memub($src2+$src3<<#0)", @@ -483,7 +499,7 @@ def LDriub_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memub($src2+$src3<<#0)", @@ -491,7 +507,7 @@ def LDriub_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memub($src2+$src3<<#0)", @@ -499,7 +515,7 @@ def LDriub_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memub($src2+$src3<<#0)", @@ -507,7 +523,7 @@ def LDriub_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -516,7 +532,7 @@ def LDriub_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -525,7 +541,7 @@ def LDriub_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -534,7 +550,7 @@ def LDriub_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memub(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriub_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -606,7 +622,7 @@ def LDriuh_ae_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), //// Load halfword conditionally. // if ([!]Pv[.new]) Rd=memh(Rs+Rt<<#u2) // if (Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memh($src2+$src3<<#0)", @@ -614,7 +630,7 @@ def LDrih_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memh($src2+$src3<<#0)", @@ -622,7 +638,7 @@ def LDrih_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memh($src2+$src3<<#0)", @@ -630,7 +646,7 @@ def LDrih_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memh($src2+$src3<<#0)", @@ -638,7 +654,7 @@ def LDrih_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -647,7 +663,7 @@ def LDrih_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -656,7 +672,7 @@ def LDrih_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -665,7 +681,7 @@ def LDrih_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -676,7 +692,7 @@ def LDrih_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), //// Load unsigned halfword conditionally. // if ([!]Pv[.new]) Rd=memuh(Rs+Rt<<#u2) // if (Pv) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memuh($src2+$src3<<#0)", @@ -684,7 +700,7 @@ def LDriuh_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memuh($src2+$src3<<#0)", @@ -692,7 +708,7 @@ def LDriuh_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memuh($src2+$src3<<#0)", @@ -700,7 +716,7 @@ def LDriuh_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memuh($src2+$src3<<#0)", @@ -708,7 +724,7 @@ def LDriuh_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -717,7 +733,7 @@ def LDriuh_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -726,7 +742,7 @@ def LDriuh_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -735,7 +751,7 @@ def LDriuh_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memuh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriuh_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -770,7 +786,7 @@ def LDriw_indexed_shl_V4 : LDInst<(outs IntRegs:$dst), //// Load word conditionally. // if ([!]Pv[.new]) Rd=memw(Rs+Rt<<#u2) // if (Pv) Rd=memw(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1) $dst=memw($src2+$src3<<#0)", @@ -778,7 +794,7 @@ def LDriw_indexed_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if ($src1.new) $dst=memw($src2+$src3<<#0)", @@ -786,7 +802,7 @@ def LDriw_indexed_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1) $dst=memw($src2+$src3<<#0)", @@ -794,7 +810,7 @@ def LDriw_indexed_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 15 in +let mayLoad = 1, AddedComplexity = 15, isPredicated = 1 in def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3), "if (!$src1.new) $dst=memw($src2+$src3<<#0)", @@ -802,7 +818,7 @@ def LDriw_indexed_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -811,7 +827,7 @@ def LDriw_indexed_shl_cPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -820,7 +836,7 @@ def LDriw_indexed_shl_cdnPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -829,7 +845,7 @@ def LDriw_indexed_shl_cNotPt_V4 : LDInst<(outs IntRegs:$dst), Requires<[HasV4T]>; // if (!Pv.new) Rd=memh(Rs+Rt<<#u2) -let mayLoad = 1, AddedComplexity = 45 in +let mayLoad = 1, AddedComplexity = 45, isPredicated = 1 in def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), (ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$offset), @@ -843,7 +859,7 @@ def LDriw_indexed_shl_cdnNotPt_V4 : LDInst<(outs IntRegs:$dst), // Post-inc Load, Predicated, Dot new -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3), "if ($src1.new) $dst1 = memd($src2++#$src3)", @@ -851,7 +867,7 @@ def POST_LDrid_cdnPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_3Imm:$src3), "if (!$src1.new) $dst1 = memd($src2++#$src3)", @@ -859,7 +875,7 @@ def POST_LDrid_cdnNotPt_V4 : LDInstPI<(outs DoubleRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), "if ($src1.new) $dst1 = memb($src2++#$src3)", @@ -867,7 +883,7 @@ def POST_LDrib_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), "if (!$src1.new) $dst1 = memb($src2++#$src3)", @@ -875,7 +891,7 @@ def POST_LDrib_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), "if ($src1.new) $dst1 = memh($src2++#$src3)", @@ -883,7 +899,7 @@ def POST_LDrih_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), "if (!$src1.new) $dst1 = memh($src2++#$src3)", @@ -891,7 +907,7 @@ def POST_LDrih_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), "if ($src1.new) $dst1 = memub($src2++#$src3)", @@ -899,7 +915,7 @@ def POST_LDriub_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_0Imm:$src3), "if (!$src1.new) $dst1 = memub($src2++#$src3)", @@ -907,7 +923,7 @@ def POST_LDriub_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), "if ($src1.new) $dst1 = memuh($src2++#$src3)", @@ -915,7 +931,7 @@ def POST_LDriuh_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_1Imm:$src3), "if (!$src1.new) $dst1 = memuh($src2++#$src3)", @@ -923,7 +939,7 @@ def POST_LDriuh_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3), "if ($src1.new) $dst1 = memw($src2++#$src3)", @@ -931,7 +947,7 @@ def POST_LDriw_cdnPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), "$src2 = $dst2">, Requires<[HasV4T]>; -let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1 in +let mayLoad = 1, hasCtrlDep = 1, neverHasSideEffects = 1, isPredicated = 1 in def POST_LDriw_cdnNotPt_V4 : LDInstPI<(outs IntRegs:$dst1, IntRegs:$dst2), (ins PredRegs:$src1, IntRegs:$src2, s4_2Imm:$src3), "if (!$src1.new) $dst1 = memw($src2++#$src3)", @@ -2215,6 +2231,181 @@ def POST_STwri_cdnNotPt_nv_V4 : NVInstPI_V4<(outs IntRegs:$dst), // NV/ST - //===----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// NV/J + +//===----------------------------------------------------------------------===// + +multiclass NVJ_type_basic_reg<string NotStr, string OpcStr, string TakenStr> { + def _ie_nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, $src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; + + def _nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, $src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; +} + +multiclass NVJ_type_basic_2ndDotNew<string NotStr, string OpcStr, string TakenStr> { + def _ie_nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1, $src2.new)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; + + def _nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1, $src2.new)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; +} + +multiclass NVJ_type_basic_imm<string NotStr, string OpcStr, string TakenStr> { + def _ie_nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; + + def _nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; +} + +multiclass NVJ_type_basic_neg<string NotStr, string OpcStr, string TakenStr> { + def _ie_nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; + + def _nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, nOneImm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; +} + +multiclass NVJ_type_basic_tstbit<string NotStr, string OpcStr, string TakenStr> { + def _ie_nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; + + def _nv_V4 : NVInst_V4<(outs), + (ins IntRegs:$src1, u1Imm:$src2, brtarget:$offset), + !strconcat("if (", !strconcat(NotStr, !strconcat(OpcStr, + !strconcat("($src1.new, #$src2)) jump:", + !strconcat(TakenStr, " $offset"))))), + []>, + Requires<[HasV4T]>; +} + +// Multiclass for regular dot new of Ist operand register. +multiclass NVJ_type_br_pred_reg<string NotStr, string OpcStr> { + defm Pt : NVJ_type_basic_reg<NotStr, OpcStr, "t">; + defm Pnt : NVJ_type_basic_reg<NotStr, OpcStr, "nt">; +} + +// Multiclass for dot new of 2nd operand register. +multiclass NVJ_type_br_pred_2ndDotNew<string NotStr, string OpcStr> { + defm Pt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "t">; + defm Pnt : NVJ_type_basic_2ndDotNew<NotStr, OpcStr, "nt">; +} + +// Multiclass for 2nd operand immediate, including -1. +multiclass NVJ_type_br_pred_imm<string NotStr, string OpcStr> { + defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">; + defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">; + defm Ptneg : NVJ_type_basic_neg<NotStr, OpcStr, "t">; + defm Pntneg : NVJ_type_basic_neg<NotStr, OpcStr, "nt">; +} + +// Multiclass for 2nd operand immediate, excluding -1. +multiclass NVJ_type_br_pred_imm_only<string NotStr, string OpcStr> { + defm Pt : NVJ_type_basic_imm<NotStr, OpcStr, "t">; + defm Pnt : NVJ_type_basic_imm<NotStr, OpcStr, "nt">; +} + +// Multiclass for tstbit, where 2nd operand is always #0. +multiclass NVJ_type_br_pred_tstbit<string NotStr, string OpcStr> { + defm Pt : NVJ_type_basic_tstbit<NotStr, OpcStr, "t">; + defm Pnt : NVJ_type_basic_tstbit<NotStr, OpcStr, "nt">; +} + +// Multiclass for GT. +multiclass NVJ_type_rr_ri<string OpcStr> { + defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; + defm rr : NVJ_type_br_pred_reg<"", OpcStr>; + defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>; + defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>; + defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>; + defm ri : NVJ_type_br_pred_imm<"", OpcStr>; +} + +// Multiclass for EQ. +multiclass NVJ_type_rr_ri_no_2ndDotNew<string OpcStr> { + defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; + defm rr : NVJ_type_br_pred_reg<"", OpcStr>; + defm riNot : NVJ_type_br_pred_imm<"!", OpcStr>; + defm ri : NVJ_type_br_pred_imm<"", OpcStr>; +} + +// Multiclass for GTU. +multiclass NVJ_type_rr_ri_no_nOne<string OpcStr> { + defm rrNot : NVJ_type_br_pred_reg<"!", OpcStr>; + defm rr : NVJ_type_br_pred_reg<"", OpcStr>; + defm rrdnNot : NVJ_type_br_pred_2ndDotNew<"!", OpcStr>; + defm rrdn : NVJ_type_br_pred_2ndDotNew<"", OpcStr>; + defm riNot : NVJ_type_br_pred_imm_only<"!", OpcStr>; + defm ri : NVJ_type_br_pred_imm_only<"", OpcStr>; +} + +// Multiclass for tstbit. +multiclass NVJ_type_r0<string OpcStr> { + defm r0Not : NVJ_type_br_pred_tstbit<"!", OpcStr>; + defm r0 : NVJ_type_br_pred_tstbit<"", OpcStr>; + } + +// Base Multiclass for New Value Jump. +multiclass NVJ_type { + defm GT : NVJ_type_rr_ri<"cmp.gt">; + defm EQ : NVJ_type_rr_ri_no_2ndDotNew<"cmp.eq">; + defm GTU : NVJ_type_rr_ri_no_nOne<"cmp.gtu">; + defm TSTBIT : NVJ_type_r0<"tstbit">; +} + +let isBranch = 1, isTerminator=1, neverHasSideEffects = 1, Defs = [PC] in { + defm JMP_ : NVJ_type; +} + +//===----------------------------------------------------------------------===// +// NV/J - +//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // XTYPE/ALU + diff --git a/lib/Target/Hexagon/HexagonIntrinsics.td b/lib/Target/Hexagon/HexagonIntrinsics.td index 1328eba..b15e293 100644 --- a/lib/Target/Hexagon/HexagonIntrinsics.td +++ b/lib/Target/Hexagon/HexagonIntrinsics.td @@ -1,4 +1,4 @@ -//===- HexagonIntrinsics.td - Instruction intrinsics -------*- tablegen -*-===// +//===-- HexagonIntrinsics.td - Instruction intrinsics ------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonOptimizeSZExtends.cpp b/lib/Target/Hexagon/HexagonOptimizeSZExtends.cpp deleted file mode 100644 index 1229aca..0000000 --- a/lib/Target/Hexagon/HexagonOptimizeSZExtends.cpp +++ /dev/null @@ -1,129 +0,0 @@ -//===-- HexagonOptimizeSZExtends.cpp - Identify and remove sign and -------===// -//===-- zero extends. -------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Constants.h" -#include "llvm/PassSupport.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Support/Debug.h" -#include "llvm/CodeGen/MachineFunctionAnalysis.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetInstrInfo.h" -#include <algorithm> -#include "Hexagon.h" -#include "HexagonTargetMachine.h" - -using namespace llvm; - -namespace { - struct HexagonOptimizeSZExtends : public MachineFunctionPass { - - public: - static char ID; - HexagonOptimizeSZExtends() : MachineFunctionPass(ID) {} - - bool runOnMachineFunction(MachineFunction &MF); - - const char *getPassName() const { - return "Hexagon remove redundant zero and size extends"; - } - - void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired<MachineFunctionAnalysis>(); - AU.addPreserved<MachineFunctionAnalysis>(); - MachineFunctionPass::getAnalysisUsage(AU); - } - - private: - }; -} - -char HexagonOptimizeSZExtends::ID = 0; - -// This is a brain dead pass to get rid of redundant sign extends for the -// following case: -// -// Transform the following pattern -// %vreg170<def> = SXTW %vreg166 -// ... -// %vreg176<def> = COPY %vreg170:subreg_loreg -// -// Into -// %vreg176<def> = COPY vreg166 - -bool HexagonOptimizeSZExtends::runOnMachineFunction(MachineFunction &MF) { - DenseMap<unsigned, unsigned> SExtMap; - - // Loop over all of the basic blocks - for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); - MBBb != MBBe; ++MBBb) { - MachineBasicBlock* MBB = MBBb; - SExtMap.clear(); - - // Traverse the basic block. - for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); - ++MII) { - MachineInstr *MI = MII; - // Look for sign extends: - // %vreg170<def> = SXTW %vreg166 - if (MI->getOpcode() == Hexagon::SXTW) { - assert (MI->getNumOperands() == 2); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src = MI->getOperand(1); - unsigned DstReg = Dst.getReg(); - unsigned SrcReg = Src.getReg(); - // Just handle virtual registers. - if (TargetRegisterInfo::isVirtualRegister(DstReg) && - TargetRegisterInfo::isVirtualRegister(SrcReg)) { - // Map the following: - // %vreg170<def> = SXTW %vreg166 - // SExtMap[170] = vreg166 - SExtMap[DstReg] = SrcReg; - } - } - // Look for copy: - // %vreg176<def> = COPY %vreg170:subreg_loreg - if (MI->isCopy()) { - assert (MI->getNumOperands() == 2); - MachineOperand &Dst = MI->getOperand(0); - MachineOperand &Src = MI->getOperand(1); - - // Make sure we are copying the lower 32 bits. - if (Src.getSubReg() != Hexagon::subreg_loreg) - continue; - - unsigned DstReg = Dst.getReg(); - unsigned SrcReg = Src.getReg(); - if (TargetRegisterInfo::isVirtualRegister(DstReg) && - TargetRegisterInfo::isVirtualRegister(SrcReg)) { - // Try to find in the map. - if (unsigned SextSrc = SExtMap.lookup(SrcReg)) { - // Change the 1st operand. - MI->RemoveOperand(1); - MI->addOperand(MachineOperand::CreateReg(SextSrc, false)); - } - } - } - } - } - return true; -} - -FunctionPass *llvm::createHexagonOptimizeSZExtends() { - return new HexagonOptimizeSZExtends(); -} diff --git a/lib/Target/Hexagon/HexagonPeephole.cpp b/lib/Target/Hexagon/HexagonPeephole.cpp new file mode 100644 index 0000000..06c732f --- /dev/null +++ b/lib/Target/Hexagon/HexagonPeephole.cpp @@ -0,0 +1,289 @@ +//===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +// This peephole pass optimizes in the following cases. +// 1. Optimizes redundant sign extends for the following case +// Transform the following pattern +// %vreg170<def> = SXTW %vreg166 +// ... +// %vreg176<def> = COPY %vreg170:subreg_loreg +// +// Into +// %vreg176<def> = COPY vreg166 +// +// 2. Optimizes redundant negation of predicates. +// %vreg15<def> = CMPGTrr %vreg6, %vreg2 +// ... +// %vreg16<def> = NOT_p %vreg15<kill> +// ... +// JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead> +// +// Into +// %vreg15<def> = CMPGTrr %vreg6, %vreg2; +// ... +// JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>; +// +// Note: The peephole pass makes the instrucstions like +// %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill> +// redundant and relies on some form of dead removal instrucions, like +// DCE or DIE to actually eliminate them. + + +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "hexagon-peephole" +#include "llvm/Constants.h" +#include "llvm/PassSupport.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/TargetRegisterInfo.h" +#include "llvm/Target/TargetInstrInfo.h" +#include <algorithm> +#include "Hexagon.h" +#include "HexagonTargetMachine.h" + +#include "llvm/Support/CommandLine.h" + +using namespace llvm; + +static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Peephole Optimization")); + +static cl::opt<int> +DbgPNPCount("pnp-count", cl::init(-1), cl::Hidden, + cl::desc("Maximum number of P=NOT(P) to be optimized")); + +static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Optimization of PNotP")); + +static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext", + cl::Hidden, cl::ZeroOrMore, cl::init(false), + cl::desc("Disable Optimization of Sign/Zero Extends")); + +namespace { + struct HexagonPeephole : public MachineFunctionPass { + const HexagonInstrInfo *QII; + const HexagonRegisterInfo *QRI; + const MachineRegisterInfo *MRI; + + public: + static char ID; + HexagonPeephole() : MachineFunctionPass(ID) { } + + bool runOnMachineFunction(MachineFunction &MF); + + const char *getPassName() const { + return "Hexagon optimize redundant zero and size extends"; + } + + void getAnalysisUsage(AnalysisUsage &AU) const { + MachineFunctionPass::getAnalysisUsage(AU); + } + + private: + void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src); + }; +} + +char HexagonPeephole::ID = 0; + +bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) { + + QII = static_cast<const HexagonInstrInfo *>(MF.getTarget(). + getInstrInfo()); + QRI = static_cast<const HexagonRegisterInfo *>(MF.getTarget(). + getRegisterInfo()); + MRI = &MF.getRegInfo(); + + DenseMap<unsigned, unsigned> PeepholeMap; + + if (DisableHexagonPeephole) return false; + + // Loop over all of the basic blocks. + for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end(); + MBBb != MBBe; ++MBBb) { + MachineBasicBlock* MBB = MBBb; + PeepholeMap.clear(); + + // Traverse the basic block. + for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); + ++MII) { + MachineInstr *MI = MII; + // Look for sign extends: + // %vreg170<def> = SXTW %vreg166 + if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) { + assert (MI->getNumOperands() == 2); + MachineOperand &Dst = MI->getOperand(0); + MachineOperand &Src = MI->getOperand(1); + unsigned DstReg = Dst.getReg(); + unsigned SrcReg = Src.getReg(); + // Just handle virtual registers. + if (TargetRegisterInfo::isVirtualRegister(DstReg) && + TargetRegisterInfo::isVirtualRegister(SrcReg)) { + // Map the following: + // %vreg170<def> = SXTW %vreg166 + // PeepholeMap[170] = vreg166 + PeepholeMap[DstReg] = SrcReg; + } + } + + // Look for P=NOT(P). + if (!DisablePNotP && + (MI->getOpcode() == Hexagon::NOT_p)) { + assert (MI->getNumOperands() == 2); + MachineOperand &Dst = MI->getOperand(0); + MachineOperand &Src = MI->getOperand(1); + unsigned DstReg = Dst.getReg(); + unsigned SrcReg = Src.getReg(); + // Just handle virtual registers. + if (TargetRegisterInfo::isVirtualRegister(DstReg) && + TargetRegisterInfo::isVirtualRegister(SrcReg)) { + // Map the following: + // %vreg170<def> = NOT_xx %vreg166 + // PeepholeMap[170] = vreg166 + PeepholeMap[DstReg] = SrcReg; + } + } + + // Look for copy: + // %vreg176<def> = COPY %vreg170:subreg_loreg + if (!DisableOptSZExt && MI->isCopy()) { + assert (MI->getNumOperands() == 2); + MachineOperand &Dst = MI->getOperand(0); + MachineOperand &Src = MI->getOperand(1); + + // Make sure we are copying the lower 32 bits. + if (Src.getSubReg() != Hexagon::subreg_loreg) + continue; + + unsigned DstReg = Dst.getReg(); + unsigned SrcReg = Src.getReg(); + if (TargetRegisterInfo::isVirtualRegister(DstReg) && + TargetRegisterInfo::isVirtualRegister(SrcReg)) { + // Try to find in the map. + if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) { + // Change the 1st operand. + MI->RemoveOperand(1); + MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); + } + } + } + + // Look for Predicated instructions. + if (!DisablePNotP) { + bool Done = false; + if (QII->isPredicated(MI)) { + MachineOperand &Op0 = MI->getOperand(0); + unsigned Reg0 = Op0.getReg(); + const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0); + if (RC0->getID() == Hexagon::PredRegsRegClassID) { + // Handle instructions that have a prediate register in op0 + // (most cases of predicable instructions). + if (TargetRegisterInfo::isVirtualRegister(Reg0)) { + // Try to find in the map. + if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) { + // Change the 1st operand and, flip the opcode. + MI->getOperand(0).setReg(PeepholeSrc); + int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode()); + MI->setDesc(QII->get(NewOp)); + Done = true; + } + } + } + } + + if (!Done) { + // Handle special instructions. + unsigned Op = MI->getOpcode(); + unsigned NewOp = 0; + unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices. + + switch (Op) { + case Hexagon::TFR_condset_rr: + case Hexagon::TFR_condset_ii: + case Hexagon::MUX_ii: + case Hexagon::MUX_rr: + NewOp = Op; + break; + case Hexagon::TFR_condset_ri: + NewOp = Hexagon::TFR_condset_ir; + break; + case Hexagon::TFR_condset_ir: + NewOp = Hexagon::TFR_condset_ri; + break; + case Hexagon::MUX_ri: + NewOp = Hexagon::MUX_ir; + break; + case Hexagon::MUX_ir: + NewOp = Hexagon::MUX_ri; + break; + } + if (NewOp) { + unsigned PSrc = MI->getOperand(PR).getReg(); + if (unsigned POrig = PeepholeMap.lookup(PSrc)) { + MI->getOperand(PR).setReg(POrig); + MI->setDesc(QII->get(NewOp)); + // Swap operands S1 and S2. + MachineOperand Op1 = MI->getOperand(S1); + MachineOperand Op2 = MI->getOperand(S2); + ChangeOpInto(MI->getOperand(S1), Op2); + ChangeOpInto(MI->getOperand(S2), Op1); + } + } // if (NewOp) + } // if (!Done) + + } // if (!DisablePNotP) + + } // Instruction + } // Basic Block + return true; +} + +void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) { + assert (&Dst != &Src && "Cannot duplicate into itself"); + switch (Dst.getType()) { + case MachineOperand::MO_Register: + if (Src.isReg()) { + Dst.setReg(Src.getReg()); + } else if (Src.isImm()) { + Dst.ChangeToImmediate(Src.getImm()); + } else { + llvm_unreachable("Unexpected src operand type"); + } + break; + + case MachineOperand::MO_Immediate: + if (Src.isImm()) { + Dst.setImm(Src.getImm()); + } else if (Src.isReg()) { + Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(), + Src.isKill(), Src.isDead(), Src.isUndef(), + Src.isDebug()); + } else { + llvm_unreachable("Unexpected src operand type"); + } + break; + + default: + llvm_unreachable("Unexpected dst operand type"); + break; + } +} + +FunctionPass *llvm::createHexagonPeephole() { + return new HexagonPeephole(); +} diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/lib/Target/Hexagon/HexagonRegisterInfo.cpp index 521e0c1..c481270 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.cpp +++ b/lib/Target/Hexagon/HexagonRegisterInfo.cpp @@ -1,4 +1,4 @@ -//==- HexagonRegisterInfo.cpp - Hexagon Register Information -----*- C++ -*-==// +//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===// // // The LLVM Compiler Infrastructure // @@ -17,24 +17,23 @@ #include "HexagonSubtarget.h" #include "HexagonTargetMachine.h" #include "HexagonMachineFunctionInfo.h" +#include "llvm/Function.h" +#include "llvm/Type.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Type.h" -#include "llvm/ADT/BitVector.h" -#include "llvm/ADT/STLExtras.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" -#include <iostream> +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/ErrorHandling.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/Function.h" using namespace llvm; @@ -45,31 +44,29 @@ HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st, TII(tii) { } -const unsigned* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction +const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - static const unsigned CalleeSavedRegsV2[] = { - Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 + static const uint16_t CalleeSavedRegsV2[] = { + Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 }; - static const unsigned CalleeSavedRegsV3[] = { + static const uint16_t CalleeSavedRegsV3[] = { Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19, Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0 }; switch(Subtarget.getHexagonArchVersion()) { + case HexagonSubtarget::V1: + break; case HexagonSubtarget::V2: return CalleeSavedRegsV2; - break; case HexagonSubtarget::V3: case HexagonSubtarget::V4: return CalleeSavedRegsV3; - break; - default: - const char *ErrorString = - "Callee saved registers requested for unknown archtecture version"; - llvm_unreachable(ErrorString); } + llvm_unreachable("Callee saved registers requested for unknown architecture " + "version"); } BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF) @@ -106,18 +103,16 @@ HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { }; switch(Subtarget.getHexagonArchVersion()) { + case HexagonSubtarget::V1: + break; case HexagonSubtarget::V2: return CalleeSavedRegClassesV2; - break; case HexagonSubtarget::V3: case HexagonSubtarget::V4: return CalleeSavedRegClassesV3; - break; - default: - const char *ErrorString = - "Callee saved register classes requested for unknown archtecture version"; - llvm_unreachable(ErrorString); } + llvm_unreachable("Callee saved register classes requested for unknown " + "architecture version"); } void HexagonRegisterInfo:: @@ -130,7 +125,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) { // Hexagon_TODO: add code } else { - assert(0 && "Cannot handle this call frame pseudo instruction"); + llvm_unreachable("Cannot handle this call frame pseudo instruction"); } MBB.erase(I); } @@ -211,8 +206,7 @@ void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, } else if ((MI.getOpcode() == Hexagon::STriw) || (MI.getOpcode() == Hexagon::STrid) || (MI.getOpcode() == Hexagon::STrih) || - (MI.getOpcode() == Hexagon::STrib) || - (MI.getOpcode() == Hexagon::STriwt)) { + (MI.getOpcode() == Hexagon::STrib)) { // For stores, we need a reserved register. Change // memw(r30 + #10000) = r0 to: // @@ -310,13 +304,11 @@ void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove> } unsigned HexagonRegisterInfo::getEHExceptionRegister() const { - assert(0 && "What is the exception register"); - return 0; + llvm_unreachable("What is the exception register"); } unsigned HexagonRegisterInfo::getEHHandlerRegister() const { - assert(0 && "What is the exception handler register"); - return 0; + llvm_unreachable("What is the exception handler register"); } #define GET_REGINFO_TARGET_DESC diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.h b/lib/Target/Hexagon/HexagonRegisterInfo.h index 33b0c14..fc65305 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.h +++ b/lib/Target/Hexagon/HexagonRegisterInfo.h @@ -48,7 +48,7 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo { HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii); /// Code Generation virtual methods... - const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; + const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; const TargetRegisterClass* const* getCalleeSavedRegClasses( const MachineFunction *MF = 0) const; diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index c05f844..d44eae3 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -1,4 +1,4 @@ -//===- HexagonRegisterInfo.td - Hexagon Register defs ------*- tablegen -*-===// +//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -11,46 +11,51 @@ // Declarations that describe the Hexagon register file. //===----------------------------------------------------------------------===// -class HexagonReg<string n> : Register<n> { - field bits<5> Num; - let Namespace = "Hexagon"; -} +let Namespace = "Hexagon" in { -class HexagonDoubleReg<string n, list<Register> subregs> : - RegisterWithSubRegs<n, subregs> { - field bits<5> Num; - let Namespace = "Hexagon"; -} + class HexagonReg<string n> : Register<n> { + field bits<5> Num; + } -// Registers are identified with 5-bit ID numbers. -// Ri - 32-bit integer registers. -class Ri<bits<5> num, string n> : HexagonReg<n> { - let Num = num; -} + class HexagonDoubleReg<string n, list<Register> subregs> : + RegisterWithSubRegs<n, subregs> { + field bits<5> Num; + } -// Rf - 32-bit floating-point registers. -class Rf<bits<5> num, string n> : HexagonReg<n> { - let Num = num; -} + // Registers are identified with 5-bit ID numbers. + // Ri - 32-bit integer registers. + class Ri<bits<5> num, string n> : HexagonReg<n> { + let Num = num; + } + // Rf - 32-bit floating-point registers. + class Rf<bits<5> num, string n> : HexagonReg<n> { + let Num = num; + } -// Rd - 64 bit registers. -class Rd<bits<5> num, string n, list<Register> subregs> : -HexagonDoubleReg<n, subregs> { - let Num = num; - let SubRegs = subregs; -} + // Rd - 64-bit registers. + class Rd<bits<5> num, string n, list<Register> subregs> : + HexagonDoubleReg<n, subregs> { + let Num = num; + let SubRegs = subregs; + } -class Rp<bits<5> num, string n> : HexagonReg<n> { - let Num = num; -} + // Rp - predicate registers + class Rp<bits<5> num, string n> : HexagonReg<n> { + let Num = num; + } -class Rc<bits<5> num, string n> : HexagonReg<n> { - let Num = num; -} + // Rc - control registers + class Rc<bits<5> num, string n> : HexagonReg<n> { + let Num = num; + } -let Namespace = "Hexagon" in { + // Rj - aliased integer registers + class Rj<string n, Ri R>: HexagonReg<n> { + let Num = R.Num; + let Aliases = [R]; + } def subreg_loreg : SubRegIndex; def subreg_hireg : SubRegIndex; @@ -89,17 +94,17 @@ let Namespace = "Hexagon" in { def R30 : Ri<30, "r30">, DwarfRegNum<[30]>; def R31 : Ri<31, "r31">, DwarfRegNum<[31]>; - - def PC : Ri<31, "r31">, DwarfRegNum<[32]>; - def GP : Ri<31, "r31">, DwarfRegNum<[33]>; + def SP : Rj<"sp", R29>, DwarfRegNum<[29]>; + def FP : Rj<"fp", R30>, DwarfRegNum<[30]>; + def LR : Rj<"lr", R31>, DwarfRegNum<[31]>; // Aliases of the R* registers used to hold 64-bit int values (doubles). - let SubRegIndices = [subreg_loreg, subreg_hireg] in { - def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; - def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; - def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; - def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; - def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; + let SubRegIndices = [subreg_loreg, subreg_hireg], CoveredBySubRegs = 1 in { + def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; + def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; + def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; + def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; + def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; @@ -114,45 +119,38 @@ let Namespace = "Hexagon" in { } // Predicate registers. - def P0 : Rp< 0, "p0">, DwarfRegNum<[63]>; - def P1 : Rp< 0, "p1">, DwarfRegNum<[64]>; - def P2 : Rp< 0, "p2">, DwarfRegNum<[65]>; - def P3 : Rp< 0, "p3">, DwarfRegNum<[66]>; + def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; + def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; + def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; + def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; // Control registers. def SA0 : Rc<0, "sa0">, DwarfRegNum<[67]>; - def LC0 : Rc<0, "lc0">, DwarfRegNum<[68]>; - - def SA1 : Rc<0, "sa1">, DwarfRegNum<[69]>; - def LC1 : Rc<0, "lc1">, DwarfRegNum<[70]>; -} - - - - - - - + def LC0 : Rc<1, "lc0">, DwarfRegNum<[68]>; + def SA1 : Rc<2, "sa1">, DwarfRegNum<[69]>; + def LC1 : Rc<3, "lc1">, DwarfRegNum<[70]>; + def PC : Rc<9, "pc">, DwarfRegNum<[32]>; // is the Dwarf number correct? + def GP : Rc<11, "gp">, DwarfRegNum<[33]>; // is the Dwarf number correct? +} // Register classes. // // FIXME: the register order should be defined in terms of the preferred // allocation order... // -def IntRegs : RegisterClass<"Hexagon", [i32], 32, (add (sequence "R%u", 0, 9), - (sequence "R%u", 12, 28), - R10, R11, R29, R30, - R31)> { +def IntRegs : RegisterClass<"Hexagon", [i32], 32, + (add (sequence "R%u", 0, 9), + (sequence "R%u", 12, 28), + R10, R11, R29, R30, R31)> { } -def DoubleRegs : RegisterClass<"Hexagon", [i64], 64, (add (sequence "D%u", 0, - 4), - (sequence "D%u", 6, 13), - D5, D14, D15)> { +def DoubleRegs : RegisterClass<"Hexagon", [i64], 64, + (add (sequence "D%u", 0, 4), + (sequence "D%u", 6, 13), D5, D14, D15)> { let SubRegClasses = [(IntRegs subreg_loreg, subreg_hireg)]; } @@ -162,8 +160,8 @@ def PredRegs : RegisterClass<"Hexagon", [i1], 32, (add (sequence "P%u", 0, 3))> let Size = 32; } -def CRRegs : RegisterClass<"Hexagon", [i32], 32, (add (sequence "LC%u", 0, 1), - (sequence "SA%u", 0, 1), - PC)> { +def CRRegs : RegisterClass<"Hexagon", [i32], 32, + (add (sequence "LC%u", 0, 1), + (sequence "SA%u", 0, 1), PC, GP)> { let Size = 32; } diff --git a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp index 3ca257f..66a00e1 100644 --- a/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp +++ b/lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp @@ -1,4 +1,4 @@ -//=- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends --=// +//===- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends =// // // The LLVM Compiler Infrastructure // @@ -12,15 +12,12 @@ // //===----------------------------------------------------------------------===// - - -#include "llvm/Pass.h" +#include "HexagonTargetMachine.h" #include "llvm/Function.h" #include "llvm/Instructions.h" -#include "llvm/Transforms/Scalar.h" +#include "llvm/Pass.h" #include "llvm/CodeGen/MachineFunctionAnalysis.h" -#include "HexagonTargetMachine.h" -#include <iostream> +#include "llvm/Transforms/Scalar.h" using namespace llvm; namespace { diff --git a/lib/Target/Hexagon/HexagonSchedule.td b/lib/Target/Hexagon/HexagonSchedule.td index 427d1cb..fbea445 100644 --- a/lib/Target/Hexagon/HexagonSchedule.td +++ b/lib/Target/Hexagon/HexagonSchedule.td @@ -1,4 +1,4 @@ -//===-HexagonSchedule.td - Hexagon Scheduling Definitions -------*- C++ -*-===// +//===- HexagonSchedule.td - Hexagon Scheduling Definitions -*- tablegen -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonSelectCCInfo.td b/lib/Target/Hexagon/HexagonSelectCCInfo.td index f21d928..d8feb89 100644 --- a/lib/Target/Hexagon/HexagonSelectCCInfo.td +++ b/lib/Target/Hexagon/HexagonSelectCCInfo.td @@ -1,4 +1,4 @@ -//=-HexagoSelectCCInfo.td - Selectcc mappings ----------------*- tablegen -*-=// +//===-- HexagoSelectCCInfo.td - Selectcc mappings ----------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // @@ -18,7 +18,7 @@ def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETNE)), - (i32 (MUX_rr (i1 (NOT_Ps (CMPEQrr IntRegs:$lhs, IntRegs:$rhs))), + (i32 (MUX_rr (i1 (NOT_p (CMPEQrr IntRegs:$lhs, IntRegs:$rhs))), IntRegs:$tval, IntRegs:$fval))>; def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, @@ -35,24 +35,24 @@ def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETULT)), - (i32 (MUX_rr (i1 (NOT_Ps (CMPGTUrr IntRegs:$lhs, + (i32 (MUX_rr (i1 (NOT_p (CMPGTUrr IntRegs:$lhs, (ADD_ri IntRegs:$rhs, -1)))), IntRegs:$tval, IntRegs:$fval))>; def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETLT)), - (i32 (MUX_rr (i1 (NOT_Ps (CMPGTrr IntRegs:$lhs, + (i32 (MUX_rr (i1 (NOT_p (CMPGTrr IntRegs:$lhs, (ADD_ri IntRegs:$rhs, -1)))), IntRegs:$tval, IntRegs:$fval))>; def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETLE)), - (i32 (MUX_rr (i1 (NOT_Ps (CMPGTrr IntRegs:$lhs, IntRegs:$rhs))), + (i32 (MUX_rr (i1 (NOT_p (CMPGTrr IntRegs:$lhs, IntRegs:$rhs))), IntRegs:$tval, IntRegs:$fval))>; def : Pat <(i32 (selectcc IntRegs:$lhs, IntRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETULE)), - (i32 (MUX_rr (i1 (NOT_Ps (CMPGTUrr IntRegs:$lhs, IntRegs:$rhs))), + (i32 (MUX_rr (i1 (NOT_p (CMPGTUrr IntRegs:$lhs, IntRegs:$rhs))), IntRegs:$tval, IntRegs:$fval))>; @@ -86,7 +86,7 @@ def : Pat <(i32 (selectcc PredRegs:$lhs, PredRegs:$rhs, IntRegs:$tval, def : Pat <(i32 (selectcc PredRegs:$lhs, PredRegs:$rhs, IntRegs:$tval, IntRegs:$fval, SETEQ)), - (i32 (MUX_rr (i1 (NOT_pp (XOR_pp PredRegs:$lhs, PredRegs:$rhs))), + (i32 (MUX_rr (i1 (NOT_p (XOR_pp PredRegs:$lhs, PredRegs:$rhs))), IntRegs:$tval, IntRegs:$fval))>; diff --git a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h index 86fa026..0673e4d 100644 --- a/lib/Target/Hexagon/HexagonSelectionDAGInfo.h +++ b/lib/Target/Hexagon/HexagonSelectionDAGInfo.h @@ -1,4 +1,4 @@ -//=-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ------*- C++ -*-=// +//===-- HexagonSelectionDAGInfo.h - Hexagon SelectionDAG Info ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp index f4d3647..d10c9f2 100644 --- a/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp +++ b/lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp @@ -1,4 +1,4 @@ -//===---- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -----===// +//===-- HexagonSplitTFRCondSets.cpp - split TFR condsets into xfers -------===// // // The LLVM Compiler Infrastructure // @@ -6,7 +6,7 @@ // License. See LICENSE.TXT for details. // // -//===----------------------------------------------------------------------===//// +//===----------------------------------------------------------------------===// // This pass tries to provide opportunities for better optimization of muxes. // The default code generated for something like: flag = (a == b) ? 1 : 3; // would be: @@ -27,31 +27,24 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "xfer" +#include "HexagonTargetMachine.h" +#include "HexagonSubtarget.h" +#include "HexagonMachineFunctionInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/CodeGen/LatencyPriorityQueue.h" -#include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/MachineDominators.h" #include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/ScheduleHazardRecognizer.h" -#include "llvm/Target/TargetMachine.h" +#include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" -#include "llvm/ADT/Statistic.h" #include "llvm/Support/MathExtras.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "HexagonTargetMachine.h" -#include "HexagonSubtarget.h" -#include "HexagonMachineFunctionInfo.h" -#include <map> -#include <iostream> - -#include "llvm/Support/CommandLine.h" -#define DEBUG_TYPE "xfer" - using namespace llvm; diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index 83fb498..654d336 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -1,4 +1,4 @@ -//===- HexagonSubtarget.cpp - Hexagon Subtarget Information ---------------===// +//===-- HexagonSubtarget.cpp - Hexagon Subtarget Information --------------===// // // The LLVM Compiler Infrastructure // @@ -52,6 +52,9 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUString); + // Max issue per cycle == bundle width. + InstrItins.IssueWidth = 4; + if (EnableMemOps) UseMemOps = true; else diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index 6de85df..3079086 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -1,4 +1,4 @@ -//==-- HexagonSubtarget.h - Define Subtarget for the Hexagon ----*- C++ -*-==// +//===-- HexagonSubtarget.h - Define Subtarget for the Hexagon ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonTargetMachine.cpp b/lib/Target/Hexagon/HexagonTargetMachine.cpp index b29e92c..319eab2 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -7,6 +7,7 @@ // //===----------------------------------------------------------------------===// // +// Implements the info about Hexagon target spec. // //===----------------------------------------------------------------------===// @@ -16,11 +17,10 @@ #include "llvm/Module.h" #include "llvm/CodeGen/Passes.h" #include "llvm/PassManager.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Transforms/IPO/PassManagerBuilder.h" #include "llvm/Transforms/Scalar.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/TargetRegistry.h" -#include <iostream> using namespace llvm; @@ -56,7 +56,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), DataLayout("e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:32:32-a0:0") , - Subtarget(TT, CPU, FS), TLInfo(*this), InstrInfo(Subtarget), + Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this), TSInfo(*this), FrameLowering(Subtarget), InstrItins(&Subtarget.getInstrItineraryData()) { @@ -76,14 +76,38 @@ bool HexagonTargetMachine::addPassesForOptimizations(PassManagerBase &PM) { return true; } -bool HexagonTargetMachine::addInstSelector(PassManagerBase &PM) { - PM.add(createHexagonRemoveExtendOps(*this)); - PM.add(createHexagonISelDag(*this)); +namespace { +/// Hexagon Code Generator Pass Configuration Options. +class HexagonPassConfig : public TargetPassConfig { +public: + HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + HexagonTargetMachine &getHexagonTargetMachine() const { + return getTM<HexagonTargetMachine>(); + } + + virtual bool addInstSelector(); + virtual bool addPreRegAlloc(); + virtual bool addPostRegAlloc(); + virtual bool addPreSched2(); + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) { + return new HexagonPassConfig(this, PM); +} + +bool HexagonPassConfig::addInstSelector() { + PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine())); + PM.add(createHexagonISelDag(getHexagonTargetMachine())); + PM.add(createHexagonPeephole()); return false; } -bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) { +bool HexagonPassConfig::addPreRegAlloc() { if (!DisableHardwareLoops) { PM.add(createHexagonHardwareLoops()); } @@ -91,28 +115,28 @@ bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) { return false; } -bool HexagonTargetMachine::addPostRegAlloc(PassManagerBase &PM) { - PM.add(createHexagonCFGOptimizer(*this)); +bool HexagonPassConfig::addPostRegAlloc() { + PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine())); return true; } -bool HexagonTargetMachine::addPreSched2(PassManagerBase &PM) { - PM.add(createIfConverterPass()); +bool HexagonPassConfig::addPreSched2() { + addPass(IfConverterID); return true; } -bool HexagonTargetMachine::addPreEmitPass(PassManagerBase &PM) { +bool HexagonPassConfig::addPreEmitPass() { if (!DisableHardwareLoops) { PM.add(createHexagonFixupHwLoops()); } // Expand Spill code for predicate registers. - PM.add(createHexagonExpandPredSpillCode(*this)); + PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine())); // Split up TFRcondsets into conditional transfers. - PM.add(createHexagonSplitTFRCondSets(*this)); + PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine())); return false; } diff --git a/lib/Target/Hexagon/HexagonTargetMachine.h b/lib/Target/Hexagon/HexagonTargetMachine.h index e27d3ae..70bea56 100644 --- a/lib/Target/Hexagon/HexagonTargetMachine.h +++ b/lib/Target/Hexagon/HexagonTargetMachine.h @@ -29,8 +29,8 @@ class Module; class HexagonTargetMachine : public LLVMTargetMachine { const TargetData DataLayout; // Calculates type size & alignment. HexagonSubtarget Subtarget; - HexagonTargetLowering TLInfo; HexagonInstrInfo InstrInfo; + HexagonTargetLowering TLInfo; HexagonSelectionDAGInfo TSInfo; HexagonFrameLowering FrameLowering; const InstrItineraryData* InstrItins; @@ -72,11 +72,7 @@ public: // Pass Pipeline Configuration. virtual bool addPassesForOptimizations(PassManagerBase &PM); - virtual bool addInstSelector(PassManagerBase &PM); - virtual bool addPreEmitPass(PassManagerBase &PM); - virtual bool addPreRegAlloc(llvm::PassManagerBase &PM); - virtual bool addPostRegAlloc(PassManagerBase &PM); - virtual bool addPreSched2(PassManagerBase &PM); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); }; extern bool flag_aligned_memcpy; diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp index 188337d..d3ce5a6 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.cpp +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.cpp @@ -1,4 +1,4 @@ -//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties ----*- C++ -*-===// +//===-- HexagonTargetObjectFile.cpp - Hexagon asm properties --------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonTargetObjectFile.h b/lib/Target/Hexagon/HexagonTargetObjectFile.h index 101c1f2..6933450 100644 --- a/lib/Target/Hexagon/HexagonTargetObjectFile.h +++ b/lib/Target/Hexagon/HexagonTargetObjectFile.h @@ -1,4 +1,4 @@ -//===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==// +//===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/HexagonVarargsCallingConvention.h b/lib/Target/Hexagon/HexagonVarargsCallingConvention.h index 21b2d67..9305c27 100644 --- a/lib/Target/Hexagon/HexagonVarargsCallingConvention.h +++ b/lib/Target/Hexagon/HexagonVarargsCallingConvention.h @@ -1,4 +1,4 @@ -//==-- HexagonVarargsCallingConvention.h - Calling Conventions ---*- C++ -*-==// +//===-- HexagonVarargsCallingConvention.h - Calling Conventions -*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h new file mode 100644 index 0000000..ed55c3c --- /dev/null +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h @@ -0,0 +1,43 @@ +//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains small standalone helper functions and enum definitions for +// the Hexagon target useful for the compiler back-end and the MC libraries. +// As such, it deliberately does not include references to LLVM core +// code gen types, passes, etc.. +// +//===----------------------------------------------------------------------===// + +#ifndef HEXAGONBASEINFO_H +#define HEXAGONBASEINFO_H + +namespace llvm { + +/// HexagonII - This namespace holds all of the target specific flags that +/// instruction info tracks. +/// +namespace HexagonII { + + // *** The code below must match HexagonInstrFormat*.td *** // + + // MCInstrDesc TSFlags + enum { + + // Predicated instructions. + PredicatedPos = 1, + PredicatedMask = 0x1 + }; + + // *** The code above must match HexagonInstrFormat*.td *** // + +} // End namespace HexagonII. + +} // End namespace llvm. + +#endif diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index 188693c..d6e6c36 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -1,4 +1,4 @@ -//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties -----------*- C++ -*-===// +//===-- HexagonMCAsmInfo.cpp - Hexagon asm properties ---------------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index 8196e95..d336cd5 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -1,4 +1,4 @@ -//===-- HexagonTargetAsmInfo.h - Hexagon asm properties ---------*- C++ -*--==// +//===-- HexagonTargetAsmInfo.h - Hexagon asm properties --------*- C++ -*--===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index 625f07c..74abc56 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- HexagonMCTargetDesc.cpp - Cell Hexagon Target Descriptions -----*- C++ -*-===// +//===-- HexagonMCTargetDesc.cpp - Cell Hexagon Target Descriptions --------===// // // The LLVM Compiler Infrastructure // @@ -18,6 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC diff --git a/lib/Target/Hexagon/Makefile b/lib/Target/Hexagon/Makefile index c936e92..34bc68d 100644 --- a/lib/Target/Hexagon/Makefile +++ b/lib/Target/Hexagon/Makefile @@ -16,6 +16,7 @@ BUILT_SOURCES = HexagonGenRegisterInfo.inc \ HexagonGenAsmWriter.inc \ HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \ HexagonGenCallingConv.inc \ + HexagonGenDFAPacketizer.inc \ HexagonAsmPrinter.cpp DIRS = TargetInfo MCTargetDesc |