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-rw-r--r--lib/Target/IA64/IA64InstrInfo.td8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td
index 536e617..8801a72 100644
--- a/lib/Target/IA64/IA64InstrInfo.td
+++ b/lib/Target/IA64/IA64InstrInfo.td
@@ -539,7 +539,7 @@ def CADDIMM22 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$src1, s22imm:$imm, PR
def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
"sub $dst = $imm, $src2">, isA;
-let isStore = 1, noResults = 1 in {
+let isStore = 1 in {
def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
"st1 [$dstPtr] = $value">, isM;
def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
@@ -687,7 +687,7 @@ def FP_TO_UINT : Pat<(i64 (fp_to_uint FP:$src)),
(GETFSIG (FCVTFXUTRUNC FP:$src))>;
-let isTerminator = 1, isBranch = 1, noResults = 1 in {
+let isTerminator = 1, isBranch = 1 in {
def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst),
"(p0) brl.cond.sptk $dst">, isB;
def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
@@ -696,7 +696,7 @@ let isTerminator = 1, isBranch = 1, noResults = 1 in {
"($qp) br.cond.sptk $dst">, isB;
}
-let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
+let isCall = 1, /* isTerminator = 1, isBranch = 1, */
Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
// all calls clobber non-callee-saved registers, and for now, they are these:
Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
@@ -733,7 +733,7 @@ let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
}
// Return branch:
-let isTerminator = 1, isReturn = 1, noResults = 1 in
+let isTerminator = 1, isReturn = 1 in
def RET : AForm_DAG<0x03, 0x0b, (outs), (ins),
"br.ret.sptk.many rp",
[(retflag)]>, isB; // return