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path: root/lib/Target/MBlaze/MBlazeISelLowering.cpp
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Diffstat (limited to 'lib/Target/MBlaze/MBlazeISelLowering.cpp')
-rw-r--r--lib/Target/MBlaze/MBlazeISelLowering.cpp124
1 files changed, 73 insertions, 51 deletions
diff --git a/lib/Target/MBlaze/MBlazeISelLowering.cpp b/lib/Target/MBlaze/MBlazeISelLowering.cpp
index 1730b68..2fc55c5 100644
--- a/lib/Target/MBlaze/MBlazeISelLowering.cpp
+++ b/lib/Target/MBlaze/MBlazeISelLowering.cpp
@@ -56,9 +56,9 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
setBooleanContents(ZeroOrOneBooleanContent);
// Set up the register classes
- addRegisterClass(MVT::i32, MBlaze::CPURegsRegisterClass);
+ addRegisterClass(MVT::i32, MBlaze::GPRRegisterClass);
if (Subtarget->hasFPU()) {
- addRegisterClass(MVT::f32, MBlaze::FGR32RegisterClass);
+ addRegisterClass(MVT::f32, MBlaze::GPRRegisterClass);
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
}
@@ -86,6 +86,10 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+ // Sign extended loads must be expanded
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
+
// MBlaze has no REM or DIVREM operations.
setOperationAction(ISD::UREM, MVT::i32, Expand);
setOperationAction(ISD::SREM, MVT::i32, Expand);
@@ -253,12 +257,12 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
loop->addSuccessor(finish);
loop->addSuccessor(loop);
- unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
+ unsigned IAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
.addReg(MI->getOperand(2).getReg())
.addImm(31);
- unsigned IVAL = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
+ unsigned IVAL = R.createVirtualRegister(MBlaze::GPRRegisterClass);
BuildMI(BB, dl, TII->get(MBlaze::ADDI), IVAL)
.addReg(MI->getOperand(1).getReg())
.addImm(0);
@@ -267,14 +271,14 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
.addReg(IAMT)
.addMBB(finish);
- unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
- unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
+ unsigned DST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
+ unsigned NDST = R.createVirtualRegister(MBlaze::GPRRegisterClass);
BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
.addReg(IVAL).addMBB(BB)
.addReg(NDST).addMBB(loop);
- unsigned SAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
- unsigned NAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
+ unsigned SAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
+ unsigned NAMT = R.createVirtualRegister(MBlaze::GPRRegisterClass);
BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
.addReg(IAMT).addMBB(BB)
.addReg(NAMT).addMBB(loop);
@@ -286,7 +290,7 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
else if (MI->getOpcode() == MBlaze::ShiftRL)
BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
else
- llvm_unreachable( "Cannot lower unknown shift instruction" );
+ llvm_unreachable("Cannot lower unknown shift instruction");
BuildMI(loop, dl, TII->get(MBlaze::ADDI), NAMT)
.addReg(SAMT)
@@ -328,7 +332,7 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
unsigned Opc;
switch (MI->getOperand(4).getImm()) {
- default: llvm_unreachable( "Unknown branch condition" );
+ default: llvm_unreachable("Unknown branch condition");
case MBlazeCC::EQ: Opc = MBlaze::BNEID; break;
case MBlazeCC::NE: Opc = MBlaze::BEQID; break;
case MBlazeCC::GT: Opc = MBlaze::BLEID; break;
@@ -392,9 +396,9 @@ SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
.getValue(1);
} else {
- llvm_unreachable( "Cannot lower select_cc with unknown type" );
+ llvm_unreachable("Cannot lower select_cc with unknown type");
}
-
+
return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
CompareFlag);
}
@@ -421,15 +425,12 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
SDValue HiPart;
// FIXME there isn't actually debug info here
DebugLoc dl = Op.getDebugLoc();
- bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
- unsigned char OpFlag = IsPIC ? MBlazeII::MO_GOT : MBlazeII::MO_ABS_HILO;
EVT PtrVT = Op.getValueType();
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
- SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
+ SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 0);
return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, JTI);
- //return JTI;
}
SDValue MBlazeTargetLowering::
@@ -440,7 +441,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const {
DebugLoc dl = Op.getDebugLoc();
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
- N->getOffset(), MBlazeII::MO_ABS_HILO);
+ N->getOffset(), 0);
return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
}
@@ -456,7 +457,8 @@ SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
// vastart just stores the address of the VarArgsFrameIndex slot into the
// memory location argument.
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
- return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
+ return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
+ MachinePointerInfo(SV),
false, false, 0);
}
@@ -466,8 +468,8 @@ SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op,
#include "MBlazeGenCallingConv.inc"
-static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
- EVT LocVT, CCValAssign::LocInfo LocInfo,
+static bool CC_MBlaze2(unsigned ValNo, MVT ValVT,
+ MVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State) {
static const unsigned RegsSize=6;
static const unsigned IntRegs[] = {
@@ -475,11 +477,6 @@ static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
MBlaze::R8, MBlaze::R9, MBlaze::R10
};
- static const unsigned FltRegs[] = {
- MBlaze::F5, MBlaze::F6, MBlaze::F7,
- MBlaze::F8, MBlaze::F9, MBlaze::F10
- };
-
unsigned Reg=0;
// Promote i8 and i16
@@ -497,7 +494,7 @@ static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
Reg = State.AllocateReg(IntRegs, RegsSize);
LocVT = MVT::i32;
} else if (ValVT == MVT::f32) {
- Reg = State.AllocateReg(FltRegs, RegsSize);
+ Reg = State.AllocateReg(IntRegs, RegsSize);
LocVT = MVT::f32;
}
@@ -556,7 +553,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
// Walk the register/memloc assignments, inserting copies/loads.
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
CCValAssign &VA = ArgLocs[i];
- EVT RegVT = VA.getLocVT();
+ MVT RegVT = VA.getLocVT();
SDValue Arg = OutVals[i];
// Promote the value if needed.
@@ -591,7 +588,8 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
// emit ISD::STORE whichs stores the
// parameter value to a stack Location
- MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
+ MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
+ MachinePointerInfo(),
false, false, 0));
}
}
@@ -616,13 +614,12 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
// node so that legalize doesn't hack it.
- unsigned char OpFlag = MBlazeII::MO_NO_FLAG;
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
- getPointerTy(), 0, OpFlag);
+ getPointerTy(), 0, 0);
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
- getPointerTy(), OpFlag);
+ getPointerTy(), 0);
// MBlazeJmpLink = #chain, #target_address, #opt_in_flags...
// = Chain, Callee, Reg#1, Reg#2, ...
@@ -678,7 +675,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
RVLocs[i].getValVT(), InFlag).getValue(1);
InFlag = Chain.getValue(2);
InVals.push_back(Chain.getValue(0));
- }
+ }
return Chain;
}
@@ -723,14 +720,14 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
// Arguments stored on registers
if (VA.isRegLoc()) {
- EVT RegVT = VA.getLocVT();
+ MVT RegVT = VA.getLocVT();
ArgRegEnd = VA.getLocReg();
TargetRegisterClass *RC = 0;
if (RegVT == MVT::i32)
- RC = MBlaze::CPURegsRegisterClass;
+ RC = MBlaze::GPRRegisterClass;
else if (RegVT == MVT::f32)
- RC = MBlaze::FGR32RegisterClass;
+ RC = MBlaze::GPRRegisterClass;
else
llvm_unreachable("RegVT not supported by LowerFormalArguments");
@@ -780,20 +777,21 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
// Create load nodes to retrieve arguments from the stack
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
- InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
+ InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
+ MachinePointerInfo::getFixedStack(FI),
false, false, 0));
}
}
// To meet ABI, when VARARGS are passed on registers, the registers
// must have their values written to the caller stack frame. If the last
- // argument was placed in the stack, there's no need to save any register.
+ // argument was placed in the stack, there's no need to save any register.
if ((isVarArg) && ArgRegEnd) {
if (StackPtr.getNode() == 0)
StackPtr = DAG.getRegister(StackReg, getPointerTy());
// The last register argument that must be saved is MBlaze::R10
- TargetRegisterClass *RC = MBlaze::CPURegsRegisterClass;
+ TargetRegisterClass *RC = MBlaze::GPRRegisterClass;
unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
@@ -808,7 +806,8 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
int FI = MFI->CreateFixedObject(4, 0, true);
MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
- OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
+ OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
+ MachinePointerInfo(),
false, false, 0));
// Record the frame index of the first variable argument
@@ -818,7 +817,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
}
}
- // All stores are grouped in one node to allow the matching between
+ // All stores are grouped in one node to allow the matching between
// the size of Ins and InVals. This only happens when on varg functions
if (!OutChains.empty()) {
OutChains.push_back(Chain);
@@ -909,6 +908,37 @@ getConstraintType(const std::string &Constraint) const
return TargetLowering::getConstraintType(Constraint);
}
+/// Examine constraint type and operand type and determine a weight value.
+/// This object must already have been set up with the operand type
+/// and the current alternative constraint selected.
+TargetLowering::ConstraintWeight
+MBlazeTargetLowering::getSingleConstraintMatchWeight(
+ AsmOperandInfo &info, const char *constraint) const {
+ ConstraintWeight weight = CW_Invalid;
+ Value *CallOperandVal = info.CallOperandVal;
+ // If we don't have a value, we can't do a match,
+ // but allow it at the lowest weight.
+ if (CallOperandVal == NULL)
+ return CW_Default;
+ const Type *type = CallOperandVal->getType();
+ // Look at the constraint type.
+ switch (*constraint) {
+ default:
+ weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
+ break;
+ case 'd':
+ case 'y':
+ if (type->isIntegerTy())
+ weight = CW_Register;
+ break;
+ case 'f':
+ if (type->isFloatTy())
+ weight = CW_Register;
+ break;
+ }
+ return weight;
+}
+
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
/// return a list of registers that can be used to satisfy the constraint.
/// This should only be used for C_RegisterClass constraints.
@@ -917,10 +947,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
- return std::make_pair(0U, MBlaze::CPURegsRegisterClass);
+ return std::make_pair(0U, MBlaze::GPRRegisterClass);
case 'f':
if (VT == MVT::f32)
- return std::make_pair(0U, MBlaze::FGR32RegisterClass);
+ return std::make_pair(0U, MBlaze::GPRRegisterClass);
}
}
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
@@ -940,6 +970,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
// GCC MBlaze Constraint Letters
case 'd':
case 'y':
+ case 'f':
return make_vector<unsigned>(
MBlaze::R3, MBlaze::R4, MBlaze::R5, MBlaze::R6,
MBlaze::R7, MBlaze::R9, MBlaze::R10, MBlaze::R11,
@@ -947,15 +978,6 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const {
MBlaze::R22, MBlaze::R23, MBlaze::R24, MBlaze::R25,
MBlaze::R26, MBlaze::R27, MBlaze::R28, MBlaze::R29,
MBlaze::R30, MBlaze::R31, 0);
-
- case 'f':
- return make_vector<unsigned>(
- MBlaze::F3, MBlaze::F4, MBlaze::F5, MBlaze::F6,
- MBlaze::F7, MBlaze::F9, MBlaze::F10, MBlaze::F11,
- MBlaze::F12, MBlaze::F19, MBlaze::F20, MBlaze::F21,
- MBlaze::F22, MBlaze::F23, MBlaze::F24, MBlaze::F25,
- MBlaze::F26, MBlaze::F27, MBlaze::F28, MBlaze::F29,
- MBlaze::F30, MBlaze::F31, 0);
}
return std::vector<unsigned>();
}
generated by cgit v1.1 at 2025-08-25 06:27:16 +0000