diff options
Diffstat (limited to 'lib/Target/MSP430/MSP430ISelLowering.cpp')
| -rw-r--r-- | lib/Target/MSP430/MSP430ISelLowering.cpp | 47 |
1 files changed, 20 insertions, 27 deletions
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index 22936dd..18141a6 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -57,7 +57,8 @@ HWMultMode("msp430-hwmult-mode", cl::Hidden, "Assume hardware multiplier cannot be used inside interrupts"), clEnumValEnd)); -MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) +MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM, + const MSP430Subtarget &STI) : TargetLowering(TM) { // Set up the register classes. @@ -65,7 +66,7 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) addRegisterClass(MVT::i16, &MSP430::GR16RegClass); // Compute derived properties from the register classes - computeRegisterProperties(); + computeRegisterProperties(STI.getRegisterInfo()); // Provide all sorts of operation actions @@ -80,11 +81,13 @@ MSP430TargetLowering::MSP430TargetLowering(const TargetMachine &TM) setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Expand); + } // We don't have any truncstores setTruncStoreAction(MVT::i16, MVT::i8, Expand); @@ -222,10 +225,10 @@ MSP430TargetLowering::getConstraintType(const std::string &Constraint) const { return TargetLowering::getConstraintType(Constraint); } -std::pair<unsigned, const TargetRegisterClass*> -MSP430TargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { +std::pair<unsigned, const TargetRegisterClass *> +MSP430TargetLowering::getRegForInlineAsmConstraint( + const TargetRegisterInfo *TRI, const std::string &Constraint, + MVT VT) const { if (Constraint.size() == 1) { // GCC Constraint Letters switch (Constraint[0]) { @@ -238,7 +241,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, } } - return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); + return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); } //===----------------------------------------------------------------------===// @@ -326,7 +329,7 @@ static void AnalyzeArguments(CCState &State, if (!UseStack && Parts <= RegsLeft) { unsigned FirstVal = ValNo; for (unsigned j = 0; j < Parts; j++) { - unsigned Reg = State.AllocateReg(RegList, NbRegs); + unsigned Reg = State.AllocateReg(RegList); State.addLoc(CCValAssign::getReg(ValNo++, ArgVT, Reg, LocVT, LocInfo)); RegsLeft--; } @@ -977,11 +980,7 @@ SDValue MSP430TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { } else { SDValue Zero = DAG.getConstant(0, VT); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); - SmallVector<SDValue, 4> Ops; - Ops.push_back(One); - Ops.push_back(Zero); - Ops.push_back(TargetCC); - Ops.push_back(Flag); + SDValue Ops[] = {One, Zero, TargetCC, Flag}; return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); } } @@ -999,11 +998,7 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); - SmallVector<SDValue, 4> Ops; - Ops.push_back(TrueV); - Ops.push_back(FalseV); - Ops.push_back(TargetCC); - Ops.push_back(Flag); + SDValue Ops[] = {TrueV, FalseV, TargetCC, Flag}; return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, Ops); } @@ -1199,8 +1194,7 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI, MachineFunction *F = BB->getParent(); MachineRegisterInfo &RI = F->getRegInfo(); DebugLoc dl = MI->getDebugLoc(); - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *F->getSubtarget().getInstrInfo(); unsigned Opc; const TargetRegisterClass * RC; @@ -1311,8 +1305,7 @@ MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, Opc == MSP430::Srl8 || Opc == MSP430::Srl16) return EmitShiftInstr(MI, BB); - const TargetInstrInfo &TII = - *getTargetMachine().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); assert((Opc == MSP430::Select16 || Opc == MSP430::Select8) && |