diff options
Diffstat (limited to 'lib/Target/Mips/Mips.td')
| -rw-r--r-- | lib/Target/Mips/Mips.td | 39 |
1 files changed, 30 insertions, 9 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 50a5f65..1199cc4 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -16,7 +16,7 @@ include "../Target.td" //===----------------------------------------------------------------------===// -// Descriptions +// Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// include "MipsRegisterInfo.td" @@ -30,22 +30,43 @@ def MipsInstrInfo : InstrInfo { } //===----------------------------------------------------------------------===// -// CPU Directives // +// Mips Subtarget features // //===----------------------------------------------------------------------===// -// Not currently supported, but work as SubtargetFeature placeholder. -def FeatureMipsIII : SubtargetFeature<"mips3", "IsMipsIII", "true", - "MipsIII ISA Support">; +def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", + "General Purpose Registers are 64-bit wide.">; +def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", + "Support 64-bit FP registers.">; +def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", + "true", "Only supports single precision float">; +def FeatureAllegrexVFPU : SubtargetFeature<"allegrex-vfpu", "HasAllegrexVFPU", + "true", "Enable Allegrex VFPU instructions.">; +def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", + "Mips2 ISA Support">; +def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", + "Enable o32 ABI">; +def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", + "Enable eabi ABI">; //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// -def : Processor<"mips1", MipsGenericItineraries, []>; -def : Processor<"r2000", MipsGenericItineraries, []>; -def : Processor<"r3000", MipsGenericItineraries, []>; +class Proc<string Name, list<SubtargetFeature> Features> + : Processor<Name, MipsGenericItineraries, Features>; + +def : Proc<"mips1", []>; +def : Proc<"r2000", []>; +def : Proc<"r3000", []>; + +def : Proc<"mips2", [FeatureMips2]>; +def : Proc<"r6000", [FeatureMips2]>; + +// Allegrex is a 32bit subset of r4000, both for interger and fp registers, +// but much more similar to Mips2 than Mips3. +def : Proc<"allegrex", [FeatureMips2, FeatureSingleFloat, FeatureAllegrexVFPU, + FeatureEABI]>; def Mips : Target { let InstructionSet = MipsInstrInfo; } - |