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-rw-r--r--lib/Target/Mips/MipsRegisterInfo.td13
1 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td
index 22c4890..cef5ebf 100644
--- a/lib/Target/Mips/MipsRegisterInfo.td
+++ b/lib/Target/Mips/MipsRegisterInfo.td
@@ -231,6 +231,16 @@ let Namespace = "Mips" in {
def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
DSPOutFlag21, DSPOutFlag22,
DSPOutFlag23]>;
+
+ // MSA-ASE control registers.
+ def MSAIR : Register<"0">;
+ def MSACSR : Register<"1">;
+ def MSAAccess : Register<"2">;
+ def MSASave : Register<"3">;
+ def MSAModify : Register<"4">;
+ def MSARequest : Register<"5">;
+ def MSAMap : Register<"6">;
+ def MSAUnmap : Register<"7">;
}
//===----------------------------------------------------------------------===//
@@ -329,6 +339,9 @@ def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
(sequence "W%u", 0, 31)>;
+def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
+ MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>;
+
// Hi/Lo Registers
def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;