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path: root/lib/Target/Mips/MipsSEFrameLowering.cpp
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Diffstat (limited to 'lib/Target/Mips/MipsSEFrameLowering.cpp')
-rw-r--r--lib/Target/Mips/MipsSEFrameLowering.cpp125
1 files changed, 94 insertions, 31 deletions
diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp
index 2b76704..91ffb94 100644
--- a/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -40,6 +40,8 @@ public:
private:
bool expandInstr(MachineBasicBlock &MBB, Iter I);
+ void expandLoadCCond(MachineBasicBlock &MBB, Iter I);
+ void expandStoreCCond(MachineBasicBlock &MBB, Iter I);
void expandLoadACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
void expandStoreACC(MachineBasicBlock &MBB, Iter I, unsigned RegSize);
bool expandCopy(MachineBasicBlock &MBB, Iter I);
@@ -47,16 +49,12 @@ private:
unsigned Src, unsigned RegSize);
MachineFunction &MF;
- const MipsSEInstrInfo &TII;
- const MipsRegisterInfo &RegInfo;
MachineRegisterInfo &MRI;
};
}
ExpandPseudo::ExpandPseudo(MachineFunction &MF_)
- : MF(MF_),
- TII(*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo())),
- RegInfo(TII.getRegisterInfo()), MRI(MF.getRegInfo()) {}
+ : MF(MF_), MRI(MF.getRegInfo()) {}
bool ExpandPseudo::expand() {
bool Expanded = false;
@@ -71,6 +69,14 @@ bool ExpandPseudo::expand() {
bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
switch(I->getOpcode()) {
+ case Mips::LOAD_CCOND_DSP:
+ case Mips::LOAD_CCOND_DSP_P8:
+ expandLoadCCond(MBB, I);
+ break;
+ case Mips::STORE_CCOND_DSP:
+ case Mips::STORE_CCOND_DSP_P8:
+ expandStoreCCond(MBB, I);
+ break;
case Mips::LOAD_AC64:
case Mips::LOAD_AC64_P8:
case Mips::LOAD_AC_DSP:
@@ -103,6 +109,46 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
return true;
}
+void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) {
+ // load $vr, FI
+ // copy ccond, $vr
+
+ assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
+ const TargetRegisterClass *RC = RegInfo.intRegClass(4);
+ unsigned VR = MRI.createVirtualRegister(RC);
+ unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+
+ TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0);
+ BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
+ .addReg(VR, RegState::Kill);
+}
+
+void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) {
+ // copy $vr, ccond
+ // store $vr, FI
+
+ assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
+ const TargetRegisterClass *RC = RegInfo.intRegClass(4);
+ unsigned VR = MRI.createVirtualRegister(RC);
+ unsigned Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
+
+ BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
+ .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
+ TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0);
+}
+
void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
unsigned RegSize) {
// load $vr0, FI
@@ -112,6 +158,11 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I,
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
unsigned VR0 = MRI.createVirtualRegister(RC);
unsigned VR1 = MRI.createVirtualRegister(RC);
@@ -136,6 +187,11 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I,
assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
unsigned VR0 = MRI.createVirtualRegister(RC);
unsigned VR1 = MRI.createVirtualRegister(RC);
@@ -170,6 +226,11 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned Dst,
// copy $vr1, src_hi
// copy dst_hi, $vr1
+ const MipsSEInstrInfo &TII =
+ *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
unsigned VR0 = MRI.createVirtualRegister(RC);
unsigned VR1 = MRI.createVirtualRegister(RC);
@@ -204,10 +265,12 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
MachineBasicBlock &MBB = MF.front();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
- const MipsRegisterInfo *RegInfo =
- static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
const MipsSEInstrInfo &TII =
*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
MachineBasicBlock::iterator MBBI = MBB.begin();
DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
@@ -222,7 +285,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
if (StackSize == 0 && !MFI->adjustsStack()) return;
MachineModuleInfo &MMI = MF.getMMI();
- std::vector<MachineMove> &Moves = MMI.getFrameMoves();
+ const MCRegisterInfo &MRI = MMI.getContext().getRegisterInfo();
MachineLocation DstML, SrcML;
// Adjust stack.
@@ -232,9 +295,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl,
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
- DstML = MachineLocation(MachineLocation::VirtualFP);
- SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
- Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
+ MMI.addFrameInst(
+ MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
@@ -258,21 +320,22 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
// If Reg is a double precision register, emit two cfa_offsets,
// one for each of the paired single precision registers.
if (Mips::AFGR64RegClass.contains(Reg)) {
- MachineLocation DstML0(MachineLocation::VirtualFP, Offset);
- MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4);
- MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips::sub_fpeven));
- MachineLocation SrcML1(RegInfo->getSubReg(Reg, Mips::sub_fpodd));
+ unsigned Reg0 =
+ MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpeven), true);
+ unsigned Reg1 =
+ MRI.getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_fpodd), true);
if (!STI.isLittle())
- std::swap(SrcML0, SrcML1);
+ std::swap(Reg0, Reg1);
- Moves.push_back(MachineMove(CSLabel, DstML0, SrcML0));
- Moves.push_back(MachineMove(CSLabel, DstML1, SrcML1));
+ MMI.addFrameInst(
+ MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
+ MMI.addFrameInst(
+ MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
} else {
// Reg is either in CPURegs or FGR32.
- DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
- SrcML = MachineLocation(Reg);
- Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
+ MMI.addFrameInst(MCCFIInstruction::createOffset(
+ CSLabel, MRI.getDwarfRegNum(Reg, 1), Offset));
}
}
}
@@ -286,7 +349,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
if (!MBB.isLiveIn(ehDataReg(I)))
MBB.addLiveIn(ehDataReg(I));
TII.storeRegToStackSlot(MBB, MBBI, ehDataReg(I), false,
- MipsFI->getEhDataRegFI(I), RC, RegInfo);
+ MipsFI->getEhDataRegFI(I), RC, &RegInfo);
}
// Emit .cfi_offset directives for eh data registers.
@@ -295,9 +358,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
for (int I = 0; I < 4; ++I) {
int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
- DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
- SrcML = MachineLocation(ehDataReg(I));
- Moves.push_back(MachineMove(CSLabel2, DstML, SrcML));
+ unsigned Reg = MRI.getDwarfRegNum(ehDataReg(I), true);
+ MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
}
}
@@ -310,9 +372,8 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const {
MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
BuildMI(MBB, MBBI, dl,
TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
- DstML = MachineLocation(FP);
- SrcML = MachineLocation(MachineLocation::VirtualFP);
- Moves.push_back(MachineMove(SetFPLabel, DstML, SrcML));
+ MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
+ SetFPLabel, MRI.getDwarfRegNum(FP, true)));
}
}
@@ -321,10 +382,12 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
MachineFrameInfo *MFI = MF.getFrameInfo();
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
- const MipsRegisterInfo *RegInfo =
- static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
const MipsSEInstrInfo &TII =
*static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo());
+ const MipsRegisterInfo &RegInfo =
+ *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo());
+
DebugLoc dl = MBBI->getDebugLoc();
unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP;
@@ -355,7 +418,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF,
// Insert instructions that restore eh data registers.
for (int J = 0; J < 4; ++J) {
TII.loadRegFromStackSlot(MBB, I, ehDataReg(J), MipsFI->getEhDataRegFI(J),
- RC, RegInfo);
+ RC, &RegInfo);
}
}
generated by cgit v1.1 at 2025-08-18 02:35:57 +0000