diff options
Diffstat (limited to 'lib/Target/Mips')
113 files changed, 5841 insertions, 3049 deletions
diff --git a/lib/Target/Mips/Android.mk b/lib/Target/Mips/Android.mk index 9f437f8..18d1177 100644 --- a/lib/Target/Mips/Android.mk +++ b/lib/Target/Mips/Android.mk @@ -20,9 +20,10 @@ mips_codegen_SRC_FILES := \ Mips16ISelLowering.cpp \ Mips16InstrInfo.cpp \ Mips16RegisterInfo.cpp \ + MipsABIInfo.cpp \ MipsAnalyzeImmediate.cpp \ MipsAsmPrinter.cpp \ - MipsCodeEmitter.cpp \ + MipsCCState.cpp \ MipsConstantIslandPass.cpp \ MipsDelaySlotFiller.cpp \ MipsFastISel.cpp \ @@ -30,7 +31,6 @@ mips_codegen_SRC_FILES := \ MipsInstrInfo.cpp \ MipsISelDAGToDAG.cpp \ MipsISelLowering.cpp \ - MipsJITInfo.cpp \ MipsLongBranch.cpp \ MipsMachineFunction.cpp \ MipsMCInstLower.cpp \ diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 0c06be8..0c5b41f 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -13,6 +13,7 @@ #include "MipsTargetStreamer.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/StringSwitch.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -26,6 +27,8 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/SourceMgr.h" +#include <memory> using namespace llvm; @@ -38,36 +41,69 @@ class MCInstrInfo; namespace { class MipsAssemblerOptions { public: - MipsAssemblerOptions() : aTReg(1), reorder(true), macro(true) {} + MipsAssemblerOptions(uint64_t Features_) : + ATReg(1), Reorder(true), Macro(true), Features(Features_) {} - unsigned getATRegNum() { return aTReg; } - bool setATReg(unsigned Reg); + MipsAssemblerOptions(const MipsAssemblerOptions *Opts) { + ATReg = Opts->getATRegNum(); + Reorder = Opts->isReorder(); + Macro = Opts->isMacro(); + Features = Opts->getFeatures(); + } - bool isReorder() { return reorder; } - void setReorder() { reorder = true; } - void setNoreorder() { reorder = false; } + unsigned getATRegNum() const { return ATReg; } + bool setATReg(unsigned Reg); - bool isMacro() { return macro; } - void setMacro() { macro = true; } - void setNomacro() { macro = false; } + bool isReorder() const { return Reorder; } + void setReorder() { Reorder = true; } + void setNoReorder() { Reorder = false; } + + bool isMacro() const { return Macro; } + void setMacro() { Macro = true; } + void setNoMacro() { Macro = false; } + + uint64_t getFeatures() const { return Features; } + void setFeatures(uint64_t Features_) { Features = Features_; } + + // Set of features that are either architecture features or referenced + // by them (e.g.: FeatureNaN2008 implied by FeatureMips32r6). + // The full table can be found in MipsGenSubtargetInfo.inc (MipsFeatureKV[]). + // The reason we need this mask is explained in the selectArch function. + // FIXME: Ideally we would like TableGen to generate this information. + static const uint64_t AllArchRelatedMask = + Mips::FeatureMips1 | Mips::FeatureMips2 | Mips::FeatureMips3 | + Mips::FeatureMips3_32 | Mips::FeatureMips3_32r2 | Mips::FeatureMips4 | + Mips::FeatureMips4_32 | Mips::FeatureMips4_32r2 | Mips::FeatureMips5 | + Mips::FeatureMips5_32r2 | Mips::FeatureMips32 | Mips::FeatureMips32r2 | + Mips::FeatureMips32r6 | Mips::FeatureMips64 | Mips::FeatureMips64r2 | + Mips::FeatureMips64r6 | Mips::FeatureCnMips | Mips::FeatureFP64Bit | + Mips::FeatureGP64Bit | Mips::FeatureNaN2008; private: - unsigned aTReg; - bool reorder; - bool macro; + unsigned ATReg; + bool Reorder; + bool Macro; + uint64_t Features; }; } namespace { class MipsAsmParser : public MCTargetAsmParser { MipsTargetStreamer &getTargetStreamer() { - MCTargetStreamer &TS = *Parser.getStreamer().getTargetStreamer(); + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); return static_cast<MipsTargetStreamer &>(TS); } MCSubtargetInfo &STI; - MCAsmParser &Parser; - MipsAssemblerOptions Options; + SmallVector<std::unique_ptr<MipsAssemblerOptions>, 2> AssemblerOptions; + MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a + // nullptr, which indicates that no function is currently + // selected. This usually happens after an '.end func' + // directive. + + // Print a warning along with its fix-it message at the given range. + void printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg, + SMRange Range, bool ShowColors = true); #define GET_ASSEMBLER_HEADER #include "MipsGenAsmMatcher.inc" @@ -76,15 +112,15 @@ class MipsAsmParser : public MCTargetAsmParser { bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - unsigned &ErrorInfo, + uint64_t &ErrorInfo, bool MatchingInlineAsm) override; /// Parse a register as used in CFI directives bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; - bool ParseParenSuffix(StringRef Name, OperandVector &Operands); + bool parseParenSuffix(StringRef Name, OperandVector &Operands); - bool ParseBracketSuffix(StringRef Name, OperandVector &Operands); + bool parseBracketSuffix(StringRef Name, OperandVector &Operands); bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -94,25 +130,28 @@ class MipsAsmParser : public MCTargetAsmParser { MipsAsmParser::OperandMatchResultTy parseMemOperand(OperandVector &Operands); MipsAsmParser::OperandMatchResultTy - MatchAnyRegisterNameWithoutDollar(OperandVector &Operands, + matchAnyRegisterNameWithoutDollar(OperandVector &Operands, StringRef Identifier, SMLoc S); MipsAsmParser::OperandMatchResultTy - MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S); + matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S); - MipsAsmParser::OperandMatchResultTy ParseAnyRegister(OperandVector &Operands); + MipsAsmParser::OperandMatchResultTy parseAnyRegister(OperandVector &Operands); - MipsAsmParser::OperandMatchResultTy ParseImm(OperandVector &Operands); + MipsAsmParser::OperandMatchResultTy parseImm(OperandVector &Operands); - MipsAsmParser::OperandMatchResultTy ParseJumpTarget(OperandVector &Operands); + MipsAsmParser::OperandMatchResultTy parseJumpTarget(OperandVector &Operands); MipsAsmParser::OperandMatchResultTy parseInvNum(OperandVector &Operands); - MipsAsmParser::OperandMatchResultTy ParseLSAImm(OperandVector &Operands); + MipsAsmParser::OperandMatchResultTy parseLSAImm(OperandVector &Operands); + + MipsAsmParser::OperandMatchResultTy + parseRegisterList (OperandVector &Operands); bool searchSymbolAlias(OperandVector &Operands); - bool ParseOperand(OperandVector &, StringRef Mnemonic); + bool parseOperand(OperandVector &, StringRef Mnemonic); bool needsExpansion(MCInst &Inst); @@ -130,6 +169,9 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions); + void expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions); + void expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd); @@ -142,8 +184,10 @@ class MipsAsmParser : public MCTargetAsmParser { const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr); bool isEvaluated(const MCExpr *Expr); + bool parseSetMips0Directive(); + bool parseSetArchDirective(); bool parseSetFeature(uint64_t Feature); - bool parseDirectiveCPLoad(SMLoc Loc); + bool parseDirectiveCpLoad(SMLoc Loc); bool parseDirectiveCPSetup(); bool parseDirectiveNaN(); bool parseDirectiveSet(); @@ -153,10 +197,16 @@ class MipsAsmParser : public MCTargetAsmParser { bool parseSetNoAtDirective(); bool parseSetMacroDirective(); bool parseSetNoMacroDirective(); + bool parseSetMsaDirective(); + bool parseSetNoMsaDirective(); + bool parseSetNoDspDirective(); bool parseSetReorderDirective(); bool parseSetNoReorderDirective(); + bool parseSetMips16Directive(); bool parseSetNoMips16Directive(); bool parseSetFpDirective(); + bool parseSetPopDirective(); + bool parseSetPushDirective(); bool parseSetAssignment(); @@ -174,6 +224,8 @@ class MipsAsmParser : public MCTargetAsmParser { int matchCPURegisterName(StringRef Symbol); + int matchHWRegsRegisterName(StringRef Symbol); + int matchRegisterByNumber(unsigned RegNum, unsigned RegClass); int matchFPURegisterName(StringRef Name); @@ -200,18 +252,51 @@ class MipsAsmParser : public MCTargetAsmParser { // Example: INSERT.B $w0[n], $1 => 16 > n >= 0 bool validateMSAIndex(int Val, int RegKind); - void setFeatureBits(unsigned Feature, StringRef FeatureString) { + // Selects a new architecture by updating the FeatureBits with the necessary + // info including implied dependencies. + // Internally, it clears all the feature bits related to *any* architecture + // and selects the new one using the ToggleFeature functionality of the + // MCSubtargetInfo object that handles implied dependencies. The reason we + // clear all the arch related bits manually is because ToggleFeature only + // clears the features that imply the feature being cleared and not the + // features implied by the feature being cleared. This is easier to see + // with an example: + // -------------------------------------------------- + // | Feature | Implies | + // | -------------------------------------------------| + // | FeatureMips1 | None | + // | FeatureMips2 | FeatureMips1 | + // | FeatureMips3 | FeatureMips2 | FeatureMipsGP64 | + // | FeatureMips4 | FeatureMips3 | + // | ... | | + // -------------------------------------------------- + // + // Setting Mips3 is equivalent to set: (FeatureMips3 | FeatureMips2 | + // FeatureMipsGP64 | FeatureMips1) + // Clearing Mips3 is equivalent to clear (FeatureMips3 | FeatureMips4). + void selectArch(StringRef ArchFeature) { + uint64_t FeatureBits = STI.getFeatureBits(); + FeatureBits &= ~MipsAssemblerOptions::AllArchRelatedMask; + STI.setFeatureBits(FeatureBits); + setAvailableFeatures( + ComputeAvailableFeatures(STI.ToggleFeature(ArchFeature))); + AssemblerOptions.back()->setFeatures(getAvailableFeatures()); + } + + void setFeatureBits(uint64_t Feature, StringRef FeatureString) { if (!(STI.getFeatureBits() & Feature)) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } + AssemblerOptions.back()->setFeatures(getAvailableFeatures()); } - void clearFeatureBits(unsigned Feature, StringRef FeatureString) { + void clearFeatureBits(uint64_t Feature, StringRef FeatureString) { if (STI.getFeatureBits() & Feature) { setAvailableFeatures( ComputeAvailableFeatures(STI.ToggleFeature(FeatureString))); } + AssemblerOptions.back()->setFeatures(getAvailableFeatures()); } public: @@ -225,9 +310,19 @@ public: MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser, const MCInstrInfo &MII, const MCTargetOptions &Options) - : MCTargetAsmParser(), STI(sti), Parser(parser) { + : MCTargetAsmParser(), STI(sti) { + MCAsmParserExtension::Initialize(parser); + // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); + + // Remember the initial assembler options. The user can not modify these. + AssemblerOptions.push_back( + make_unique<MipsAssemblerOptions>(getAvailableFeatures())); + + // Create an assembler options environment for the user to modify. + AssemblerOptions.push_back( + make_unique<MipsAssemblerOptions>(getAvailableFeatures())); getTargetStreamer().updateABIInfo(*this); @@ -237,12 +332,11 @@ public: ((STI.getFeatureBits() & Mips::FeatureN32) != 0) + ((STI.getFeatureBits() & Mips::FeatureN64) != 0)) == 1); - if (!isABI_O32() && !allowOddSPReg() != 0) + if (!isABI_O32() && !useOddSPReg() != 0) report_fatal_error("-mno-odd-spreg requires the O32 ABI"); - } - MCAsmParser &getParser() const { return Parser; } - MCAsmLexer &getLexer() const { return Parser.getLexer(); } + CurrentFn = nullptr; + } /// True if all of $fcc0 - $fcc7 exist for the current ISA. bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); } @@ -252,9 +346,9 @@ public: bool isABI_N32() const { return STI.getFeatureBits() & Mips::FeatureN32; } bool isABI_N64() const { return STI.getFeatureBits() & Mips::FeatureN64; } bool isABI_O32() const { return STI.getFeatureBits() & Mips::FeatureO32; } - bool isABI_FPXX() const { return false; } // TODO: add check for FeatureXX + bool isABI_FPXX() const { return STI.getFeatureBits() & Mips::FeatureFPXX; } - bool allowOddSPReg() const { + bool useOddSPReg() const { return !(STI.getFeatureBits() & Mips::FeatureNoOddSPReg); } @@ -292,10 +386,10 @@ public: return STI.getFeatureBits() & Mips::FeatureMips16; } // TODO: see how can we get this info. - bool mipsSEUsesSoftFloat() const { return false; } + bool abiUsesSoftFloat() const { return false; } /// Warn if RegNo is the current assembler temporary. - void WarnIfAssemblerTemporary(int RegNo, SMLoc Loc); + void warnIfAssemblerTemporary(int RegNo, SMLoc Loc); }; } @@ -333,7 +427,8 @@ private: k_Memory, /// Base + Offset Memory Address k_PhysRegister, /// A physical register from the Mips namespace k_RegisterIndex, /// A register index in one or more RegKind. - k_Token /// A simple token + k_Token, /// A simple token + k_RegList /// A physical register list } Kind; public: @@ -368,12 +463,17 @@ private: const MCExpr *Off; }; + struct RegListOp { + SmallVector<unsigned, 10> *List; + }; + union { struct Token Tok; struct PhysRegOp PhysReg; struct RegIdxOp RegIdx; struct ImmOp Imm; struct MemOp Mem; + struct RegListOp RegList; }; SMLoc StartLoc, EndLoc; @@ -397,7 +497,15 @@ public: /// target. unsigned getGPR32Reg() const { assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); - AsmParser.WarnIfAssemblerTemporary(RegIdx.Index, StartLoc); + AsmParser.warnIfAssemblerTemporary(RegIdx.Index, StartLoc); + unsigned ClassID = Mips::GPR32RegClassID; + return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); + } + + /// Coerce the register to GPR32 and return the real register for the current + /// target. + unsigned getGPRMM16Reg() const { + assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); unsigned ClassID = Mips::GPR32RegClassID; return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); } @@ -550,6 +658,11 @@ public: Inst.addOperand(MCOperand::CreateReg(getGPR32Reg())); } + void addGPRMM16AsmRegOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + Inst.addOperand(MCOperand::CreateReg(getGPRMM16Reg())); + } + /// Render the operand to an MCInst as a GPR64 /// Asserts if the wrong number of operands are requested, or the operand /// is not a k_RegisterIndex compatible with RegKind_GPR @@ -572,7 +685,7 @@ public: assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateReg(getFGR32Reg())); // FIXME: We ought to do this for -integrated-as without -via-file-asm too. - if (!AsmParser.allowOddSPReg() && RegIdx.Index & 1) + if (!AsmParser.useOddSPReg() && RegIdx.Index & 1) AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " "registers"); } @@ -647,6 +760,13 @@ public: addExpr(Inst, Expr); } + void addRegListOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + + for (auto RegNo : getRegList()) + Inst.addOperand(MCOperand::CreateReg(RegNo)); + } + bool isReg() const override { // As a special case until we sort out the definition of div/divu, pretend // that $0/$zero are k_PhysRegister so that MCK_ZERO works correctly. @@ -679,6 +799,7 @@ public: int64_t Val = getConstantImm(); return 1 <= Val && Val <= 4; } + bool isRegList() const { return Kind == k_RegList; } StringRef getToken() const { assert(Kind == k_Token && "Invalid access!"); @@ -720,6 +841,11 @@ public: return static_cast<const MCConstantExpr *>(getMemOff())->getValue(); } + const SmallVectorImpl<unsigned> &getRegList() const { + assert((Kind == k_RegList) && "Invalid access!"); + return *(RegList.List); + } + static std::unique_ptr<MipsOperand> CreateToken(StringRef Str, SMLoc S, MipsAsmParser &Parser) { auto Op = make_unique<MipsOperand>(k_Token, Parser); @@ -733,16 +859,16 @@ public: /// Create a numeric register (e.g. $1). The exact register remains /// unresolved until an instruction successfully matches static std::unique_ptr<MipsOperand> - CreateNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, + createNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { - DEBUG(dbgs() << "CreateNumericReg(" << Index << ", ...)\n"); + DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n"); return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser); } /// Create a register that is definitely a GPR. /// This is typically only used for named registers such as $gp. static std::unique_ptr<MipsOperand> - CreateGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, + createGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser); } @@ -750,15 +876,23 @@ public: /// Create a register that is definitely a FGR. /// This is typically only used for named registers such as $f0. static std::unique_ptr<MipsOperand> - CreateFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, + createFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser); } + /// Create a register that is definitely a HWReg. + /// This is typically only used for named registers such as $hwr_cpunum. + static std::unique_ptr<MipsOperand> + createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser); + } + /// Create a register that is definitely an FCC. /// This is typically only used for named registers such as $fcc0. static std::unique_ptr<MipsOperand> - CreateFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, + createFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser); } @@ -766,7 +900,7 @@ public: /// Create a register that is definitely an ACC. /// This is typically only used for named registers such as $ac0. static std::unique_ptr<MipsOperand> - CreateACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, + createACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser); } @@ -774,7 +908,7 @@ public: /// Create a register that is definitely an MSA128. /// This is typically only used for named registers such as $w0. static std::unique_ptr<MipsOperand> - CreateMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, + createMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser); } @@ -782,7 +916,7 @@ public: /// Create a register that is definitely an MSACtrl. /// This is typically only used for named registers such as $msaaccess. static std::unique_ptr<MipsOperand> - CreateMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, + createMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser); } @@ -807,9 +941,29 @@ public: return Op; } + static std::unique_ptr<MipsOperand> + CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, + MipsAsmParser &Parser) { + assert (Regs.size() > 0 && "Empty list not allowed"); + + auto Op = make_unique<MipsOperand>(k_RegList, Parser); + Op->RegList.List = new SmallVector<unsigned, 10>(); + for (auto Reg : Regs) + Op->RegList.List->push_back(Reg); + Op->StartLoc = StartLoc; + Op->EndLoc = EndLoc; + return Op; + } + bool isGPRAsmReg() const { return isRegIdx() && RegIdx.Kind & RegKind_GPR && RegIdx.Index <= 31; } + bool isMM16AsmReg() const { + if (!(isRegIdx() && RegIdx.Kind)) + return false; + return ((RegIdx.Index >= 2 && RegIdx.Index <= 7) + || RegIdx.Index == 16 || RegIdx.Index == 17); + } bool isFGRAsmReg() const { // AFGR64 is $0-$15 but we handle this in getAFGR64() return isRegIdx() && RegIdx.Kind & RegKind_FGR && RegIdx.Index <= 31; @@ -855,6 +1009,8 @@ public: case k_Memory: delete Mem.Base; break; + case k_RegList: + delete RegList.List; case k_PhysRegister: case k_RegisterIndex: case k_Token: @@ -885,6 +1041,12 @@ public: case k_Token: OS << Tok.Data; break; + case k_RegList: + OS << "RegList< "; + for (auto Reg : (*RegList.List)) + OS << Reg << " "; + OS << ">"; + break; } } }; // class MipsOperand @@ -897,6 +1059,19 @@ static const MCInstrDesc &getInstDesc(unsigned Opcode) { return MipsInsts[Opcode]; } +static bool hasShortDelaySlot(unsigned Opcode) { + switch (Opcode) { + case Mips::JALS_MM: + case Mips::JALRS_MM: + case Mips::JALRS16_MM: + case Mips::BGEZALS_MM: + case Mips::BLTZALS_MM: + return true; + default: + return false; + } +} + bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); @@ -961,15 +1136,21 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, "nop instruction"); } - if (MCID.hasDelaySlot() && Options.isReorder()) { + if (MCID.hasDelaySlot() && AssemblerOptions.back()->isReorder()) { // If this instruction has a delay slot and .set reorder is active, // emit a NOP after it. Instructions.push_back(Inst); MCInst NopInst; - NopInst.setOpcode(Mips::SLL); - NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); - NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); - NopInst.addOperand(MCOperand::CreateImm(0)); + if (hasShortDelaySlot(Inst.getOpcode())) { + NopInst.setOpcode(Mips::MOVE16_MM); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + } else { + NopInst.setOpcode(Mips::SLL); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + NopInst.addOperand(MCOperand::CreateReg(Mips::ZERO)); + NopInst.addOperand(MCOperand::CreateImm(0)); + } Instructions.push_back(NopInst); return false; } @@ -1008,6 +1189,80 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } // for } // if load/store + // TODO: Handle this with the AsmOperandClass.PredicateMethod. + if (inMicroMipsMode()) { + MCOperand Opnd; + int Imm; + + switch (Inst.getOpcode()) { + default: + break; + case Mips::ADDIUS5_MM: + Opnd = Inst.getOperand(2); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (Imm < -8 || Imm > 7) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::ADDIUSP_MM: + Opnd = Inst.getOperand(0); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (Imm < -1032 || Imm > 1028 || (Imm < 8 && Imm > -12) || + Imm % 4 != 0) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::SLL16_MM: + case Mips::SRL16_MM: + Opnd = Inst.getOperand(2); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (Imm < 1 || Imm > 8) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::LI16_MM: + Opnd = Inst.getOperand(1); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (Imm < -1 || Imm > 126) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::ADDIUR2_MM: + Opnd = Inst.getOperand(2); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (!(Imm == 1 || Imm == -1 || + ((Imm % 4 == 0) && Imm < 28 && Imm > 0))) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::ADDIUR1SP_MM: + Opnd = Inst.getOperand(1); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (OffsetToAlignment(Imm, 4LL)) + return Error(IDLoc, "misaligned immediate operand value"); + if (Imm < 0 || Imm > 255) + return Error(IDLoc, "immediate operand value out of range"); + break; + case Mips::ANDI16_MM: + Opnd = Inst.getOperand(2); + if (!Opnd.isImm()) + return Error(IDLoc, "expected immediate operand kind"); + Imm = Opnd.getImm(); + if (!(Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || + Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || + Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535)) + return Error(IDLoc, "immediate operand value out of range"); + break; + } + } + if (needsExpansion(Inst)) return expandInstruction(Inst, IDLoc, Instructions); else @@ -1039,7 +1294,7 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc, return expandLoadImm(Inst, IDLoc, Instructions); case Mips::LoadImm64Reg: if (!isGP64bit()) { - Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + Error(IDLoc, "instruction requires a 64-bit architecture"); return true; } return expandLoadImm(Inst, IDLoc, Instructions); @@ -1051,8 +1306,8 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc, } namespace { -template <int Shift, bool PerformShift> -void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc, +template <bool PerformShift> +void createShiftOr(MCOperand Operand, unsigned RegNo, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { MCInst tmpInst; if (PerformShift) { @@ -1067,11 +1322,18 @@ void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc, tmpInst.setOpcode(Mips::ORi); tmpInst.addOperand(MCOperand::CreateReg(RegNo)); tmpInst.addOperand(MCOperand::CreateReg(RegNo)); - tmpInst.addOperand( - MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift))); + tmpInst.addOperand(Operand); tmpInst.setLoc(IDLoc); Instructions.push_back(tmpInst); } + +template <int Shift, bool PerformShift> +void createShiftOr(int64_t Value, unsigned RegNo, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions) { + createShiftOr<PerformShift>( + MCOperand::CreateImm(((Value & (0xffffLL << Shift)) >> Shift)), RegNo, + IDLoc, Instructions); +} } bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc, @@ -1114,7 +1376,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc, createShiftOr<0, false>(ImmValue, RegOp.getReg(), IDLoc, Instructions); } else if ((ImmValue & (0xffffLL << 48)) == 0) { if (!isGP64bit()) { - Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + Error(IDLoc, "instruction requires a 64-bit architecture"); return true; } @@ -1141,7 +1403,7 @@ bool MipsAsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc, createShiftOr<0, true>(ImmValue, RegOp.getReg(), IDLoc, Instructions); } else { if (!isGP64bit()) { - Error(IDLoc, "instruction requires a CPU feature not currently enabled"); + Error(IDLoc, "instruction requires a 64-bit architecture"); return true; } @@ -1176,7 +1438,12 @@ MipsAsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { MCInst tmpInst; const MCOperand &ImmOp = Inst.getOperand(2); - assert(ImmOp.isImm() && "expected immediate operand kind"); + assert((ImmOp.isImm() || ImmOp.isExpr()) && + "expected immediate operand kind"); + if (!ImmOp.isImm()) { + expandLoadAddressSym(Inst, IDLoc, Instructions); + return false; + } const MCOperand &SrcRegOp = Inst.getOperand(1); assert(SrcRegOp.isReg() && "expected register operand kind"); const MCOperand &DstRegOp = Inst.getOperand(0); @@ -1220,7 +1487,12 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions) { MCInst tmpInst; const MCOperand &ImmOp = Inst.getOperand(1); - assert(ImmOp.isImm() && "expected immediate operand kind"); + assert((ImmOp.isImm() || ImmOp.isExpr()) && + "expected immediate operand kind"); + if (!ImmOp.isImm()) { + expandLoadAddressSym(Inst, IDLoc, Instructions); + return false; + } const MCOperand &RegOp = Inst.getOperand(0); assert(RegOp.isReg() && "expected register operand kind"); int ImmValue = ImmOp.getImm(); @@ -1250,6 +1522,71 @@ MipsAsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc, return false; } +void +MipsAsmParser::expandLoadAddressSym(MCInst &Inst, SMLoc IDLoc, + SmallVectorImpl<MCInst> &Instructions) { + // FIXME: If we do have a valid at register to use, we should generate a + // slightly shorter sequence here. + MCInst tmpInst; + int ExprOperandNo = 1; + // Sometimes the assembly parser will get the immediate expression as + // a $zero + an immediate. + if (Inst.getNumOperands() == 3) { + assert(Inst.getOperand(1).getReg() == + (isGP64bit() ? Mips::ZERO_64 : Mips::ZERO)); + ExprOperandNo = 2; + } + const MCOperand &SymOp = Inst.getOperand(ExprOperandNo); + assert(SymOp.isExpr() && "expected symbol operand kind"); + const MCOperand &RegOp = Inst.getOperand(0); + unsigned RegNo = RegOp.getReg(); + const MCSymbolRefExpr *Symbol = cast<MCSymbolRefExpr>(SymOp.getExpr()); + const MCSymbolRefExpr *HiExpr = + MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), + MCSymbolRefExpr::VK_Mips_ABS_HI, getContext()); + const MCSymbolRefExpr *LoExpr = + MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), + MCSymbolRefExpr::VK_Mips_ABS_LO, getContext()); + if (isGP64bit()) { + // If it's a 64-bit architecture, expand to: + // la d,sym => lui d,highest(sym) + // ori d,d,higher(sym) + // dsll d,d,16 + // ori d,d,hi16(sym) + // dsll d,d,16 + // ori d,d,lo16(sym) + const MCSymbolRefExpr *HighestExpr = + MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), + MCSymbolRefExpr::VK_Mips_HIGHEST, getContext()); + const MCSymbolRefExpr *HigherExpr = + MCSymbolRefExpr::Create(Symbol->getSymbol().getName(), + MCSymbolRefExpr::VK_Mips_HIGHER, getContext()); + + tmpInst.setOpcode(Mips::LUi); + tmpInst.addOperand(MCOperand::CreateReg(RegNo)); + tmpInst.addOperand(MCOperand::CreateExpr(HighestExpr)); + Instructions.push_back(tmpInst); + + createShiftOr<false>(MCOperand::CreateExpr(HigherExpr), RegNo, SMLoc(), + Instructions); + createShiftOr<true>(MCOperand::CreateExpr(HiExpr), RegNo, SMLoc(), + Instructions); + createShiftOr<true>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(), + Instructions); + } else { + // Otherwise, expand to: + // la d,sym => lui d,hi16(sym) + // ori d,d,lo16(sym) + tmpInst.setOpcode(Mips::LUi); + tmpInst.addOperand(MCOperand::CreateReg(RegNo)); + tmpInst.addOperand(MCOperand::CreateExpr(HiExpr)); + Instructions.push_back(tmpInst); + + createShiftOr<false>(MCOperand::CreateExpr(LoExpr), RegNo, SMLoc(), + Instructions); + } +} + void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc, SmallVectorImpl<MCInst> &Instructions, bool isLoad, bool isImmOpnd) { @@ -1381,7 +1718,7 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - unsigned &ErrorInfo, + uint64_t &ErrorInfo, bool MatchingInlineAsm) { MCInst Inst; @@ -1404,7 +1741,7 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return true; case Match_InvalidOperand: { SMLoc ErrorLoc = IDLoc; - if (ErrorInfo != ~0U) { + if (ErrorInfo != ~0ULL) { if (ErrorInfo >= Operands.size()) return Error(IDLoc, "too few operands for instruction"); @@ -1423,16 +1760,25 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return true; } -void MipsAsmParser::WarnIfAssemblerTemporary(int RegIndex, SMLoc Loc) { - if ((RegIndex != 0) && ((int)Options.getATRegNum() == RegIndex)) { +void MipsAsmParser::warnIfAssemblerTemporary(int RegIndex, SMLoc Loc) { + if ((RegIndex != 0) && + ((int)AssemblerOptions.back()->getATRegNum() == RegIndex)) { if (RegIndex == 1) - Warning(Loc, "Used $at without \".set noat\""); + Warning(Loc, "used $at without \".set noat\""); else - Warning(Loc, Twine("Used $") + Twine(RegIndex) + " with \".set at=$" + + Warning(Loc, Twine("used $") + Twine(RegIndex) + " with \".set at=$" + Twine(RegIndex) + "\""); } } +void +MipsAsmParser::printWarningWithFixIt(const Twine &Msg, const Twine &FixMsg, + SMRange Range, bool ShowColors) { + getSourceManager().PrintMessage(Range.Start, SourceMgr::DK_Warning, Msg, + Range, SMFixIt(Range, FixMsg), + ShowColors); +} + int MipsAsmParser::matchCPURegisterName(StringRef Name) { int CC; @@ -1472,23 +1818,55 @@ int MipsAsmParser::matchCPURegisterName(StringRef Name) { .Case("t9", 25) .Default(-1); - if (isABI_N32() || isABI_N64()) { - // Although SGI documentation just cuts out t0-t3 for n32/n64, - // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7 - // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7. - if (8 <= CC && CC <= 11) - CC += 4; + if (!(isABI_N32() || isABI_N64())) + return CC; + + if (12 <= CC && CC <= 15) { + // Name is one of t4-t7 + AsmToken RegTok = getLexer().peekTok(); + SMRange RegRange = RegTok.getLocRange(); + + StringRef FixedName = StringSwitch<StringRef>(Name) + .Case("t4", "t0") + .Case("t5", "t1") + .Case("t6", "t2") + .Case("t7", "t3") + .Default(""); + assert(FixedName != "" && "Register name is not one of t4-t7."); + + printWarningWithFixIt("register names $t4-$t7 are only available in O32.", + "Did you mean $" + FixedName + "?", RegRange); + } + + // Although SGI documentation just cuts out t0-t3 for n32/n64, + // GNU pushes the values of t0-t3 to override the o32/o64 values for t4-t7 + // We are supporting both cases, so for t0-t3 we'll just push them to t4-t7. + if (8 <= CC && CC <= 11) + CC += 4; + + if (CC == -1) + CC = StringSwitch<unsigned>(Name) + .Case("a4", 8) + .Case("a5", 9) + .Case("a6", 10) + .Case("a7", 11) + .Case("kt0", 26) + .Case("kt1", 27) + .Default(-1); - if (CC == -1) - CC = StringSwitch<unsigned>(Name) - .Case("a4", 8) - .Case("a5", 9) - .Case("a6", 10) - .Case("a7", 11) - .Case("kt0", 26) - .Case("kt1", 27) - .Default(-1); - } + return CC; +} + +int MipsAsmParser::matchHWRegsRegisterName(StringRef Name) { + int CC; + + CC = StringSwitch<unsigned>(Name) + .Case("hwr_cpunum", 0) + .Case("hwr_synci_step", 1) + .Case("hwr_cc", 2) + .Case("hwr_ccres", 3) + .Case("hwr_ulr", 29) + .Default(-1); return CC; } @@ -1568,15 +1946,15 @@ bool MipsAssemblerOptions::setATReg(unsigned Reg) { if (Reg > 31) return false; - aTReg = Reg; + ATReg = Reg; return true; } int MipsAsmParser::getATReg(SMLoc Loc) { - int AT = Options.getATRegNum(); + int AT = AssemblerOptions.back()->getATRegNum(); if (AT == 0) reportParseError(Loc, - "Pseudo instruction requires $at, which is not available"); + "pseudo-instruction requires $at, which is not available"); return AT; } @@ -1597,8 +1975,9 @@ int MipsAsmParser::matchRegisterByNumber(unsigned RegNum, unsigned RegClass) { return getReg(RegClass, RegNum); } -bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) { - DEBUG(dbgs() << "ParseOperand\n"); +bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { + MCAsmParser &Parser = getParser(); + DEBUG(dbgs() << "parseOperand\n"); // Check if the current operand has a custom associated parser, if so, try to // custom parse the operand, or fallback to the general approach. @@ -1626,7 +2005,7 @@ bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) { // for div, divu, and similar instructions because it is not an operand // to the instruction definition but an explicit register. Special case // this situation for now. - if (ParseAnyRegister(Operands) != MatchOperand_NoMatch) + if (parseAnyRegister(Operands) != MatchOperand_NoMatch) return false; // Maybe it is a symbol reference. @@ -1651,7 +2030,7 @@ bool MipsAsmParser::ParseOperand(OperandVector &Operands, StringRef Mnemonic) { case AsmToken::Tilde: case AsmToken::String: { DEBUG(dbgs() << ".. generic integer\n"); - OperandMatchResultTy ResTy = ParseImm(Operands); + OperandMatchResultTy ResTy = parseImm(Operands); return ResTy != MatchOperand_Success; } case AsmToken::Percent: { @@ -1696,7 +2075,7 @@ const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr, Val = ((MCE->getValue() + 0x800080008000LL) >> 48) & 0xffff; break; default: - report_fatal_error("Unsupported reloc value!"); + report_fatal_error("unsupported reloc value"); } return MCConstantExpr::Create(Val, getContext()); } @@ -1753,6 +2132,7 @@ bool MipsAsmParser::isEvaluated(const MCExpr *Expr) { } bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) { + MCAsmParser &Parser = getParser(); Parser.Lex(); // Eat the % token. const AsmToken &Tok = Parser.getTok(); // Get next token, operation. if (Tok.isNot(AsmToken::Identifier)) @@ -1797,7 +2177,7 @@ bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) { bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; - OperandMatchResultTy ResTy = ParseAnyRegister(Operands); + OperandMatchResultTy ResTy = parseAnyRegister(Operands); if (ResTy == MatchOperand_Success) { assert(Operands.size() == 1); MipsOperand &Operand = static_cast<MipsOperand &>(*Operands.front()); @@ -1821,6 +2201,7 @@ bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, } bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { + MCAsmParser &Parser = getParser(); SMLoc S; bool Result = true; @@ -1850,6 +2231,7 @@ bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseMemOperand(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseMemOperand\n"); const MCExpr *IdVal = nullptr; SMLoc S; @@ -1882,7 +2264,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) { // Zero register assumed, add a memory operand with ZERO as its base. // "Base" will be managed by k_Memory. - auto Base = MipsOperand::CreateGPRReg(0, getContext().getRegisterInfo(), + auto Base = MipsOperand::createGPRReg(0, getContext().getRegisterInfo(), S, E, *this); Operands.push_back( MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this)); @@ -1895,7 +2277,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) { Parser.Lex(); // Eat the '(' token. } - Res = ParseAnyRegister(Operands); + Res = parseAnyRegister(Operands); if (Res != MatchOperand_Success) return Res; @@ -1932,7 +2314,7 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) { } bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { - + MCAsmParser &Parser = getParser(); MCSymbol *Sym = getContext().LookupSymbol(Parser.getTok().getIdentifier()); if (Sym) { SMLoc S = Parser.getTok().getLoc(); @@ -1943,10 +2325,10 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { return false; if (Expr->getKind() == MCExpr::SymbolRef) { const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr *>(Expr); - const StringRef DefSymbol = Ref->getSymbol().getName(); + StringRef DefSymbol = Ref->getSymbol().getName(); if (DefSymbol.startswith("$")) { OperandMatchResultTy ResTy = - MatchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S); + matchAnyRegisterNameWithoutDollar(Operands, DefSymbol.substr(1), S); if (ResTy == MatchOperand_Success) { Parser.Lex(); return true; @@ -1966,47 +2348,54 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands, +MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands, StringRef Identifier, SMLoc S) { int Index = matchCPURegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateGPRReg( + Operands.push_back(MipsOperand::createGPRReg( + Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + return MatchOperand_Success; + } + + Index = matchHWRegsRegisterName(Identifier); + if (Index != -1) { + Operands.push_back(MipsOperand::createHWRegsReg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchFPURegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateFGRReg( + Operands.push_back(MipsOperand::createFGRReg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchFCCRegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateFCCReg( + Operands.push_back(MipsOperand::createFCCReg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchACRegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateACCReg( + Operands.push_back(MipsOperand::createACCReg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchMSA128RegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateMSA128Reg( + Operands.push_back(MipsOperand::createMSA128Reg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchMSA128CtrlRegisterName(Identifier); if (Index != -1) { - Operands.push_back(MipsOperand::CreateMSACtrlReg( + Operands.push_back(MipsOperand::createMSACtrlReg( Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); return MatchOperand_Success; } @@ -2015,18 +2404,19 @@ MipsAsmParser::MatchAnyRegisterNameWithoutDollar(OperandVector &Operands, } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { +MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { + MCAsmParser &Parser = getParser(); auto Token = Parser.getLexer().peekTok(false); if (Token.is(AsmToken::Identifier)) { DEBUG(dbgs() << ".. identifier\n"); StringRef Identifier = Token.getIdentifier(); OperandMatchResultTy ResTy = - MatchAnyRegisterNameWithoutDollar(Operands, Identifier, S); + matchAnyRegisterNameWithoutDollar(Operands, Identifier, S); return ResTy; } else if (Token.is(AsmToken::Integer)) { DEBUG(dbgs() << ".. integer\n"); - Operands.push_back(MipsOperand::CreateNumericReg( + Operands.push_back(MipsOperand::createNumericReg( Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(), *this)); return MatchOperand_Success; @@ -2038,8 +2428,9 @@ MipsAsmParser::MatchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::ParseAnyRegister(OperandVector &Operands) { - DEBUG(dbgs() << "ParseAnyRegister\n"); +MipsAsmParser::parseAnyRegister(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + DEBUG(dbgs() << "parseAnyRegister\n"); auto Token = Parser.getTok(); @@ -2056,7 +2447,7 @@ MipsAsmParser::ParseAnyRegister(OperandVector &Operands) { } DEBUG(dbgs() << ".. $\n"); - OperandMatchResultTy ResTy = MatchAnyRegisterWithoutDollar(Operands, S); + OperandMatchResultTy ResTy = matchAnyRegisterWithoutDollar(Operands, S); if (ResTy == MatchOperand_Success) { Parser.Lex(); // $ Parser.Lex(); // identifier @@ -2065,7 +2456,8 @@ MipsAsmParser::ParseAnyRegister(OperandVector &Operands) { } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::ParseImm(OperandVector &Operands) { +MipsAsmParser::parseImm(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); switch (getLexer().getKind()) { default: return MatchOperand_NoMatch; @@ -2089,18 +2481,19 @@ MipsAsmParser::ParseImm(OperandVector &Operands) { } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::ParseJumpTarget(OperandVector &Operands) { - DEBUG(dbgs() << "ParseJumpTarget\n"); +MipsAsmParser::parseJumpTarget(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + DEBUG(dbgs() << "parseJumpTarget\n"); SMLoc S = getLexer().getLoc(); // Integers and expressions are acceptable - OperandMatchResultTy ResTy = ParseImm(Operands); + OperandMatchResultTy ResTy = parseImm(Operands); if (ResTy != MatchOperand_NoMatch) return ResTy; // Registers are a valid target and have priority over symbols. - ResTy = ParseAnyRegister(Operands); + ResTy = parseAnyRegister(Operands); if (ResTy != MatchOperand_NoMatch) return ResTy; @@ -2116,6 +2509,7 @@ MipsAsmParser::ParseJumpTarget(OperandVector &Operands) { MipsAsmParser::OperandMatchResultTy MipsAsmParser::parseInvNum(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); const MCExpr *IdVal; // If the first token is '$' we may have register operand. if (Parser.getTok().is(AsmToken::Dollar)) @@ -2133,7 +2527,8 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) { } MipsAsmParser::OperandMatchResultTy -MipsAsmParser::ParseLSAImm(OperandVector &Operands) { +MipsAsmParser::parseLSAImm(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); switch (getLexer().getKind()) { default: return MatchOperand_NoMatch; @@ -2171,6 +2566,82 @@ MipsAsmParser::ParseLSAImm(OperandVector &Operands) { return MatchOperand_Success; } +MipsAsmParser::OperandMatchResultTy +MipsAsmParser::parseRegisterList(OperandVector &Operands) { + MCAsmParser &Parser = getParser(); + SmallVector<unsigned, 10> Regs; + unsigned RegNo; + unsigned PrevReg = Mips::NoRegister; + bool RegRange = false; + SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands; + + if (Parser.getTok().isNot(AsmToken::Dollar)) + return MatchOperand_ParseFail; + + SMLoc S = Parser.getTok().getLoc(); + while (parseAnyRegister(TmpOperands) == MatchOperand_Success) { + SMLoc E = getLexer().getLoc(); + MipsOperand &Reg = static_cast<MipsOperand &>(*TmpOperands.back()); + RegNo = isGP64bit() ? Reg.getGPR64Reg() : Reg.getGPR32Reg(); + if (RegRange) { + // Remove last register operand because registers from register range + // should be inserted first. + if (RegNo == Mips::RA) { + Regs.push_back(RegNo); + } else { + unsigned TmpReg = PrevReg + 1; + while (TmpReg <= RegNo) { + if ((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) { + Error(E, "invalid register operand"); + return MatchOperand_ParseFail; + } + + PrevReg = TmpReg; + Regs.push_back(TmpReg++); + } + } + + RegRange = false; + } else { + if ((PrevReg == Mips::NoRegister) && (RegNo != Mips::S0) && + (RegNo != Mips::RA)) { + Error(E, "$16 or $31 expected"); + return MatchOperand_ParseFail; + } else if (((RegNo < Mips::S0) || (RegNo > Mips::S7)) && + (RegNo != Mips::FP) && (RegNo != Mips::RA)) { + Error(E, "invalid register operand"); + return MatchOperand_ParseFail; + } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && + (RegNo != Mips::FP) && (RegNo != Mips::RA)) { + Error(E, "consecutive register numbers expected"); + return MatchOperand_ParseFail; + } + + Regs.push_back(RegNo); + } + + if (Parser.getTok().is(AsmToken::Minus)) + RegRange = true; + + if (!Parser.getTok().isNot(AsmToken::Minus) && + !Parser.getTok().isNot(AsmToken::Comma)) { + Error(E, "',' or '-' expected"); + return MatchOperand_ParseFail; + } + + Lex(); // Consume comma or minus + if (Parser.getTok().isNot(AsmToken::Dollar)) + break; + + PrevReg = RegNo; + } + + SMLoc E = Parser.getTok().getLoc(); + Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this)); + parseMemOperand(Operands); + return MatchOperand_Success; +} + MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) { MCSymbolRefExpr::VariantKind VK = @@ -2212,12 +2683,13 @@ MCSymbolRefExpr::VariantKind MipsAsmParser::getVariantKind(StringRef Symbol) { /// ::= '(', register, ')' /// handle it before we iterate so we don't get tripped up by the lack of /// a comma. -bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) { +bool MipsAsmParser::parseParenSuffix(StringRef Name, OperandVector &Operands) { + MCAsmParser &Parser = getParser(); if (getLexer().is(AsmToken::LParen)) { Operands.push_back( MipsOperand::CreateToken("(", getLexer().getLoc(), *this)); Parser.Lex(); - if (ParseOperand(Operands, Name)) { + if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); @@ -2240,13 +2712,14 @@ bool MipsAsmParser::ParseParenSuffix(StringRef Name, OperandVector &Operands) { /// ::= '[', integer, ']' /// handle it before we iterate so we don't get tripped up by the lack of /// a comma. -bool MipsAsmParser::ParseBracketSuffix(StringRef Name, +bool MipsAsmParser::parseBracketSuffix(StringRef Name, OperandVector &Operands) { + MCAsmParser &Parser = getParser(); if (getLexer().is(AsmToken::LBrac)) { Operands.push_back( MipsOperand::CreateToken("[", getLexer().getLoc(), *this)); Parser.Lex(); - if (ParseOperand(Operands, Name)) { + if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); @@ -2265,14 +2738,16 @@ bool MipsAsmParser::ParseBracketSuffix(StringRef Name, bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) { + MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "ParseInstruction\n"); - // We have reached first instruction, module directive after - // this is forbidden. - getTargetStreamer().setCanHaveModuleDir(false); + + // We have reached first instruction, module directive are now forbidden. + getTargetStreamer().forbidModuleDirective(); + // Check if we have valid mnemonic if (!mnemonicIsValid(Name, 0)) { Parser.eatToEndOfStatement(); - return Error(NameLoc, "Unknown instruction"); + return Error(NameLoc, "unknown instruction"); } // First operand in MCInst is instruction mnemonic. Operands.push_back(MipsOperand::CreateToken(Name, NameLoc, *this)); @@ -2280,29 +2755,29 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Read the remaining operands. if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. - if (ParseOperand(Operands, Name)) { + if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } - if (getLexer().is(AsmToken::LBrac) && ParseBracketSuffix(Name, Operands)) + if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands)) return true; // AFAIK, parenthesis suffixes are never on the first operand while (getLexer().is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. // Parse and remember the operand. - if (ParseOperand(Operands, Name)) { + if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } // Parse bracket and parenthesis suffixes before we iterate if (getLexer().is(AsmToken::LBrac)) { - if (ParseBracketSuffix(Name, Operands)) + if (parseBracketSuffix(Name, Operands)) return true; } else if (getLexer().is(AsmToken::LParen) && - ParseParenSuffix(Name, Operands)) + parseParenSuffix(Name, Operands)) return true; } } @@ -2316,6 +2791,7 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, } bool MipsAsmParser::reportParseError(Twine ErrorMsg) { + MCAsmParser &Parser = getParser(); SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); return Error(Loc, ErrorMsg); @@ -2326,14 +2802,15 @@ bool MipsAsmParser::reportParseError(SMLoc Loc, Twine ErrorMsg) { } bool MipsAsmParser::parseSetNoAtDirective() { + MCAsmParser &Parser = getParser(); // Line should look like: ".set noat". // set at reg to 0. - Options.setATReg(0); + AssemblerOptions.back()->setATReg(0); // eat noat Parser.Lex(); // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } Parser.Lex(); // Consume the EndOfStatement. @@ -2341,18 +2818,19 @@ bool MipsAsmParser::parseSetNoAtDirective() { } bool MipsAsmParser::parseSetAtDirective() { + MCAsmParser &Parser = getParser(); // Line can be .set at - defaults to $1 // or .set at=$reg int AtRegNo; getParser().Lex(); if (getLexer().is(AsmToken::EndOfStatement)) { - Options.setATReg(1); + AssemblerOptions.back()->setATReg(1); Parser.Lex(); // Consume the EndOfStatement. return false; } else if (getLexer().is(AsmToken::Equal)) { getParser().Lex(); // Eat the '='. if (getLexer().isNot(AsmToken::Dollar)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected dollar sign '$'"); return false; } Parser.Lex(); // Eat the '$'. @@ -2362,7 +2840,7 @@ bool MipsAsmParser::parseSetAtDirective() { } else if (Reg.is(AsmToken::Integer)) { AtRegNo = Reg.getIntVal(); } else { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected identifier or integer"); return false; } @@ -2371,14 +2849,14 @@ bool MipsAsmParser::parseSetAtDirective() { return false; } - if (!Options.setATReg(AtRegNo)) { - reportParseError("unexpected token in statement"); + if (!AssemblerOptions.back()->setATReg(AtRegNo)) { + reportParseError("invalid register"); return false; } getParser().Lex(); // Eat the register. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } Parser.Lex(); // Consume the EndOfStatement. @@ -2390,72 +2868,138 @@ bool MipsAsmParser::parseSetAtDirective() { } bool MipsAsmParser::parseSetReorderDirective() { + MCAsmParser &Parser = getParser(); Parser.Lex(); // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } - Options.setReorder(); + AssemblerOptions.back()->setReorder(); getTargetStreamer().emitDirectiveSetReorder(); Parser.Lex(); // Consume the EndOfStatement. return false; } bool MipsAsmParser::parseSetNoReorderDirective() { + MCAsmParser &Parser = getParser(); Parser.Lex(); // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } - Options.setNoreorder(); + AssemblerOptions.back()->setNoReorder(); getTargetStreamer().emitDirectiveSetNoReorder(); Parser.Lex(); // Consume the EndOfStatement. return false; } bool MipsAsmParser::parseSetMacroDirective() { + MCAsmParser &Parser = getParser(); Parser.Lex(); // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } - Options.setMacro(); + AssemblerOptions.back()->setMacro(); Parser.Lex(); // Consume the EndOfStatement. return false; } bool MipsAsmParser::parseSetNoMacroDirective() { + MCAsmParser &Parser = getParser(); Parser.Lex(); // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("`noreorder' must be set before `nomacro'"); + reportParseError("unexpected token, expected end of statement"); return false; } - if (Options.isReorder()) { + if (AssemblerOptions.back()->isReorder()) { reportParseError("`noreorder' must be set before `nomacro'"); return false; } - Options.setNomacro(); + AssemblerOptions.back()->setNoMacro(); Parser.Lex(); // Consume the EndOfStatement. return false; } -bool MipsAsmParser::parseSetNoMips16Directive() { +bool MipsAsmParser::parseSetMsaDirective() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) + return reportParseError("unexpected token, expected end of statement"); + + setFeatureBits(Mips::FeatureMSA, "msa"); + getTargetStreamer().emitDirectiveSetMsa(); + return false; +} + +bool MipsAsmParser::parseSetNoMsaDirective() { + MCAsmParser &Parser = getParser(); Parser.Lex(); + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) + return reportParseError("unexpected token, expected end of statement"); + + clearFeatureBits(Mips::FeatureMSA, "msa"); + getTargetStreamer().emitDirectiveSetNoMsa(); + return false; +} + +bool MipsAsmParser::parseSetNoDspDirective() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); // Eat "nodsp". + // If this is not the end of the statement, report an error. if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } - // For now do nothing. + + clearFeatureBits(Mips::FeatureDSP, "dsp"); + getTargetStreamer().emitDirectiveSetNoDsp(); + return false; +} + +bool MipsAsmParser::parseSetMips16Directive() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); // Eat "mips16". + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + setFeatureBits(Mips::FeatureMips16, "mips16"); + getTargetStreamer().emitDirectiveSetMips16(); + Parser.Lex(); // Consume the EndOfStatement. + return false; +} + +bool MipsAsmParser::parseSetNoMips16Directive() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); // Eat "nomips16". + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + clearFeatureBits(Mips::FeatureMips16, "mips16"); + getTargetStreamer().emitDirectiveSetNoMips16(); Parser.Lex(); // Consume the EndOfStatement. return false; } bool MipsAsmParser::parseSetFpDirective() { + MCAsmParser &Parser = getParser(); MipsABIFlagsSection::FpABIKind FpAbiVal; // Line can be: .set fp=32 // .set fp=xx @@ -2463,7 +3007,7 @@ bool MipsAsmParser::parseSetFpDirective() { Parser.Lex(); // Eat fp token AsmToken Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Equal)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected equals sign '='"); return false; } Parser.Lex(); // Eat '=' token. @@ -2473,7 +3017,7 @@ bool MipsAsmParser::parseSetFpDirective() { return false; if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } getTargetStreamer().emitDirectiveSetFp(FpAbiVal); @@ -2481,15 +3025,50 @@ bool MipsAsmParser::parseSetFpDirective() { return false; } +bool MipsAsmParser::parseSetPopDirective() { + MCAsmParser &Parser = getParser(); + SMLoc Loc = getLexer().getLoc(); + + Parser.Lex(); + if (getLexer().isNot(AsmToken::EndOfStatement)) + return reportParseError("unexpected token, expected end of statement"); + + // Always keep an element on the options "stack" to prevent the user + // from changing the initial options. This is how we remember them. + if (AssemblerOptions.size() == 2) + return reportParseError(Loc, ".set pop with no .set push"); + + AssemblerOptions.pop_back(); + setAvailableFeatures(AssemblerOptions.back()->getFeatures()); + + getTargetStreamer().emitDirectiveSetPop(); + return false; +} + +bool MipsAsmParser::parseSetPushDirective() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); + if (getLexer().isNot(AsmToken::EndOfStatement)) + return reportParseError("unexpected token, expected end of statement"); + + // Create a copy of the current assembler options environment and push it. + AssemblerOptions.push_back( + make_unique<MipsAssemblerOptions>(AssemblerOptions.back().get())); + + getTargetStreamer().emitDirectiveSetPush(); + return false; +} + bool MipsAsmParser::parseSetAssignment() { StringRef Name; const MCExpr *Value; + MCAsmParser &Parser = getParser(); if (Parser.parseIdentifier(Name)) reportParseError("expected identifier after .set"); if (getLexer().isNot(AsmToken::Comma)) - return reportParseError("unexpected token in .set directive"); + return reportParseError("unexpected token, expected comma"); Lex(); // Eat comma if (Parser.parseExpression(Value)) @@ -2505,10 +3084,61 @@ bool MipsAsmParser::parseSetAssignment() { return false; } +bool MipsAsmParser::parseSetMips0Directive() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); + if (getLexer().isNot(AsmToken::EndOfStatement)) + return reportParseError("unexpected token, expected end of statement"); + + // Reset assembler options to their initial values. + setAvailableFeatures(AssemblerOptions.front()->getFeatures()); + AssemblerOptions.back()->setFeatures(AssemblerOptions.front()->getFeatures()); + + getTargetStreamer().emitDirectiveSetMips0(); + return false; +} + +bool MipsAsmParser::parseSetArchDirective() { + MCAsmParser &Parser = getParser(); + Parser.Lex(); + if (getLexer().isNot(AsmToken::Equal)) + return reportParseError("unexpected token, expected equals sign"); + + Parser.Lex(); + StringRef Arch; + if (Parser.parseIdentifier(Arch)) + return reportParseError("expected arch identifier"); + + StringRef ArchFeatureName = + StringSwitch<StringRef>(Arch) + .Case("mips1", "mips1") + .Case("mips2", "mips2") + .Case("mips3", "mips3") + .Case("mips4", "mips4") + .Case("mips5", "mips5") + .Case("mips32", "mips32") + .Case("mips32r2", "mips32r2") + .Case("mips32r6", "mips32r6") + .Case("mips64", "mips64") + .Case("mips64r2", "mips64r2") + .Case("mips64r6", "mips64r6") + .Case("cnmips", "cnmips") + .Case("r4000", "mips3") // This is an implementation of Mips3. + .Default(""); + + if (ArchFeatureName.empty()) + return reportParseError("unsupported architecture"); + + selectArch(ArchFeatureName); + getTargetStreamer().emitDirectiveSetArch(Arch); + return false; +} + bool MipsAsmParser::parseSetFeature(uint64_t Feature) { + MCAsmParser &Parser = getParser(); Parser.Lex(); if (getLexer().isNot(AsmToken::EndOfStatement)) - return reportParseError("unexpected token in .set directive"); + return reportParseError("unexpected token, expected end of statement"); switch (Feature) { default: @@ -2520,26 +3150,56 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) { case Mips::FeatureMicroMips: getTargetStreamer().emitDirectiveSetMicroMips(); break; - case Mips::FeatureMips16: - getTargetStreamer().emitDirectiveSetMips16(); + case Mips::FeatureMips1: + selectArch("mips1"); + getTargetStreamer().emitDirectiveSetMips1(); + break; + case Mips::FeatureMips2: + selectArch("mips2"); + getTargetStreamer().emitDirectiveSetMips2(); + break; + case Mips::FeatureMips3: + selectArch("mips3"); + getTargetStreamer().emitDirectiveSetMips3(); + break; + case Mips::FeatureMips4: + selectArch("mips4"); + getTargetStreamer().emitDirectiveSetMips4(); + break; + case Mips::FeatureMips5: + selectArch("mips5"); + getTargetStreamer().emitDirectiveSetMips5(); + break; + case Mips::FeatureMips32: + selectArch("mips32"); + getTargetStreamer().emitDirectiveSetMips32(); break; case Mips::FeatureMips32r2: - setFeatureBits(Mips::FeatureMips32r2, "mips32r2"); + selectArch("mips32r2"); getTargetStreamer().emitDirectiveSetMips32R2(); break; + case Mips::FeatureMips32r6: + selectArch("mips32r6"); + getTargetStreamer().emitDirectiveSetMips32R6(); + break; case Mips::FeatureMips64: - setFeatureBits(Mips::FeatureMips64, "mips64"); + selectArch("mips64"); getTargetStreamer().emitDirectiveSetMips64(); break; case Mips::FeatureMips64r2: - setFeatureBits(Mips::FeatureMips64r2, "mips64r2"); + selectArch("mips64r2"); getTargetStreamer().emitDirectiveSetMips64R2(); break; + case Mips::FeatureMips64r6: + selectArch("mips64r6"); + getTargetStreamer().emitDirectiveSetMips64R6(); + break; } return false; } bool MipsAsmParser::eatComma(StringRef ErrorStr) { + MCAsmParser &Parser = getParser(); if (getLexer().isNot(AsmToken::Comma)) { SMLoc Loc = getLexer().getLoc(); Parser.eatToEndOfStatement(); @@ -2550,14 +3210,17 @@ bool MipsAsmParser::eatComma(StringRef ErrorStr) { return true; } -bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) { - if (Options.isReorder()) - Warning(Loc, ".cpload in reorder section"); +bool MipsAsmParser::parseDirectiveCpLoad(SMLoc Loc) { + if (AssemblerOptions.back()->isReorder()) + Warning(Loc, ".cpload should be inside a noreorder section"); - // FIXME: Warn if cpload is used in Mips16 mode. + if (inMips16Mode()) { + reportParseError(".cpload is not supported in Mips16 mode"); + return false; + } SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Reg; - OperandMatchResultTy ResTy = ParseAnyRegister(Reg); + OperandMatchResultTy ResTy = parseAnyRegister(Reg); if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { reportParseError("expected register containing function address"); return false; @@ -2569,17 +3232,24 @@ bool MipsAsmParser::parseDirectiveCPLoad(SMLoc Loc) { return false; } - getTargetStreamer().emitDirectiveCpload(RegOpnd.getGPR32Reg()); + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + getTargetStreamer().emitDirectiveCpLoad(RegOpnd.getGPR32Reg()); return false; } bool MipsAsmParser::parseDirectiveCPSetup() { + MCAsmParser &Parser = getParser(); unsigned FuncReg; unsigned Save; bool SaveIsReg = true; SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; - OperandMatchResultTy ResTy = ParseAnyRegister(TmpReg); + OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); if (ResTy == MatchOperand_NoMatch) { reportParseError("expected register containing function address"); Parser.eatToEndOfStatement(); @@ -2596,10 +3266,10 @@ bool MipsAsmParser::parseDirectiveCPSetup() { FuncReg = FuncRegOpnd.getGPR32Reg(); TmpReg.clear(); - if (!eatComma("expected comma parsing directive")) + if (!eatComma("unexpected token, expected comma")) return true; - ResTy = ParseAnyRegister(TmpReg); + ResTy = parseAnyRegister(TmpReg); if (ResTy == MatchOperand_NoMatch) { const AsmToken &Tok = Parser.getTok(); if (Tok.is(AsmToken::Integer)) { @@ -2621,7 +3291,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() { Save = SaveOpnd.getGPR32Reg(); } - if (!eatComma("expected comma parsing directive")) + if (!eatComma("unexpected token, expected comma")) return true; StringRef Name; @@ -2634,6 +3304,7 @@ bool MipsAsmParser::parseDirectiveCPSetup() { } bool MipsAsmParser::parseDirectiveNaN() { + MCAsmParser &Parser = getParser(); if (getLexer().isNot(AsmToken::EndOfStatement)) { const AsmToken &Tok = Parser.getTok(); @@ -2654,7 +3325,7 @@ bool MipsAsmParser::parseDirectiveNaN() { } bool MipsAsmParser::parseDirectiveSet() { - + MCAsmParser &Parser = getParser(); // Get the next token. const AsmToken &Tok = Parser.getTok(); @@ -2662,8 +3333,14 @@ bool MipsAsmParser::parseDirectiveSet() { return parseSetNoAtDirective(); } else if (Tok.getString() == "at") { return parseSetAtDirective(); + } else if (Tok.getString() == "arch") { + return parseSetArchDirective(); } else if (Tok.getString() == "fp") { return parseSetFpDirective(); + } else if (Tok.getString() == "pop") { + return parseSetPopDirective(); + } else if (Tok.getString() == "push") { + return parseSetPushDirective(); } else if (Tok.getString() == "reorder") { return parseSetReorderDirective(); } else if (Tok.getString() == "noreorder") { @@ -2673,7 +3350,7 @@ bool MipsAsmParser::parseDirectiveSet() { } else if (Tok.getString() == "nomacro") { return parseSetNoMacroDirective(); } else if (Tok.getString() == "mips16") { - return parseSetFeature(Mips::FeatureMips16); + return parseSetMips16Directive(); } else if (Tok.getString() == "nomips16") { return parseSetNoMips16Directive(); } else if (Tok.getString() == "nomicromips") { @@ -2682,14 +3359,38 @@ bool MipsAsmParser::parseDirectiveSet() { return false; } else if (Tok.getString() == "micromips") { return parseSetFeature(Mips::FeatureMicroMips); + } else if (Tok.getString() == "mips0") { + return parseSetMips0Directive(); + } else if (Tok.getString() == "mips1") { + return parseSetFeature(Mips::FeatureMips1); + } else if (Tok.getString() == "mips2") { + return parseSetFeature(Mips::FeatureMips2); + } else if (Tok.getString() == "mips3") { + return parseSetFeature(Mips::FeatureMips3); + } else if (Tok.getString() == "mips4") { + return parseSetFeature(Mips::FeatureMips4); + } else if (Tok.getString() == "mips5") { + return parseSetFeature(Mips::FeatureMips5); + } else if (Tok.getString() == "mips32") { + return parseSetFeature(Mips::FeatureMips32); } else if (Tok.getString() == "mips32r2") { return parseSetFeature(Mips::FeatureMips32r2); + } else if (Tok.getString() == "mips32r6") { + return parseSetFeature(Mips::FeatureMips32r6); } else if (Tok.getString() == "mips64") { return parseSetFeature(Mips::FeatureMips64); } else if (Tok.getString() == "mips64r2") { return parseSetFeature(Mips::FeatureMips64r2); + } else if (Tok.getString() == "mips64r6") { + return parseSetFeature(Mips::FeatureMips64r6); } else if (Tok.getString() == "dsp") { return parseSetFeature(Mips::FeatureDSP); + } else if (Tok.getString() == "nodsp") { + return parseSetNoDspDirective(); + } else if (Tok.getString() == "msa") { + return parseSetMsaDirective(); + } else if (Tok.getString() == "nomsa") { + return parseSetNoMsaDirective(); } else { // It is just an identifier, look for an assignment. parseSetAssignment(); @@ -2702,6 +3403,7 @@ bool MipsAsmParser::parseDirectiveSet() { /// parseDataDirective /// ::= .word [ expression (, expression)* ] bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) { + MCAsmParser &Parser = getParser(); if (getLexer().isNot(AsmToken::EndOfStatement)) { for (;;) { const MCExpr *Value; @@ -2713,9 +3415,8 @@ bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) { if (getLexer().is(AsmToken::EndOfStatement)) break; - // FIXME: Improve diagnostic. if (getLexer().isNot(AsmToken::Comma)) - return Error(L, "unexpected token in directive"); + return Error(L, "unexpected token, expected comma"); Parser.Lex(); } } @@ -2727,6 +3428,7 @@ bool MipsAsmParser::parseDataDirective(unsigned Size, SMLoc L) { /// parseDirectiveGpWord /// ::= .gpword local_sym bool MipsAsmParser::parseDirectiveGpWord() { + MCAsmParser &Parser = getParser(); const MCExpr *Value; // EmitGPRel32Value requires an expression, so we are using base class // method to evaluate the expression. @@ -2735,7 +3437,8 @@ bool MipsAsmParser::parseDirectiveGpWord() { getParser().getStreamer().EmitGPRel32Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), "unexpected token in directive"); + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); Parser.Lex(); // Eat EndOfStatement token. return false; } @@ -2743,6 +3446,7 @@ bool MipsAsmParser::parseDirectiveGpWord() { /// parseDirectiveGpDWord /// ::= .gpdword local_sym bool MipsAsmParser::parseDirectiveGpDWord() { + MCAsmParser &Parser = getParser(); const MCExpr *Value; // EmitGPRel64Value requires an expression, so we are using base class // method to evaluate the expression. @@ -2751,17 +3455,19 @@ bool MipsAsmParser::parseDirectiveGpDWord() { getParser().getStreamer().EmitGPRel64Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), "unexpected token in directive"); + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); Parser.Lex(); // Eat EndOfStatement token. return false; } bool MipsAsmParser::parseDirectiveOption() { + MCAsmParser &Parser = getParser(); // Get the option token. AsmToken Tok = Parser.getTok(); // At the moment only identifiers are supported. if (Tok.isNot(AsmToken::Identifier)) { - Error(Parser.getTok().getLoc(), "unexpected token in .option directive"); + Error(Parser.getTok().getLoc(), "unexpected token, expected identifier"); Parser.eatToEndOfStatement(); return false; } @@ -2773,7 +3479,7 @@ bool MipsAsmParser::parseDirectiveOption() { Parser.Lex(); if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { Error(Parser.getTok().getLoc(), - "unexpected token in .option pic0 directive"); + "unexpected token, expected end of statement"); Parser.eatToEndOfStatement(); } return false; @@ -2784,14 +3490,15 @@ bool MipsAsmParser::parseDirectiveOption() { Parser.Lex(); if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { Error(Parser.getTok().getLoc(), - "unexpected token in .option pic2 directive"); + "unexpected token, expected end of statement"); Parser.eatToEndOfStatement(); } return false; } // Unknown option. - Warning(Parser.getTok().getLoc(), "unknown option in .option directive"); + Warning(Parser.getTok().getLoc(), + "unknown option, expected 'pic0' or 'pic2'"); Parser.eatToEndOfStatement(); return false; } @@ -2801,10 +3508,11 @@ bool MipsAsmParser::parseDirectiveOption() { /// ::= .module nooddspreg /// ::= .module fp=value bool MipsAsmParser::parseDirectiveModule() { + MCAsmParser &Parser = getParser(); MCAsmLexer &Lexer = getLexer(); SMLoc L = Lexer.getLoc(); - if (!getTargetStreamer().getCanHaveModuleDir()) { + if (!getTargetStreamer().isModuleDirectiveAllowed()) { // TODO : get a better message. reportParseError(".module directive must appear before any code"); return false; @@ -2819,7 +3527,7 @@ bool MipsAsmParser::parseDirectiveModule() { clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("Expected end of statement"); + reportParseError("unexpected token, expected end of statement"); return false; } @@ -2834,7 +3542,7 @@ bool MipsAsmParser::parseDirectiveModule() { setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("Expected end of statement"); + reportParseError("unexpected token, expected end of statement"); return false; } @@ -2854,10 +3562,11 @@ bool MipsAsmParser::parseDirectiveModule() { /// ::= =xx /// ::= =64 bool MipsAsmParser::parseDirectiveModuleFP() { + MCAsmParser &Parser = getParser(); MCAsmLexer &Lexer = getLexer(); if (Lexer.isNot(AsmToken::Equal)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected equals sign '='"); return false; } Parser.Lex(); // Eat '=' token. @@ -2867,7 +3576,7 @@ bool MipsAsmParser::parseDirectiveModuleFP() { return false; if (getLexer().isNot(AsmToken::EndOfStatement)) { - reportParseError("unexpected token in statement"); + reportParseError("unexpected token, expected end of statement"); return false; } @@ -2879,6 +3588,7 @@ bool MipsAsmParser::parseDirectiveModuleFP() { bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, StringRef Directive) { + MCAsmParser &Parser = getParser(); MCAsmLexer &Lexer = getLexer(); if (Lexer.is(AsmToken::Identifier)) { @@ -2925,30 +3635,160 @@ bool MipsAsmParser::parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, } bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { + MCAsmParser &Parser = getParser(); StringRef IDVal = DirectiveID.getString(); if (IDVal == ".cpload") - return parseDirectiveCPLoad(DirectiveID.getLoc()); + return parseDirectiveCpLoad(DirectiveID.getLoc()); if (IDVal == ".dword") { parseDataDirective(8, DirectiveID.getLoc()); return false; } - if (IDVal == ".ent") { - // Ignore this directive for now. - Parser.Lex(); + StringRef SymbolName; + + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .ent"); + return false; + } + + // There's an undocumented extension that allows an integer to + // follow the name of the procedure which AFAICS is ignored by GAS. + // Example: .ent foo,2 + if (getLexer().isNot(AsmToken::EndOfStatement)) { + if (getLexer().isNot(AsmToken::Comma)) { + // Even though we accept this undocumented extension for compatibility + // reasons, the additional integer argument does not actually change + // the behaviour of the '.ent' directive, so we would like to discourage + // its use. We do this by not referring to the extended version in + // error messages which are not directly related to its use. + reportParseError("unexpected token, expected end of statement"); + return false; + } + Parser.Lex(); // Eat the comma. + const MCExpr *DummyNumber; + int64_t DummyNumberVal; + // If the user was explicitly trying to use the extended version, + // we still give helpful extension-related error messages. + if (Parser.parseExpression(DummyNumber)) { + reportParseError("expected number after comma"); + return false; + } + if (!DummyNumber->EvaluateAsAbsolute(DummyNumberVal)) { + reportParseError("expected an absolute expression after comma"); + return false; + } + } + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + MCSymbol *Sym = getContext().GetOrCreateSymbol(SymbolName); + + getTargetStreamer().emitDirectiveEnt(*Sym); + CurrentFn = Sym; return false; } if (IDVal == ".end") { - // Ignore this directive for now. - Parser.Lex(); + StringRef SymbolName; + + if (Parser.parseIdentifier(SymbolName)) { + reportParseError("expected identifier after .end"); + return false; + } + + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + if (CurrentFn == nullptr) { + reportParseError(".end used without .ent"); + return false; + } + + if ((SymbolName != CurrentFn->getName())) { + reportParseError(".end symbol does not match .ent symbol"); + return false; + } + + getTargetStreamer().emitDirectiveEnd(SymbolName); + CurrentFn = nullptr; return false; } if (IDVal == ".frame") { - // Ignore this directive for now. - Parser.eatToEndOfStatement(); + // .frame $stack_reg, frame_size_in_bytes, $return_reg + SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> TmpReg; + OperandMatchResultTy ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected stack register"); + return false; + } + + MipsOperand &StackRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); + if (!StackRegOpnd.isGPRAsmReg()) { + reportParseError(StackRegOpnd.getStartLoc(), + "expected general purpose register"); + return false; + } + unsigned StackReg = StackRegOpnd.getGPR32Reg(); + + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + + // Parse the frame size. + const MCExpr *FrameSize; + int64_t FrameSizeVal; + + if (Parser.parseExpression(FrameSize)) { + reportParseError("expected frame size value"); + return false; + } + + if (!FrameSize->EvaluateAsAbsolute(FrameSizeVal)) { + reportParseError("frame size not an absolute expression"); + return false; + } + + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + + // Parse the return register. + TmpReg.clear(); + ResTy = parseAnyRegister(TmpReg); + if (ResTy == MatchOperand_NoMatch || ResTy == MatchOperand_ParseFail) { + reportParseError("expected return register"); + return false; + } + + MipsOperand &ReturnRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); + if (!ReturnRegOpnd.isGPRAsmReg()) { + reportParseError(ReturnRegOpnd.getStartLoc(), + "expected general purpose register"); + return false; + } + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + getTargetStreamer().emitFrame(StackReg, FrameSizeVal, + ReturnRegOpnd.getGPR32Reg()); return false; } @@ -2956,15 +3796,61 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { return parseDirectiveSet(); } - if (IDVal == ".fmask") { - // Ignore this directive for now. - Parser.eatToEndOfStatement(); - return false; - } + if (IDVal == ".mask" || IDVal == ".fmask") { + // .mask bitmask, frame_offset + // bitmask: One bit for each register used. + // frame_offset: Offset from Canonical Frame Address ($sp on entry) where + // first register is expected to be saved. + // Examples: + // .mask 0x80000000, -4 + // .fmask 0x80000000, -4 + // - if (IDVal == ".mask") { - // Ignore this directive for now. - Parser.eatToEndOfStatement(); + // Parse the bitmask + const MCExpr *BitMask; + int64_t BitMaskVal; + + if (Parser.parseExpression(BitMask)) { + reportParseError("expected bitmask value"); + return false; + } + + if (!BitMask->EvaluateAsAbsolute(BitMaskVal)) { + reportParseError("bitmask not an absolute expression"); + return false; + } + + if (Parser.getTok().is(AsmToken::Comma)) + Parser.Lex(); + else { + reportParseError("unexpected token, expected comma"); + return false; + } + + // Parse the frame_offset + const MCExpr *FrameOffset; + int64_t FrameOffsetVal; + + if (Parser.parseExpression(FrameOffset)) { + reportParseError("expected frame offset value"); + return false; + } + + if (!FrameOffset->EvaluateAsAbsolute(FrameOffsetVal)) { + reportParseError("frame offset not an absolute expression"); + return false; + } + + // If this is not the end of the statement, report an error. + if (getLexer().isNot(AsmToken::EndOfStatement)) { + reportParseError("unexpected token, expected end of statement"); + return false; + } + + if (IDVal == ".mask") + getTargetStreamer().emitMask(BitMaskVal, FrameOffsetVal); + else + getTargetStreamer().emitFMask(BitMaskVal, FrameOffsetVal); return false; } @@ -2992,7 +3878,8 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { if (IDVal == ".abicalls") { getTargetStreamer().emitDirectiveAbiCalls(); if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { - Error(Parser.getTok().getLoc(), "unexpected token in directive"); + Error(Parser.getTok().getLoc(), + "unexpected token, expected end of statement"); // Clear line Parser.eatToEndOfStatement(); } diff --git a/lib/Target/Mips/CMakeLists.txt b/lib/Target/Mips/CMakeLists.txt index bf67d71..1f201b0 100644 --- a/lib/Target/Mips/CMakeLists.txt +++ b/lib/Target/Mips/CMakeLists.txt @@ -3,8 +3,7 @@ set(LLVM_TARGET_DEFINITIONS Mips.td) tablegen(LLVM MipsGenRegisterInfo.inc -gen-register-info) tablegen(LLVM MipsGenInstrInfo.inc -gen-instr-info) tablegen(LLVM MipsGenDisassemblerTables.inc -gen-disassembler) -tablegen(LLVM MipsGenCodeEmitter.inc -gen-emitter) -tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter -mc-emitter) +tablegen(LLVM MipsGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM MipsGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM MipsGenDAGISel.inc -gen-dag-isel) tablegen(LLVM MipsGenFastISel.inc -gen-fast-isel) @@ -22,13 +21,13 @@ add_llvm_target(MipsCodeGen Mips16ISelDAGToDAG.cpp Mips16ISelLowering.cpp Mips16RegisterInfo.cpp + MipsABIInfo.cpp MipsAnalyzeImmediate.cpp MipsAsmPrinter.cpp - MipsCodeEmitter.cpp + MipsCCState.cpp MipsConstantIslandPass.cpp MipsDelaySlotFiller.cpp MipsFastISel.cpp - MipsJITInfo.cpp MipsInstrInfo.cpp MipsISelDAGToDAG.cpp MipsISelLowering.cpp diff --git a/lib/Target/Mips/Disassembler/LLVMBuild.txt b/lib/Target/Mips/Disassembler/LLVMBuild.txt index bb70fd3..414b4f7 100644 --- a/lib/Target/Mips/Disassembler/LLVMBuild.txt +++ b/lib/Target/Mips/Disassembler/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = MipsDisassembler parent = Mips -required_libraries = MC MipsInfo Support +required_libraries = MCDisassembler MipsInfo Support add_to_library_groups = Mips diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index 902b877..48904ce 100644 --- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -20,7 +20,6 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/MathExtras.h" -#include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -31,15 +30,14 @@ typedef MCDisassembler::DecodeStatus DecodeStatus; namespace { -/// MipsDisassemblerBase - a disasembler class for Mips. +/// A disasembler class for Mips. class MipsDisassemblerBase : public MCDisassembler { public: - /// Constructor - Initializes the disassembler. - /// MipsDisassemblerBase(const MCSubtargetInfo &STI, MCContext &Ctx, - bool bigEndian) : - MCDisassembler(STI, Ctx), - IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {} + bool IsBigEndian) + : MCDisassembler(STI, Ctx), + IsN64(STI.getFeatureBits() & Mips::FeatureN64), + IsBigEndian(IsBigEndian) {} virtual ~MipsDisassemblerBase() {} @@ -48,15 +46,13 @@ public: private: bool IsN64; protected: - bool isBigEndian; + bool IsBigEndian; }; -/// MipsDisassembler - a disasembler class for Mips32. +/// A disasembler class for Mips32. class MipsDisassembler : public MipsDisassemblerBase { bool IsMicroMips; public: - /// Constructor - Initializes the disassembler. - /// MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) : MipsDisassemblerBase(STI, Ctx, bigEndian) { IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips; @@ -75,32 +71,23 @@ public: return !hasMips32() && !hasMips3(); } - /// getInstruction - See MCDisassembler. - DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const override; }; - -/// Mips64Disassembler - a disasembler class for Mips64. +/// A disasembler class for Mips64. class Mips64Disassembler : public MipsDisassemblerBase { public: - /// Constructor - Initializes the disassembler. - /// Mips64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool bigEndian) : MipsDisassemblerBase(STI, Ctx, bigEndian) {} - /// getInstruction - See MCDisassembler. - DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const override; }; } // end anonymous namespace @@ -117,6 +104,11 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -142,11 +134,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, uint64_t Address, const void *Decoder); -static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder); - static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -255,6 +242,11 @@ static DecodeStatus DecodeMem(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeCacheOp(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); @@ -272,6 +264,14 @@ static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + +static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -341,6 +341,10 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn, + uint64_t Address, + const void *Decoder); + namespace llvm { extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, TheMips64elTarget; @@ -456,7 +460,7 @@ static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { @@ -495,7 +499,7 @@ static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rs >= Rt) { @@ -535,7 +539,7 @@ static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) @@ -580,7 +584,7 @@ static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; if (Rt == 0) return MCDisassembler::Fail; @@ -622,7 +626,7 @@ static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; bool HasRt = false; @@ -671,7 +675,7 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, InsnType Rs = fieldFromInstruction(insn, 21, 5); InsnType Rt = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) << 2; + InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4; bool HasRs = false; if (Rt == 0) @@ -696,43 +700,31 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, return MCDisassembler::Success; } - /// readInstruction - read four bytes from the MemoryObject - /// and return 32 bit word sorted according to the given endianess -static DecodeStatus readInstruction32(const MemoryObject ®ion, - uint64_t address, - uint64_t &size, - uint32_t &insn, - bool isBigEndian, - bool IsMicroMips) { - uint8_t Bytes[4]; - +/// Read four bytes from the ArrayRef and return 32 bit word sorted +/// according to the given endianess +static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, + uint64_t &Size, uint32_t &Insn, + bool IsBigEndian, bool IsMicroMips) { // We want to read exactly 4 Bytes of data. - if (region.readBytes(address, 4, Bytes) == -1) { - size = 0; + if (Bytes.size() < 4) { + Size = 0; return MCDisassembler::Fail; } - if (isBigEndian) { + if (IsBigEndian) { // Encoded as a big-endian 32-bit word in the stream. - insn = (Bytes[3] << 0) | - (Bytes[2] << 8) | - (Bytes[1] << 16) | - (Bytes[0] << 24); - } - else { + Insn = + (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); + } else { // Encoded as a small-endian 32-bit word in the stream. // Little-endian byte ordering: // mips32r2: 4 | 3 | 2 | 1 // microMIPS: 2 | 1 | 4 | 3 if (IsMicroMips) { - insn = (Bytes[2] << 0) | - (Bytes[3] << 8) | - (Bytes[0] << 16) | + Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) | (Bytes[1] << 24); } else { - insn = (Bytes[0] << 0) | - (Bytes[1] << 8) | - (Bytes[2] << 16) | + Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) | (Bytes[3] << 24); } } @@ -740,24 +732,22 @@ static DecodeStatus readInstruction32(const MemoryObject ®ion, return MCDisassembler::Success; } -DecodeStatus -MipsDisassembler::getInstruction(MCInst &instr, - uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &vStream, - raw_ostream &cStream) const { +DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, + uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const { uint32_t Insn; - DecodeStatus Result = readInstruction32(Region, Address, Size, - Insn, isBigEndian, IsMicroMips); + DecodeStatus Result = + readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, IsMicroMips); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; if (IsMicroMips) { DEBUG(dbgs() << "Trying MicroMips32 table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address, + Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -769,7 +759,7 @@ MipsDisassembler::getInstruction(MCInst &instr, if (hasCOP3()) { DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n"); Result = - decodeInstruction(DecoderTableCOP3_32, instr, Insn, Address, this, STI); + decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -778,7 +768,7 @@ MipsDisassembler::getInstruction(MCInst &instr, if (hasMips32r6() && isGP64()) { DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn, + Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -788,7 +778,7 @@ MipsDisassembler::getInstruction(MCInst &instr, if (hasMips32r6()) { DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n"); - Result = decodeInstruction(DecoderTableMips32r6_64r632, instr, Insn, + Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; @@ -798,8 +788,8 @@ MipsDisassembler::getInstruction(MCInst &instr, DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n"); // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, - this, STI); + Result = + decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -808,30 +798,28 @@ MipsDisassembler::getInstruction(MCInst &instr, return MCDisassembler::Fail; } -DecodeStatus -Mips64Disassembler::getInstruction(MCInst &instr, - uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &vStream, - raw_ostream &cStream) const { +DecodeStatus Mips64Disassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, + uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const { uint32_t Insn; - DecodeStatus Result = readInstruction32(Region, Address, Size, - Insn, isBigEndian, false); + DecodeStatus Result = + readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address, - this, STI); + Result = + decodeInstruction(DecoderTableMips6432, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; } // If we fail to decode in Mips64 decoder space we can try in Mips32 - Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address, - this, STI); + Result = + decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; return Result; @@ -862,6 +850,13 @@ static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, + unsigned RegNo, + uint64_t Address, + const void *Decoder) { + return MCDisassembler::Fail; +} + static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -914,18 +909,6 @@ static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, return MCDisassembler::Success; } -static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst, - unsigned RegNo, - uint64_t Address, - const void *Decoder) { - if (RegNo > 31) - return MCDisassembler::Fail; - - unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo); - Inst.addOperand(MCOperand::CreateReg(Reg)); - return MCDisassembler::Success; -} - static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, @@ -981,6 +964,23 @@ static DecodeStatus DecodeMem(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeCacheOp(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Hint = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + Inst.addOperand(MCOperand::CreateImm(Hint)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10)); @@ -1012,15 +1012,15 @@ static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn, break; case Mips::LD_H: case Mips::ST_H: - Inst.addOperand(MCOperand::CreateImm(Offset << 1)); + Inst.addOperand(MCOperand::CreateImm(Offset * 2)); break; case Mips::LD_W: case Mips::ST_W: - Inst.addOperand(MCOperand::CreateImm(Offset << 2)); + Inst.addOperand(MCOperand::CreateImm(Offset * 4)); break; case Mips::LD_D: case Mips::ST_D: - Inst.addOperand(MCOperand::CreateImm(Offset << 3)); + Inst.addOperand(MCOperand::CreateImm(Offset * 8)); break; } @@ -1038,12 +1038,23 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); Base = getReg(Decoder, Mips::GPR32RegClassID, Base); - if (Inst.getOpcode() == Mips::SC_MM) + switch (Inst.getOpcode()) { + case Mips::SWM32_MM: + case Mips::LWM32_MM: + if (DecodeRegListOperand(Inst, Insn, Address, Decoder) + == MCDisassembler::Fail) + return MCDisassembler::Fail; + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + break; + case Mips::SC_MM: Inst.addOperand(MCOperand::CreateReg(Reg)); - - Inst.addOperand(MCOperand::CreateReg(Reg)); - Inst.addOperand(MCOperand::CreateReg(Base)); - Inst.addOperand(MCOperand::CreateImm(Offset)); + // fallthrough + default: + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + } return MCDisassembler::Success; } @@ -1084,6 +1095,42 @@ static DecodeStatus DecodeFMem(MCInst &Inst, return MCDisassembler::Success; } +static DecodeStatus DecodeFMem2(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::COP2RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + +static DecodeStatus DecodeFMem3(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0xffff); + unsigned Reg = fieldFromInstruction(Insn, 16, 5); + unsigned Base = fieldFromInstruction(Insn, 21, 5); + + Reg = getReg(Decoder, Mips::COP3RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::CreateReg(Reg)); + Inst.addOperand(MCOperand::CreateReg(Base)); + Inst.addOperand(MCOperand::CreateImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1242,7 +1289,7 @@ static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = (SignExtend32<16>(Offset) << 2) + 4; + int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; } @@ -1261,7 +1308,7 @@ static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<21>(Offset) << 2; + int32_t BranchOffset = SignExtend32<21>(Offset) * 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; @@ -1271,7 +1318,7 @@ static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<26>(Offset) << 2; + int32_t BranchOffset = SignExtend32<26>(Offset) * 4; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; @@ -1281,7 +1328,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<16>(Offset) << 1; + int32_t BranchOffset = SignExtend32<16>(Offset) * 2; Inst.addOperand(MCOperand::CreateImm(BranchOffset)); return MCDisassembler::Success; } @@ -1334,12 +1381,35 @@ static DecodeStatus DecodeExtSize(MCInst &Inst, static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) << 2)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4)); return MCDisassembler::Success; } static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) << 3)); + Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8)); + return MCDisassembler::Success; +} + +static DecodeStatus DecodeRegListOperand(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, + Mips::S6, Mips::FP}; + unsigned RegNum; + + unsigned RegLst = fieldFromInstruction(Insn, 21, 5); + // Empty register lists are not allowed. + if (RegLst == 0) + return MCDisassembler::Fail; + + RegNum = RegLst & 0xf; + for (unsigned i = 0; i < RegNum; i++) + Inst.addOperand(MCOperand::CreateReg(Regs[i])); + + if (RegLst & 0x10) + Inst.addOperand(MCOperand::CreateReg(Mips::RA)); + return MCDisassembler::Success; } diff --git a/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index 8c79751..ab6b225 100644 --- a/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -225,6 +225,18 @@ printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) + + // opNum can be invalid if instruction had reglist as operand. + // MemOperand is always last operand of instruction (base + offset). + switch (MI->getOpcode()) { + default: + break; + case Mips::SWM32_MM: + case Mips::LWM32_MM: + opNum = MI->getNumOperands() - 2; + break; + } + printOperand(MI, opNum+1, O); O << "("; printOperand(MI, opNum, O); @@ -324,3 +336,13 @@ void MipsInstPrinter::printSaveRestore(const MCInst *MI, raw_ostream &O) { } } +void MipsInstPrinter:: +printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) { + // - 2 because register List is always first operand of instruction and it is + // always followed by memory operand (base + offset). + for (int i = opNum, e = MI->getNumOperands() - 2; i != e; ++i) { + if (i != opNum) + O << ", "; + printRegName(O, MI->getOperand(i).getReg()); + } +} diff --git a/lib/Target/Mips/InstPrinter/MipsInstPrinter.h b/lib/Target/Mips/InstPrinter/MipsInstPrinter.h index 550a0f1..42df013 100644 --- a/lib/Target/Mips/InstPrinter/MipsInstPrinter.h +++ b/lib/Target/Mips/InstPrinter/MipsInstPrinter.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSINSTPRINTER_H -#define MIPSINSTPRINTER_H +#ifndef LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H +#define LLVM_LIB_TARGET_MIPS_INSTPRINTER_MIPSINSTPRINTER_H #include "llvm/MC/MCInstPrinter.h" namespace llvm { @@ -107,6 +107,7 @@ private: unsigned OpNo1, raw_ostream &OS); bool printAlias(const MCInst &MI, raw_ostream &OS); void printSaveRestore(const MCInst *MI, raw_ostream &O); + void printRegisterList(const MCInst *MI, int opNum, raw_ostream &O); }; } // end namespace llvm diff --git a/lib/Target/Mips/LLVMBuild.txt b/lib/Target/Mips/LLVMBuild.txt index e6d3a42..0e8d902 100644 --- a/lib/Target/Mips/LLVMBuild.txt +++ b/lib/Target/Mips/LLVMBuild.txt @@ -31,5 +31,5 @@ has_jit = 1 type = Library name = MipsCodeGen parent = Mips -required_libraries = Analysis AsmPrinter CodeGen Core MC MipsAsmPrinter MipsDesc MipsInfo Scalar SelectionDAG Support Target +required_libraries = Analysis AsmPrinter CodeGen Core MC MipsAsmPrinter MipsDesc MipsInfo SelectionDAG Support Target add_to_library_groups = Mips diff --git a/lib/Target/Mips/MCTargetDesc/Android.mk b/lib/Target/Mips/MCTargetDesc/Android.mk index c8d18fc..89e132d 100644 --- a/lib/Target/Mips/MCTargetDesc/Android.mk +++ b/lib/Target/Mips/MCTargetDesc/Android.mk @@ -15,6 +15,7 @@ mips_mc_desc_SRC_FILES := \ MipsMCCodeEmitter.cpp \ MipsMCExpr.cpp \ MipsMCTargetDesc.cpp \ + MipsOptionRecord.cpp \ MipsNaClELFStreamer.cpp \ MipsTargetStreamer.cpp diff --git a/lib/Target/Mips/MCTargetDesc/CMakeLists.txt b/lib/Target/Mips/MCTargetDesc/CMakeLists.txt index c14ee35..6b3788c 100644 --- a/lib/Target/Mips/MCTargetDesc/CMakeLists.txt +++ b/lib/Target/Mips/MCTargetDesc/CMakeLists.txt @@ -8,5 +8,6 @@ add_llvm_library(LLVMMipsDesc MipsMCExpr.cpp MipsMCTargetDesc.cpp MipsNaClELFStreamer.cpp + MipsOptionRecord.cpp MipsTargetStreamer.cpp ) diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp index 52d5dd3..5b0f950 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.cpp @@ -41,6 +41,12 @@ StringRef MipsABIFlagsSection::getFpABIString(FpABIKind Value) { } } +uint8_t MipsABIFlagsSection::getCPR1SizeValue() { + if (FpABI == FpABIKind::XX) + return (uint8_t)AFL_REG_32; + return (uint8_t)CPR1Size; +} + namespace llvm { MCStreamer &operator<<(MCStreamer &OS, MipsABIFlagsSection &ABIFlagsSection) { // Write out a Elf_Internal_ABIFlags_v0 struct diff --git a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h index ab18c44..8bcfb0f 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h +++ b/lib/Target/Mips/MCTargetDesc/MipsABIFlagsSection.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSABIFLAGSSECTION_H -#define MIPSABIFLAGSSECTION_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSABIFLAGSSECTION_H #include "llvm/MC/MCStreamer.h" @@ -115,7 +115,7 @@ public: uint8_t getISALevelValue() { return (uint8_t)ISALevel; } uint8_t getISARevisionValue() { return (uint8_t)ISARevision; } uint8_t getGPRSizeValue() { return (uint8_t)GPRSize; } - uint8_t getCPR1SizeValue() { return (uint8_t)CPR1Size; } + uint8_t getCPR1SizeValue(); uint8_t getCPR2SizeValue() { return (uint8_t)CPR2Size; } uint8_t getFpABIValue(); uint32_t getISAExtensionSetValue() { return (uint32_t)ISAExtensionSet; } @@ -181,7 +181,7 @@ public: template <class PredicateLibrary> void setCPR1SizeFromPredicates(const PredicateLibrary &P) { - if (P.mipsSEUsesSoftFloat()) + if (P.abiUsesSoftFloat()) CPR1Size = AFL_REG_NONE; else if (P.hasMSA()) CPR1Size = AFL_REG_128; @@ -212,10 +212,10 @@ public: if (P.isABI_N32() || P.isABI_N64()) FpABI = FpABIKind::S64; else if (P.isABI_O32()) { - if (P.isFP64bit()) - FpABI = FpABIKind::S64; - else if (P.isABI_FPXX()) + if (P.isABI_FPXX()) FpABI = FpABIKind::XX; + else if (P.isFP64bit()) + FpABI = FpABIKind::S64; else FpABI = FpABIKind::S32; } @@ -228,6 +228,7 @@ public: setCPR1SizeFromPredicates(P); setASESetFromPredicates(P); setFpAbiFromPredicates(P); + OddSPReg = P.useOddSPReg(); } }; diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index d8e6128..efeb54d 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -367,7 +367,12 @@ bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { // Check for a less than instruction size number of bytes // FIXME: 16 bit instructions are not handled yet here. // We shouldn't be using a hard coded number for instruction size. - if (Count % 4) return false; + + // If the count is not 4-byte aligned, we must be writing data into the text + // section (otherwise we have unaligned instructions, and thus have far + // bigger problems), so just write zeros instead. + for (uint64_t i = 0, e = Count % 4; i != e; ++i) + OW->Write8(0); uint64_t NumNops = Count / 4; for (uint64_t i = 0; i != NumNops; ++i) diff --git a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h index d5c3dbc..d4f4983 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h +++ b/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// // -#ifndef MIPSASMBACKEND_H -#define MIPSASMBACKEND_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H #include "MCTargetDesc/MipsFixupKinds.h" #include "llvm/MC/MCAsmBackend.h" diff --git a/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h index d2323dc..ff7779e 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h +++ b/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h @@ -11,8 +11,8 @@ // the Mips target useful for the compiler back-end and the MC libraries. // //===----------------------------------------------------------------------===// -#ifndef MIPSBASEINFO_H -#define MIPSBASEINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSBASEINFO_H #include "MipsFixupKinds.h" #include "MipsMCTargetDesc.h" diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index 49ac256..4ea7846 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -30,7 +30,8 @@ namespace { unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, bool IsPCRel) const override; - bool needsRelocateWithSymbol(unsigned Type) const override; + bool needsRelocateWithSymbol(const MCSymbolData &SD, + unsigned Type) const override; }; } @@ -216,7 +217,8 @@ unsigned MipsELFObjectWriter::GetRelocType(const MCValue &Target, } bool -MipsELFObjectWriter::needsRelocateWithSymbol(unsigned Type) const { +MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbolData &SD, + unsigned Type) const { // FIXME: This is extremelly conservative. This really needs to use a // whitelist with a clear explanation for why each realocation needs to // point to the symbol, not to the section. diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp index fe37829..18c4a20 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.cpp @@ -8,12 +8,72 @@ //===----------------------------------------------------------------------===// #include "MipsELFStreamer.h" +#include "MipsTargetStreamer.h" +#include "llvm/MC/MCELF.h" +#include "llvm/MC/MCInst.h" +#include "llvm/Support/ELF.h" + +using namespace llvm; + +void MipsELFStreamer::EmitInstruction(const MCInst &Inst, + const MCSubtargetInfo &STI) { + MCELFStreamer::EmitInstruction(Inst, STI); + + MCContext &Context = getContext(); + const MCRegisterInfo *MCRegInfo = Context.getRegisterInfo(); + MipsTargetELFStreamer *ELFTargetStreamer = + static_cast<MipsTargetELFStreamer *>(getTargetStreamer()); + + for (unsigned OpIndex = 0; OpIndex < Inst.getNumOperands(); ++OpIndex) { + const MCOperand &Op = Inst.getOperand(OpIndex); + + if (!Op.isReg()) + continue; + + unsigned Reg = Op.getReg(); + RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo); + } + + if (ELFTargetStreamer->isMicroMipsEnabled()) { + for (auto Label : Labels) { + MCSymbolData &Data = getOrCreateSymbolData(Label); + // The "other" values are stored in the last 6 bits of the second byte. + // The traditional defines for STO values assume the full byte and thus + // the shift to pack it. + MCELF::setOther(Data, ELF::STO_MIPS_MICROMIPS >> 2); + } + } + + Labels.clear(); +} + +void MipsELFStreamer::EmitLabel(MCSymbol *Symbol) { + MCELFStreamer::EmitLabel(Symbol); + Labels.push_back(Symbol); +} + +void MipsELFStreamer::SwitchSection(const MCSection * Section, + const MCExpr *Subsection) { + MCELFStreamer::SwitchSection(Section, Subsection); + Labels.clear(); +} + +void MipsELFStreamer::EmitValueImpl(const MCExpr *Value, unsigned Size, + const SMLoc &Loc) { + MCELFStreamer::EmitValueImpl(Value, Size, Loc); + Labels.clear(); +} + +void MipsELFStreamer::EmitMipsOptionRecords() { + for (const auto &I : MipsOptionRecords) + I->EmitMipsOptionRecord(); +} namespace llvm { MCELFStreamer *createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, bool RelaxAll, - bool NoExecStack) { + const MCSubtargetInfo &STI, + bool RelaxAll) { return new MipsELFStreamer(Context, MAB, OS, Emitter, STI); } } diff --git a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h index 641f8cf..136146b 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h +++ b/lib/Target/Mips/MCTargetDesc/MipsELFStreamer.h @@ -12,11 +12,13 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSELFSTREAMER_H -#define MIPSELFSTREAMER_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSELFSTREAMER_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSELFSTREAMER_H +#include "MipsOptionRecord.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/MC/MCELFStreamer.h" -#include "llvm/Support/raw_ostream.h" +#include <memory> namespace llvm { class MCAsmBackend; @@ -25,18 +27,48 @@ class MCContext; class MCSubtargetInfo; class MipsELFStreamer : public MCELFStreamer { + SmallVector<std::unique_ptr<MipsOptionRecord>, 8> MipsOptionRecords; + MipsRegInfoRecord *RegInfoRecord; + SmallVector<MCSymbol*, 4> Labels; + public: MipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI) - : MCELFStreamer(Context, MAB, OS, Emitter) {} + : MCELFStreamer(Context, MAB, OS, Emitter) { + + RegInfoRecord = new MipsRegInfoRecord(this, Context, STI); + MipsOptionRecords.push_back( + std::unique_ptr<MipsRegInfoRecord>(RegInfoRecord)); + } + + /// Overriding this function allows us to add arbitrary behaviour before the + /// \p Inst is actually emitted. For example, we can inspect the operands and + /// gather sufficient information that allows us to reason about the register + /// usage for the translation unit. + void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override; + + /// Overriding this function allows us to record all labels that should be + /// marked as microMIPS. Based on this data marking is done in + /// EmitInstruction. + void EmitLabel(MCSymbol *Symbol) override; + + /// Overriding this function allows us to dismiss all labels that are + /// candidates for marking as microMIPS when .section directive is processed. + void SwitchSection(const MCSection *Section, + const MCExpr *Subsection = nullptr) override; + + /// Overriding this function allows us to dismiss all labels that are + /// candidates for marking as microMIPS when .word directive is emitted. + void EmitValueImpl(const MCExpr *Value, unsigned Size, + const SMLoc &Loc) override; - virtual ~MipsELFStreamer() {} + /// Emits all the option records stored up until the point it's called. + void EmitMipsOptionRecords(); }; MCELFStreamer *createMipsELFStreamer(MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, bool RelaxAll, - bool NoExecStack); + const MCSubtargetInfo &STI, bool RelaxAll); } // namespace llvm. #endif diff --git a/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h b/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h index 05080f0..317db16 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h +++ b/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_MIPS_MIPSFIXUPKINDS_H -#define LLVM_MIPS_MIPSFIXUPKINDS_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSFIXUPKINDS_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSFIXUPKINDS_H #include "llvm/MC/MCFixup.h" @@ -199,4 +199,4 @@ namespace Mips { } // namespace llvm -#endif // LLVM_MIPS_MIPSFIXUPKINDS_H +#endif diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index e415412..2f5d196 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -41,6 +41,5 @@ MipsMCAsmInfo::MipsMCAsmInfo(StringRef TT) { UseAssignmentForEHBegin = true; SupportsDebugInformation = true; ExceptionsType = ExceptionHandling::DwarfCFI; - HasLEB128 = true; DwarfRegNumForCFI = true; } diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h index 37ba0c4..59ff1c4 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSTARGETASMINFO_H -#define MIPSTARGETASMINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 43fc521..d632c27 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -345,6 +345,67 @@ getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, } unsigned MipsMCCodeEmitter:: +getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + // The immediate is encoded as 'immediate << 2'. + unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); + assert((Res & 3) == 0); + return Res >> 2; + } + + assert(MO.isExpr() && + "getUImm5Lsl2Encoding expects only expressions or an immediate"); + + return 0; +} + +unsigned MipsMCCodeEmitter:: +getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + int Value = MO.getImm(); + return Value >> 2; + } + + return 0; +} + +unsigned MipsMCCodeEmitter:: +getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + unsigned Value = MO.getImm(); + return Value >> 2; + } + + return 0; +} + +unsigned MipsMCCodeEmitter:: +getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + if (MO.isImm()) { + unsigned Binary = (MO.getImm() >> 2) & 0x0000ffff; + return (((Binary & 0x8000) >> 7) | (Binary & 0x00ff)); + } + + return 0; +} + +unsigned MipsMCCodeEmitter:: getExprOpValue(const MCExpr *Expr,SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { int64_t Res; @@ -577,6 +638,17 @@ unsigned MipsMCCodeEmitter:: getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const { + // opNum can be invalid if instruction had reglist as operand. + // MemOperand is always last operand of instruction (base + offset). + switch (MI.getOpcode()) { + default: + break; + case Mips::SWM32_MM: + case Mips::LWM32_MM: + OpNo = MI.getNumOperands() - 2; + break; + } + // Base register is encoded in bits 20-16, offset is encoded in bits 11-0. assert(MI.getOperand(OpNo).isReg()); unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), Fixups, STI) << 16; @@ -659,4 +731,61 @@ MipsMCCodeEmitter::getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, return 0; } +unsigned +MipsMCCodeEmitter::getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + assert(MI.getOperand(OpNo).isImm()); + const MCOperand &MO = MI.getOperand(OpNo); + return MO.getImm() % 8; +} + +unsigned +MipsMCCodeEmitter::getUImm4AndValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + assert(MI.getOperand(OpNo).isImm()); + const MCOperand &MO = MI.getOperand(OpNo); + unsigned Value = MO.getImm(); + switch (Value) { + case 128: return 0x0; + case 1: return 0x1; + case 2: return 0x2; + case 3: return 0x3; + case 4: return 0x4; + case 7: return 0x5; + case 8: return 0x6; + case 15: return 0x7; + case 16: return 0x8; + case 31: return 0x9; + case 32: return 0xa; + case 63: return 0xb; + case 64: return 0xc; + case 255: return 0xd; + case 32768: return 0xe; + case 65535: return 0xf; + } + llvm_unreachable("Unexpected value"); +} + +unsigned +MipsMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + unsigned res = 0; + + // Register list operand is always first operand of instruction and it is + // placed before memory operand (register + imm). + + for (unsigned I = OpNo, E = MI.getNumOperands() - 2; I < E; ++I) { + unsigned Reg = MI.getOperand(I).getReg(); + unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); + if (RegNo != 31) + res++; + else + res |= 0x10; + } + return res; +} + #include "MipsGenMCCodeEmitter.inc" diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index 304167f..9016fcf 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -12,8 +12,8 @@ //===----------------------------------------------------------------------===// // -#ifndef MIPS_MC_CODE_EMITTER_H -#define MIPS_MC_CODE_EMITTER_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H #include "llvm/MC/MCCodeEmitter.h" #include "llvm/Support/DataTypes.h" @@ -60,7 +60,7 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; - // getBranchJumpOpValue - Return binary encoding of the jump + // getJumpTargetOpValue - Return binary encoding of the jump // target operand. If the machine operand requires relocation, // record the relocation and return zero. unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, @@ -74,6 +74,26 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump + // target operand. + unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + + unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + + // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp + // instruction immediate operand. + unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + // getBranchTargetOpValue - Return binary encoding of the branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. @@ -145,9 +165,19 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; }; // class MipsMCCodeEmitter } // namespace llvm. diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp index 5bba3e5..74490f3 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.cpp @@ -80,8 +80,9 @@ void MipsMCExpr::PrintImpl(raw_ostream &OS) const { bool MipsMCExpr::EvaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout) const { - return getSubExpr()->EvaluateAsRelocatable(Res, Layout); + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + return getSubExpr()->EvaluateAsRelocatable(Res, Layout, Fixup); } void MipsMCExpr::visitUsedExpr(MCStreamer &Streamer) const { diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h index f193dc9..2b8f0c8 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCExpr.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSMCEXPR_H -#define MIPSMCEXPR_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCEXPR_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCEXPR_H #include "llvm/MC/MCAsmLayout.h" #include "llvm/MC/MCExpr.h" @@ -48,7 +48,8 @@ public: void PrintImpl(raw_ostream &OS) const override; bool EvaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout) const override; + const MCAsmLayout *Layout, + const MCFixup *Fixup) const override; void visitUsedExpr(MCStreamer &Streamer) const override; const MCSection *FindAssociatedSection() const override { return getSubExpr()->FindAssociatedSection(); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h b/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h index 01d5363..e756b47 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCNaCl.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSMCNACL_H -#define MIPSMCNACL_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCNACL_H #include "llvm/MC/MCELFStreamer.h" @@ -26,8 +26,7 @@ MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, - bool RelaxAll, bool NoExecStack); - + bool RelaxAll); } #endif diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index d2b929b..bab4254 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -109,15 +109,12 @@ static MCInstPrinter *createMipsMCInstPrinter(const Target &T, static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, - bool RelaxAll, bool NoExecStack) { + const MCSubtargetInfo &STI, bool RelaxAll) { MCStreamer *S; if (!Triple(TT).isOSNaCl()) - S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll, - NoExecStack); + S = createMipsELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll); else - S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll, - NoExecStack); + S = createMipsNaClELFStreamer(Context, MAB, OS, Emitter, STI, RelaxAll); new MipsTargetELFStreamer(*S, STI); return S; } diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 161d1ea..f08a8f4 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSMCTARGETDESC_H -#define MIPSMCTARGETDESC_H +#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H +#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCTARGETDESC_H #include "llvm/Support/DataTypes.h" diff --git a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp index 6cde8f9..92b8455 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp @@ -255,13 +255,11 @@ MCELFStreamer *createMipsNaClELFStreamer(MCContext &Context, MCAsmBackend &TAB, raw_ostream &OS, MCCodeEmitter *Emitter, const MCSubtargetInfo &STI, - bool RelaxAll, bool NoExecStack) { + bool RelaxAll) { MipsNaClELFStreamer *S = new MipsNaClELFStreamer(Context, TAB, OS, Emitter, STI); if (RelaxAll) S->getAssembler().setRelaxAll(true); - if (NoExecStack) - S->getAssembler().setNoExecStack(true); // Set bundle-alignment as required by the NaCl ABI for the target. S->EmitBundleAlignMode(MIPS_NACL_BUNDLE_ALIGN); diff --git a/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp b/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp new file mode 100644 index 0000000..0ef2208 --- /dev/null +++ b/lib/Target/Mips/MCTargetDesc/MipsOptionRecord.cpp @@ -0,0 +1,92 @@ +//===-- MipsOptionRecord.cpp - Abstraction for storing information --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MipsOptionRecord.h" +#include "MipsELFStreamer.h" +#include "llvm/MC/MCSectionELF.h" + +using namespace llvm; + +void MipsRegInfoRecord::EmitMipsOptionRecord() { + MCAssembler &MCA = Streamer->getAssembler(); + Triple T(STI.getTargetTriple()); + uint64_t Features = STI.getFeatureBits(); + + Streamer->PushSection(); + + // We need to distinguish between N64 and the rest because at the moment + // we don't emit .Mips.options for other ELFs other than N64. + // Since .reginfo has the same information as .Mips.options (ODK_REGINFO), + // we can use the same abstraction (MipsRegInfoRecord class) to handle both. + if (Features & Mips::FeatureN64) { + // The EntrySize value of 1 seems strange since the records are neither + // 1-byte long nor fixed length but it matches the value GAS emits. + const MCSectionELF *Sec = + Context.getELFSection(".MIPS.options", ELF::SHT_MIPS_OPTIONS, + ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, + SectionKind::getMetadata(), 1, ""); + MCA.getOrCreateSectionData(*Sec).setAlignment(8); + Streamer->SwitchSection(Sec); + + Streamer->EmitIntValue(1, 1); // kind + Streamer->EmitIntValue(40, 1); // size + Streamer->EmitIntValue(0, 2); // section + Streamer->EmitIntValue(0, 4); // info + Streamer->EmitIntValue(ri_gprmask, 4); + Streamer->EmitIntValue(0, 4); // pad + Streamer->EmitIntValue(ri_cprmask[0], 4); + Streamer->EmitIntValue(ri_cprmask[1], 4); + Streamer->EmitIntValue(ri_cprmask[2], 4); + Streamer->EmitIntValue(ri_cprmask[3], 4); + Streamer->EmitIntValue(ri_gp_value, 8); + } else { + const MCSectionELF *Sec = + Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC, + SectionKind::getMetadata(), 24, ""); + MCA.getOrCreateSectionData(*Sec) + .setAlignment(Features & Mips::FeatureN32 ? 8 : 4); + Streamer->SwitchSection(Sec); + + Streamer->EmitIntValue(ri_gprmask, 4); + Streamer->EmitIntValue(ri_cprmask[0], 4); + Streamer->EmitIntValue(ri_cprmask[1], 4); + Streamer->EmitIntValue(ri_cprmask[2], 4); + Streamer->EmitIntValue(ri_cprmask[3], 4); + assert((ri_gp_value & 0xffffffff) == ri_gp_value); + Streamer->EmitIntValue(ri_gp_value, 4); + } + + Streamer->PopSection(); +} + +void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, + const MCRegisterInfo *MCRegInfo) { + unsigned Value = 0; + + for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid(); + ++SubRegIt) { + unsigned CurrentSubReg = *SubRegIt; + + unsigned EncVal = MCRegInfo->getEncodingValue(CurrentSubReg); + Value |= 1 << EncVal; + + if (GPR32RegClass->contains(CurrentSubReg) || + GPR64RegClass->contains(CurrentSubReg)) + ri_gprmask |= Value; + else if (FGR32RegClass->contains(CurrentSubReg) || + FGR64RegClass->contains(CurrentSubReg) || + AFGR64RegClass->contains(CurrentSubReg) || + MSA128BRegClass->contains(CurrentSubReg)) + ri_cprmask[1] |= Value; + else if (COP2RegClass->contains(CurrentSubReg)) + ri_cprmask[2] |= Value; + else if (COP3RegClass->contains(CurrentSubReg)) + ri_cprmask[3] |= Value; + } +} diff --git a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp index fbe375b..1e092f2 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "InstPrinter/MipsInstPrinter.h" +#include "MipsELFStreamer.h" #include "MipsMCTargetDesc.h" #include "MipsTargetObjectFile.h" #include "MipsTargetStreamer.h" @@ -28,17 +29,21 @@ using namespace llvm; MipsTargetStreamer::MipsTargetStreamer(MCStreamer &S) - : MCTargetStreamer(S), canHaveModuleDirective(true) {} + : MCTargetStreamer(S), ModuleDirectiveAllowed(true) { + GPRInfoSet = FPRInfoSet = FrameInfoSet = false; +} void MipsTargetStreamer::emitDirectiveSetMicroMips() {} void MipsTargetStreamer::emitDirectiveSetNoMicroMips() {} void MipsTargetStreamer::emitDirectiveSetMips16() {} -void MipsTargetStreamer::emitDirectiveSetNoMips16() {} -void MipsTargetStreamer::emitDirectiveSetReorder() {} +void MipsTargetStreamer::emitDirectiveSetNoMips16() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetReorder() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveSetNoReorder() {} -void MipsTargetStreamer::emitDirectiveSetMacro() {} -void MipsTargetStreamer::emitDirectiveSetNoMacro() {} -void MipsTargetStreamer::emitDirectiveSetAt() {} -void MipsTargetStreamer::emitDirectiveSetNoAt() {} +void MipsTargetStreamer::emitDirectiveSetMacro() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoMacro() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMsa() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoMsa() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetAt() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoAt() { forbidModuleDirective(); } void MipsTargetStreamer::emitDirectiveEnd(StringRef Name) {} void MipsTargetStreamer::emitDirectiveEnt(const MCSymbol &Symbol) {} void MipsTargetStreamer::emitDirectiveAbiCalls() {} @@ -51,11 +56,26 @@ void MipsTargetStreamer::emitFrame(unsigned StackReg, unsigned StackSize, void MipsTargetStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) {} void MipsTargetStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) { } -void MipsTargetStreamer::emitDirectiveSetMips32R2() {} -void MipsTargetStreamer::emitDirectiveSetMips64() {} -void MipsTargetStreamer::emitDirectiveSetMips64R2() {} -void MipsTargetStreamer::emitDirectiveSetDsp() {} -void MipsTargetStreamer::emitDirectiveCpload(unsigned RegNo) {} +void MipsTargetStreamer::emitDirectiveSetArch(StringRef Arch) { + forbidModuleDirective(); +} +void MipsTargetStreamer::emitDirectiveSetMips0() {} +void MipsTargetStreamer::emitDirectiveSetMips1() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips2() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips3() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips4() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips5() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips32() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips32R2() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips32R6() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips64() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips64R2() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetMips64R6() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetPop() {} +void MipsTargetStreamer::emitDirectiveSetPush() {} +void MipsTargetStreamer::emitDirectiveSetDsp() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveSetNoDsp() { forbidModuleDirective(); } +void MipsTargetStreamer::emitDirectiveCpLoad(unsigned RegNo) {} void MipsTargetStreamer::emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) { } @@ -71,52 +91,62 @@ MipsTargetAsmStreamer::MipsTargetAsmStreamer(MCStreamer &S, void MipsTargetAsmStreamer::emitDirectiveSetMicroMips() { OS << "\t.set\tmicromips\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveSetNoMicroMips() { OS << "\t.set\tnomicromips\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveSetMips16() { OS << "\t.set\tmips16\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveSetNoMips16() { OS << "\t.set\tnomips16\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetNoMips16(); } void MipsTargetAsmStreamer::emitDirectiveSetReorder() { OS << "\t.set\treorder\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetReorder(); } void MipsTargetAsmStreamer::emitDirectiveSetNoReorder() { OS << "\t.set\tnoreorder\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveSetMacro() { OS << "\t.set\tmacro\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetMacro(); } void MipsTargetAsmStreamer::emitDirectiveSetNoMacro() { OS << "\t.set\tnomacro\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetNoMacro(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMsa() { + OS << "\t.set\tmsa\n"; + MipsTargetStreamer::emitDirectiveSetMsa(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetNoMsa() { + OS << "\t.set\tnomsa\n"; + MipsTargetStreamer::emitDirectiveSetNoMsa(); } void MipsTargetAsmStreamer::emitDirectiveSetAt() { OS << "\t.set\tat\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetAt(); } void MipsTargetAsmStreamer::emitDirectiveSetNoAt() { OS << "\t.set\tnoat\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetNoAt(); } void MipsTargetAsmStreamer::emitDirectiveEnd(StringRef Name) { @@ -151,25 +181,82 @@ void MipsTargetAsmStreamer::emitFrame(unsigned StackReg, unsigned StackSize, << StringRef(MipsInstPrinter::getRegisterName(ReturnReg)).lower() << '\n'; } +void MipsTargetAsmStreamer::emitDirectiveSetArch(StringRef Arch) { + OS << "\t.set arch=" << Arch << "\n"; + MipsTargetStreamer::emitDirectiveSetArch(Arch); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips0() { OS << "\t.set\tmips0\n"; } + +void MipsTargetAsmStreamer::emitDirectiveSetMips1() { + OS << "\t.set\tmips1\n"; + MipsTargetStreamer::emitDirectiveSetMips1(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips2() { + OS << "\t.set\tmips2\n"; + MipsTargetStreamer::emitDirectiveSetMips2(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips3() { + OS << "\t.set\tmips3\n"; + MipsTargetStreamer::emitDirectiveSetMips3(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips4() { + OS << "\t.set\tmips4\n"; + MipsTargetStreamer::emitDirectiveSetMips4(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips5() { + OS << "\t.set\tmips5\n"; + MipsTargetStreamer::emitDirectiveSetMips5(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips32() { + OS << "\t.set\tmips32\n"; + MipsTargetStreamer::emitDirectiveSetMips32(); +} + void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() { OS << "\t.set\tmips32r2\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetMips32R2(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips32R6() { + OS << "\t.set\tmips32r6\n"; + MipsTargetStreamer::emitDirectiveSetMips32R6(); } void MipsTargetAsmStreamer::emitDirectiveSetMips64() { OS << "\t.set\tmips64\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetMips64(); } void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() { OS << "\t.set\tmips64r2\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetMips64R2(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetMips64R6() { + OS << "\t.set\tmips64r6\n"; + MipsTargetStreamer::emitDirectiveSetMips64R6(); } void MipsTargetAsmStreamer::emitDirectiveSetDsp() { OS << "\t.set\tdsp\n"; - setCanHaveModuleDir(false); + MipsTargetStreamer::emitDirectiveSetDsp(); } + +void MipsTargetAsmStreamer::emitDirectiveSetNoDsp() { + OS << "\t.set\tnodsp\n"; + MipsTargetStreamer::emitDirectiveSetNoDsp(); +} + +void MipsTargetAsmStreamer::emitDirectiveSetPop() { OS << "\t.set\tpop\n"; } + +void MipsTargetAsmStreamer::emitDirectiveSetPush() { OS << "\t.set\tpush\n"; } + // Print a 32 bit hex number with all numbers. static void printHex32(unsigned Value, raw_ostream &OS) { OS << "0x"; @@ -191,10 +278,10 @@ void MipsTargetAsmStreamer::emitFMask(unsigned FPUBitmask, OS << "," << FPUTopSavedRegOff << '\n'; } -void MipsTargetAsmStreamer::emitDirectiveCpload(unsigned RegNo) { +void MipsTargetAsmStreamer::emitDirectiveCpLoad(unsigned RegNo) { OS << "\t.cpload\t$" << StringRef(MipsInstPrinter::getRegisterName(RegNo)).lower() << "\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo, @@ -213,7 +300,7 @@ void MipsTargetAsmStreamer::emitDirectiveCpsetup(unsigned RegNo, OS << ", "; OS << Sym.getName() << "\n"; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetAsmStreamer::emitDirectiveModuleFP( @@ -281,27 +368,29 @@ MipsTargetELFStreamer::MipsTargetELFStreamer(MCStreamer &S, else EFlags |= ELF::EF_MIPS_ARCH_1; - if (T.isArch64Bit()) { - if (Features & Mips::FeatureN32) - EFlags |= ELF::EF_MIPS_ABI2; - else if (Features & Mips::FeatureO32) { - EFlags |= ELF::EF_MIPS_ABI_O32; - EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */ - } - // No need to set any bit for N64 which is the default ABI at the moment - // for 64-bit Mips architectures. - } else { - if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64) - EFlags |= ELF::EF_MIPS_32BITMODE; - - // ABI + // ABI + // N64 does not require any ABI bits. + if (Features & Mips::FeatureO32) EFlags |= ELF::EF_MIPS_ABI_O32; - } + else if (Features & Mips::FeatureN32) + EFlags |= ELF::EF_MIPS_ABI2; + + if (Features & Mips::FeatureGP64Bit) { + if (Features & Mips::FeatureO32) + EFlags |= ELF::EF_MIPS_32BITMODE; /* Compatibility Mode */ + } else if (Features & Mips::FeatureMips64r2 || Features & Mips::FeatureMips64) + EFlags |= ELF::EF_MIPS_32BITMODE; // Other options. if (Features & Mips::FeatureNaN2008) EFlags |= ELF::EF_MIPS_NAN2008; + // -mabicalls and -mplt are not implemented but we should act as if they were + // given. + EFlags |= ELF::EF_MIPS_CPIC; + if (Features & Mips::FeatureN64) + EFlags |= ELF::EF_MIPS_PIC; + MCA.setELFHeaderEFlags(EFlags); } @@ -321,41 +410,26 @@ void MipsTargetELFStreamer::emitLabel(MCSymbol *Symbol) { void MipsTargetELFStreamer::finish() { MCAssembler &MCA = getStreamer().getAssembler(); - MCContext &Context = MCA.getContext(); - MCStreamer &OS = getStreamer(); - Triple T(STI.getTargetTriple()); - uint64_t Features = STI.getFeatureBits(); + const MCObjectFileInfo &OFI = *MCA.getContext().getObjectFileInfo(); + + // .bss, .text and .data are always at least 16-byte aligned. + MCSectionData &TextSectionData = + MCA.getOrCreateSectionData(*OFI.getTextSection()); + MCSectionData &DataSectionData = + MCA.getOrCreateSectionData(*OFI.getDataSection()); + MCSectionData &BSSSectionData = + MCA.getOrCreateSectionData(*OFI.getBSSSection()); + + TextSectionData.setAlignment(std::max(16u, TextSectionData.getAlignment())); + DataSectionData.setAlignment(std::max(16u, DataSectionData.getAlignment())); + BSSSectionData.setAlignment(std::max(16u, BSSSectionData.getAlignment())); + + // Emit all the option records. + // At the moment we are only emitting .Mips.options (ODK_REGINFO) and + // .reginfo. + MipsELFStreamer &MEF = static_cast<MipsELFStreamer &>(Streamer); + MEF.EmitMipsOptionRecords(); - if (T.isArch64Bit() && (Features & Mips::FeatureN64)) { - const MCSectionELF *Sec = Context.getELFSection( - ".MIPS.options", ELF::SHT_MIPS_OPTIONS, - ELF::SHF_ALLOC | ELF::SHF_MIPS_NOSTRIP, SectionKind::getMetadata()); - OS.SwitchSection(Sec); - - OS.EmitIntValue(1, 1); // kind - OS.EmitIntValue(40, 1); // size - OS.EmitIntValue(0, 2); // section - OS.EmitIntValue(0, 4); // info - OS.EmitIntValue(0, 4); // ri_gprmask - OS.EmitIntValue(0, 4); // pad - OS.EmitIntValue(0, 4); // ri_cpr[0]mask - OS.EmitIntValue(0, 4); // ri_cpr[1]mask - OS.EmitIntValue(0, 4); // ri_cpr[2]mask - OS.EmitIntValue(0, 4); // ri_cpr[3]mask - OS.EmitIntValue(0, 8); // ri_gp_value - } else { - const MCSectionELF *Sec = - Context.getELFSection(".reginfo", ELF::SHT_MIPS_REGINFO, ELF::SHF_ALLOC, - SectionKind::getMetadata()); - OS.SwitchSection(Sec); - - OS.EmitIntValue(0, 4); // ri_gprmask - OS.EmitIntValue(0, 4); // ri_cpr[0]mask - OS.EmitIntValue(0, 4); // ri_cpr[1]mask - OS.EmitIntValue(0, 4); // ri_cpr[2]mask - OS.EmitIntValue(0, 4); // ri_cpr[3]mask - OS.EmitIntValue(0, 4); // ri_gp_value - } emitMipsAbiFlags(); } @@ -390,11 +464,12 @@ void MipsTargetELFStreamer::emitDirectiveSetMicroMips() { unsigned Flags = MCA.getELFHeaderEFlags(); Flags |= ELF::EF_MIPS_MICROMIPS; MCA.setELFHeaderEFlags(Flags); + forbidModuleDirective(); } void MipsTargetELFStreamer::emitDirectiveSetNoMicroMips() { MicroMipsEnabled = false; - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetELFStreamer::emitDirectiveSetMips16() { @@ -402,17 +477,7 @@ void MipsTargetELFStreamer::emitDirectiveSetMips16() { unsigned Flags = MCA.getELFHeaderEFlags(); Flags |= ELF::EF_MIPS_ARCH_ASE_M16; MCA.setELFHeaderEFlags(Flags); - setCanHaveModuleDir(false); -} - -void MipsTargetELFStreamer::emitDirectiveSetNoMips16() { - // FIXME: implement. - setCanHaveModuleDir(false); -} - -void MipsTargetELFStreamer::emitDirectiveSetReorder() { - // FIXME: implement. - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetELFStreamer::emitDirectiveSetNoReorder() { @@ -420,35 +485,49 @@ void MipsTargetELFStreamer::emitDirectiveSetNoReorder() { unsigned Flags = MCA.getELFHeaderEFlags(); Flags |= ELF::EF_MIPS_NOREORDER; MCA.setELFHeaderEFlags(Flags); - setCanHaveModuleDir(false); + forbidModuleDirective(); } -void MipsTargetELFStreamer::emitDirectiveSetMacro() { - // FIXME: implement. - setCanHaveModuleDir(false); -} +void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { + MCAssembler &MCA = getStreamer().getAssembler(); + MCContext &Context = MCA.getContext(); + MCStreamer &OS = getStreamer(); -void MipsTargetELFStreamer::emitDirectiveSetNoMacro() { - // FIXME: implement. - setCanHaveModuleDir(false); -} + const MCSectionELF *Sec = Context.getELFSection(".pdr", ELF::SHT_PROGBITS, + ELF::SHF_ALLOC | ELF::SHT_REL, + SectionKind::getMetadata()); -void MipsTargetELFStreamer::emitDirectiveSetAt() { - // FIXME: implement. - setCanHaveModuleDir(false); -} + const MCSymbolRefExpr *ExprRef = + MCSymbolRefExpr::Create(Name, MCSymbolRefExpr::VK_None, Context); -void MipsTargetELFStreamer::emitDirectiveSetNoAt() { - // FIXME: implement. - setCanHaveModuleDir(false); -} + MCSectionData &SecData = MCA.getOrCreateSectionData(*Sec); + SecData.setAlignment(4); -void MipsTargetELFStreamer::emitDirectiveEnd(StringRef Name) { - // FIXME: implement. + OS.PushSection(); + + OS.SwitchSection(Sec); + + OS.EmitValueImpl(ExprRef, 4); + + OS.EmitIntValue(GPRInfoSet ? GPRBitMask : 0, 4); // reg_mask + OS.EmitIntValue(GPRInfoSet ? GPROffset : 0, 4); // reg_offset + + OS.EmitIntValue(FPRInfoSet ? FPRBitMask : 0, 4); // fpreg_mask + OS.EmitIntValue(FPRInfoSet ? FPROffset : 0, 4); // fpreg_offset + + OS.EmitIntValue(FrameInfoSet ? FrameOffset : 0, 4); // frame_offset + OS.EmitIntValue(FrameInfoSet ? FrameReg : 0, 4); // frame_reg + OS.EmitIntValue(FrameInfoSet ? ReturnReg : 0, 4); // return_reg + + // The .end directive marks the end of a procedure. Invalidate + // the information gathered up until this point. + GPRInfoSet = FPRInfoSet = FrameInfoSet = false; + + OS.PopSection(); } void MipsTargetELFStreamer::emitDirectiveEnt(const MCSymbol &Symbol) { - // FIXME: implement. + GPRInfoSet = FPRInfoSet = FrameInfoSet = false; } void MipsTargetELFStreamer::emitDirectiveAbiCalls() { @@ -494,37 +573,31 @@ void MipsTargetELFStreamer::emitDirectiveOptionPic2() { } void MipsTargetELFStreamer::emitFrame(unsigned StackReg, unsigned StackSize, - unsigned ReturnReg) { - // FIXME: implement. + unsigned ReturnReg_) { + MCContext &Context = getStreamer().getAssembler().getContext(); + const MCRegisterInfo *RegInfo = Context.getRegisterInfo(); + + FrameInfoSet = true; + FrameReg = RegInfo->getEncodingValue(StackReg); + FrameOffset = StackSize; + ReturnReg = RegInfo->getEncodingValue(ReturnReg_); } void MipsTargetELFStreamer::emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) { - // FIXME: implement. + GPRInfoSet = true; + GPRBitMask = CPUBitmask; + GPROffset = CPUTopSavedRegOff; } void MipsTargetELFStreamer::emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) { - // FIXME: implement. -} - -void MipsTargetELFStreamer::emitDirectiveSetMips32R2() { - setCanHaveModuleDir(false); -} - -void MipsTargetELFStreamer::emitDirectiveSetMips64() { - setCanHaveModuleDir(false); -} - -void MipsTargetELFStreamer::emitDirectiveSetMips64R2() { - setCanHaveModuleDir(false); -} - -void MipsTargetELFStreamer::emitDirectiveSetDsp() { - setCanHaveModuleDir(false); + FPRInfoSet = true; + FPRBitMask = FPUBitmask; + FPROffset = FPUTopSavedRegOff; } -void MipsTargetELFStreamer::emitDirectiveCpload(unsigned RegNo) { +void MipsTargetELFStreamer::emitDirectiveCpLoad(unsigned RegNo) { // .cpload $reg // This directive expands to: // lui $gp, %hi(_gp_disp) @@ -572,7 +645,7 @@ void MipsTargetELFStreamer::emitDirectiveCpload(unsigned RegNo) { TmpInst.addOperand(MCOperand::CreateReg(RegNo)); getStreamer().EmitInstruction(TmpInst, STI); - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo, @@ -629,7 +702,7 @@ void MipsTargetELFStreamer::emitDirectiveCpsetup(unsigned RegNo, Inst.addOperand(MCOperand::CreateReg(RegNo)); getStreamer().EmitInstruction(Inst, STI); - setCanHaveModuleDir(false); + forbidModuleDirective(); } void MipsTargetELFStreamer::emitMipsAbiFlags() { @@ -638,7 +711,7 @@ void MipsTargetELFStreamer::emitMipsAbiFlags() { MCStreamer &OS = getStreamer(); const MCSectionELF *Sec = Context.getELFSection(".MIPS.abiflags", ELF::SHT_MIPS_ABIFLAGS, - ELF::SHF_ALLOC, SectionKind::getMetadata()); + ELF::SHF_ALLOC, SectionKind::getMetadata(), 24, ""); MCSectionData &ABIShndxSD = MCA.getOrCreateSectionData(*Sec); ABIShndxSD.setAlignment(8); OS.SwitchSection(Sec); diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile index 41efa47..56db450 100644 --- a/lib/Target/Mips/Makefile +++ b/lib/Target/Mips/Makefile @@ -13,7 +13,7 @@ TARGET = Mips # Make sure that tblgen is run, first thing. BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \ - MipsGenAsmWriter.inc MipsGenFastISel.inc MipsGenCodeEmitter.inc \ + MipsGenAsmWriter.inc MipsGenFastISel.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtargetInfo.inc MipsGenMCCodeEmitter.inc \ MipsGenDisassemblerTables.inc \ diff --git a/lib/Target/Mips/MicroMipsInstrFPU.td b/lib/Target/Mips/MicroMipsInstrFPU.td index b93017a..fae7059 100644 --- a/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/lib/Target/Mips/MicroMipsInstrFPU.td @@ -123,10 +123,10 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>; -def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>, - MFC1_FM_MM<3>, ISA_MIPS32R2; -def MTHC1_MM : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>, - MFC1_FM_MM<7>, ISA_MIPS32R2; +def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM_MM<0xc0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; +def MTHC1_MM : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, + MFC1_FM_MM<0xe0>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, MADDS_FM_MM<0x1>; diff --git a/lib/Target/Mips/MicroMipsInstrFormats.td b/lib/Target/Mips/MicroMipsInstrFormats.td index 15b951d..59bf949 100644 --- a/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/lib/Target/Mips/MicroMipsInstrFormats.td @@ -41,6 +41,95 @@ class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern, // MicroMIPS 16-bit Instruction Formats //===----------------------------------------------------------------------===// +class ARITH_FM_MM16<bit funct> { + bits<3> rd; + bits<3> rt; + bits<3> rs; + + bits<16> Inst; + + let Inst{15-10} = 0x01; + let Inst{9-7} = rd; + let Inst{6-4} = rt; + let Inst{3-1} = rs; + let Inst{0} = funct; +} + +class ANDI_FM_MM16<bits<6> funct> { + bits<3> rd; + bits<3> rs; + bits<4> imm; + + bits<16> Inst; + + let Inst{15-10} = funct; + let Inst{9-7} = rd; + let Inst{6-4} = rs; + let Inst{3-0} = imm; +} + +class LOGIC_FM_MM16<bits<4> funct> { + bits<3> rt; + bits<3> rs; + + bits<16> Inst; + + let Inst{15-10} = 0x11; + let Inst{9-6} = funct; + let Inst{5-3} = rt; + let Inst{2-0} = rs; +} + +class SHIFT_FM_MM16<bits<1> funct> { + bits<3> rd; + bits<3> rt; + bits<3> shamt; + + bits<16> Inst; + + let Inst{15-10} = 0x09; + let Inst{9-7} = rd; + let Inst{6-4} = rt; + let Inst{3-1} = shamt; + let Inst{0} = funct; +} + +class ADDIUR2_FM_MM16 { + bits<3> rd; + bits<3> rs; + bits<3> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x1b; + let Inst{9-7} = rd; + let Inst{6-4} = rs; + let Inst{3-1} = imm; + let Inst{0} = 0; +} + +class ADDIUS5_FM_MM16 { + bits<5> rd; + bits<4> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x13; + let Inst{9-5} = rd; + let Inst{4-1} = imm; + let Inst{0} = 0; +} + +class ADDIUSP_FM_MM16 { + bits<9> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x13; + let Inst{9-1} = imm; + let Inst{0} = 1; +} + class MOVE_FM_MM16<bits<6> funct> { bits<5> rs; bits<5> rd; @@ -52,6 +141,17 @@ class MOVE_FM_MM16<bits<6> funct> { let Inst{4-0} = rs; } +class LI_FM_MM16 { + bits<3> rd; + bits<7> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x3b; + let Inst{9-7} = rd; + let Inst{6-0} = imm; +} + class JALR_FM_MM16<bits<5> op> { bits<5> rs; @@ -72,6 +172,29 @@ class MFHILO_FM_MM16<bits<5> funct> { let Inst{4-0} = rd; } +class JRADDIUSP_FM_MM16<bits<5> op> { + bits<5> rs; + bits<5> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x11; + let Inst{9-5} = op; + let Inst{4-0} = imm; +} + +class ADDIUR1SP_FM_MM16 { + bits<3> rd; + bits<6> imm; + + bits<16> Inst; + + let Inst{15-10} = 0x1b; + let Inst{9-7} = rd; + let Inst{6-1} = imm; + let Inst{0} = 1; +} + //===----------------------------------------------------------------------===// // MicroMIPS 32-bit Instruction Formats //===----------------------------------------------------------------------===// @@ -621,3 +744,76 @@ class MADDS_FM_MM<bits<6> funct>: MMArch { let Inst{10-6} = fr; let Inst{5-0} = funct; } + +class COMPACT_BRANCH_FM_MM<bits<5> funct> { + bits<5> rs; + bits<16> offset; + + bits<32> Inst; + + let Inst{31-26} = 0x10; + let Inst{25-21} = funct; + let Inst{20-16} = rs; + let Inst{15-0} = offset; +} + +class COP0_TLB_FM_MM<bits<10> op> : MMArch { + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-16} = 0x0; + let Inst{15-6} = op; + let Inst{5-0} = 0x3c; +} + +class SDBBP_FM_MM : MMArch { + bits<10> code_; + + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-16} = code_; + let Inst{15-6} = 0x36d; + let Inst{5-0} = 0x3c; +} + +class RDHWR_FM_MM : MMArch { + bits<5> rt; + bits<5> rd; + + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-21} = rt; + let Inst{20-16} = rd; + let Inst{15-6} = 0x1ac; + let Inst{5-0} = 0x3c; +} + +class LWXS_FM_MM<bits<10> funct> { + bits<5> rd; + bits<5> base; + bits<5> index; + + bits<32> Inst; + + let Inst{31-26} = 0x0; + let Inst{25-21} = index; + let Inst{20-16} = base; + let Inst{15-11} = rd; + let Inst{10} = 0; + let Inst{9-0} = funct; +} + +class LWM_FM_MM<bits<4> funct> : MMArch { + bits<5> rt; + bits<21> addr; + + bits<32> Inst; + + let Inst{31-26} = 0x8; + let Inst{25-21} = rt; + let Inst{20-16} = addr{20-16}; + let Inst{15-12} = funct; + let Inst{11-0} = addr{11-0}; +} diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td index 87a3a3e..e854620 100644 --- a/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/lib/Target/Mips/MicroMipsInstrInfo.td @@ -1,9 +1,51 @@ def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>; +def simm4 : Operand<i32>; +def simm7 : Operand<i32>; + def simm12 : Operand<i32> { let DecoderMethod = "DecodeSimm12"; } +def uimm5_lsl2 : Operand<OtherVT> { + let EncoderMethod = "getUImm5Lsl2Encoding"; +} + +def uimm6_lsl2 : Operand<i32> { + let EncoderMethod = "getUImm6Lsl2Encoding"; +} + +def simm9_addiusp : Operand<i32> { + let EncoderMethod = "getSImm9AddiuspValue"; +} + +def uimm3_shift : Operand<i32> { + let EncoderMethod = "getUImm3Mod8Encoding"; +} + +def simm3_lsa2 : Operand<i32> { + let EncoderMethod = "getSImm3Lsa2Value"; +} + +def uimm4_andi : Operand<i32> { + let EncoderMethod = "getUImm4AndValue"; +} + +def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 || + ((Imm % 4 == 0) && + Imm < 28 && Imm > 0);}]>; + +def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>; + +def immZExtAndi16 : ImmLeaf<i32, + [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || + Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || + Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>; + +def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>; + +def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>; + def mem_mm_12 : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR32, simm12); @@ -26,6 +68,16 @@ def brtarget_mm : Operand<OtherVT> { let DecoderMethod = "DecodeBranchTargetMM"; } +class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op, + RegisterOperand RO> : + InstSE<(outs), (ins RO:$rs, opnd:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> { + let isBranch = 1; + let isTerminator = 1; + let hasDelaySlot = 0; + let Defs = [AT]; +} + let canFoldAsLoad = 1 in class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO, Operand MemOpnd> : @@ -70,6 +122,61 @@ class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, let mayLoad = 1; } +class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0, + InstrItinClass Itin = NoItinerary, + SDPatternOperator OpNode = null_frag> : + MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { + let isCommutable = isComm; +} + +class AndImmMM16<string opstr, RegisterOperand RO, + InstrItinClass Itin = NoItinerary> : + MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm), + !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>; + +class LogicRMM16<string opstr, RegisterOperand RO, + InstrItinClass Itin = NoItinerary, + SDPatternOperator OpNode = null_frag> : + MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt), + !strconcat(opstr, "\t$rt, $rs"), + [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { + let isCommutable = 1; + let Constraints = "$rt = $dst"; +} + +class NotMM16<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs RO:$rt), (ins RO:$rs), + !strconcat(opstr, "\t$rt, $rs"), + [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>; + +class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO, + InstrItinClass Itin = NoItinerary> : + MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), + !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>; + +class AddImmUR2<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), + !strconcat(opstr, "\t$rd, $rs, $imm"), + [], NoItinerary, FrmR> { + let isCommutable = 1; +} + +class AddImmUS5<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm), + !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { + let Constraints = "$rd = $dst"; +} + +class AddImmUR1SP<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm), + !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>; + +class AddImmUSP<string opstr> : + MicroMipsInst16<(outs), (ins simm9_addiusp:$imm), + !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>; + class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> : MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO, FrmR> { @@ -85,6 +192,13 @@ class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0, let isReMaterializable = 1; } +class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO, + SDPatternOperator imm_type = null_frag> : + MicroMipsInst16<(outs RO:$rd), (ins Od:$imm), + !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> { + let isReMaterializable = 1; +} + // 16-bit Jump and Link (Call) class JumpLinkRegMM16<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), @@ -94,16 +208,140 @@ class JumpLinkRegMM16<string opstr, RegisterOperand RO> : let Defs = [RA]; } +// 16-bit Jump Reg +class JumpRegMM16<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), + [], IIBranch, FrmR> { + let hasDelaySlot = 1; + let isBranch = 1; + let isIndirectBranch = 1; +} + +// Base class for JRADDIUSP instruction. +class JumpRAddiuStackMM16 : + MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm", + [], IIBranch, FrmR> { + let isTerminator = 1; + let isBarrier = 1; + let hasDelaySlot = 1; + let isBranch = 1; + let isIndirectBranch = 1; +} + +// 16-bit Jump and Link (Call) - Short Delay Slot +class JumpLinkRegSMM16<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), + [], IIBranch, FrmR> { + let isCall = 1; + let hasDelaySlot = 1; + let Defs = [RA]; +} + +// 16-bit Jump Register Compact - No delay slot +class JumpRegCMM16<string opstr, RegisterOperand RO> : + MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), + [], IIBranch, FrmR> { + let isTerminator = 1; + let isBarrier = 1; + let isBranch = 1; + let isIndirectBranch = 1; +} + +// MicroMIPS Jump and Link (Call) - Short Delay Slot +let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { + class JumpLinkMM<string opstr, DAGOperand opnd> : + InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), + [], IIBranch, FrmJ, opstr> { + let DecoderMethod = "DecodeJumpTargetMM"; + } + + class JumpLinkRegMM<string opstr, RegisterOperand RO>: + InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), + [], IIBranch, FrmR>; + + class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd, + RegisterOperand RO> : + InstSE<(outs), (ins RO:$rs, opnd:$offset), + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; +} + +class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO, + InstrItinClass Itin = NoItinerary, + SDPatternOperator OpNode = null_frag> : + InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index), + !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>; + +/// A list of registers used by load/store multiple instructions. +def RegListAsmOperand : AsmOperandClass { + let Name = "RegList"; + let ParserMethod = "parseRegisterList"; +} + +def reglist : Operand<i32> { + let EncoderMethod = "getRegisterListOpValue"; + let ParserMatchClass = RegListAsmOperand; + let PrintMethod = "printRegisterList"; + let DecoderMethod = "DecodeRegListOperand"; +} + +class StoreMultMM<string opstr, + InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : + InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { + let DecoderMethod = "DecodeMemMMImm12"; + let mayStore = 1; +} + +class LoadMultMM<string opstr, + InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : + InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { + let DecoderMethod = "DecodeMemMMImm12"; + let mayLoad = 1; +} + +def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, + ARITH_FM_MM16<0>; +def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, + ARITH_FM_MM16<1>; +def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>; +def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, + LOGIC_FM_MM16<0x2>; +def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, + LOGIC_FM_MM16<0x3>; +def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, + LOGIC_FM_MM16<0x1>; +def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>; +def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, + SHIFT_FM_MM16<0>; +def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, + SHIFT_FM_MM16<1>; +def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16; +def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; +def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; +def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>; def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; +def LI16_MM : LoadImmMM16<"li16", simm7, GPRMM16Opnd, immLi16>, + LI_FM_MM16, IsAsCheapAsAMove; def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>; +def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>; +def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>; +def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>; +def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>; class WaitMM<string opstr> : InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmOther, opstr>; let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { + /// Compact Branch Instructions + def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>, + COMPACT_BRANCH_FM_MM<0x7>; + def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>, + COMPACT_BRANCH_FM_MM<0x5>; + /// Arithmetic Instructions (ALU Immediate) def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>, ADDI_FM_MM<0xc>; @@ -179,6 +417,8 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; } + def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>; + def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>; /// Load and Store Instructions - unaligned @@ -191,6 +431,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, LWL_FM_MM<0x9>; + /// Load and Store Instructions - multiple + def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; + def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; + /// Move Conditional def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, NoItinerary>, ADD_FM_MM<0, 0x58>; @@ -247,6 +491,10 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>; def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>; + /// Jump Instructions - Short Delay Slot + def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>; + def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>; + /// Branch Instructions def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>, BEQ_FM_MM<0x25>; @@ -265,6 +513,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>, BGEZAL_FM_MM<0x01>; + /// Branch Instructions - Short Delay Slot + def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x13>; + def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, + GPR32Opnd>, BGEZAL_FM_MM<0x11>; + /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; @@ -295,12 +549,47 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Load-linked, Store-conditional def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>; + + def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>; + def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>; + def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>; + def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; + + def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM; + def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM; } +let Predicates = [InMicroMips] in { + +//===----------------------------------------------------------------------===// +// MicroMips arbitrary patterns that map to one or more instructions +//===----------------------------------------------------------------------===// + +def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm), + (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>; +def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm), + (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>; +def : MipsPat<(add GPR32:$src, immSExt16:$imm), + (ADDiu_MM GPR32:$src, immSExt16:$imm)>; + +def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), + (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>; +def : MipsPat<(and GPR32:$src, immZExt16:$imm), + (ANDi_MM GPR32:$src, immZExt16:$imm)>; + +def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), + (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; +def : MipsPat<(shl GPR32:$src, immZExt5:$imm), + (SLL_MM GPR32:$src, immZExt5:$imm)>; + +def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), + (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; +def : MipsPat<(srl GPR32:$src, immZExt5:$imm), + (SRL_MM GPR32:$src, immZExt5:$imm)>; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// -let Predicates = [InMicroMips] in { def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; } diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index d512d65..87f1b04 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef TARGET_MIPS_H -#define TARGET_MIPS_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS_H +#define LLVM_LIB_TARGET_MIPS_MIPS_H #include "MCTargetDesc/MipsMCTargetDesc.h" #include "llvm/Target/TargetMachine.h" @@ -26,8 +26,6 @@ namespace llvm { FunctionPass *createMipsOptimizePICCallPass(MipsTargetMachine &TM); FunctionPass *createMipsDelaySlotFillerPass(MipsTargetMachine &TM); FunctionPass *createMipsLongBranchPass(MipsTargetMachine &TM); - FunctionPass *createMipsJITCodeEmitterPass(MipsTargetMachine &TM, - JITCodeEmitter &JCE); FunctionPass *createMipsConstantIslandPass(MipsTargetMachine &tm); } // end namespace llvm; diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index dd3bc9b..3e1d047 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -57,6 +57,8 @@ def MipsInstrInfo : InstrInfo; // Mips Subtarget features // //===----------------------------------------------------------------------===// +def FeatureNoABICalls : SubtargetFeature<"noabicalls", "NoABICalls", "true", + "Disable SVR4-style position-independent code.">; def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", @@ -67,13 +69,13 @@ def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true", "IEEE 754-2008 NaN encoding.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", "true", "Only supports single precision float">; -def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", +def FeatureO32 : SubtargetFeature<"o32", "ABI", "MipsABIInfo::O32()", "Enable o32 ABI">; -def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32", +def FeatureN32 : SubtargetFeature<"n32", "ABI", "MipsABIInfo::N32()", "Enable n32 ABI">; -def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64", +def FeatureN64 : SubtargetFeature<"n64", "ABI", "MipsABIInfo::N64()", "Enable n64 ABI">; -def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", +def FeatureEABI : SubtargetFeature<"eabi", "ABI", "MipsABIInfo::EABI()", "Enable eabi ABI">; def FeatureNoOddSPReg : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false", "Disable odd numbered single-precision " diff --git a/lib/Target/Mips/Mips16FrameLowering.cpp b/lib/Target/Mips/Mips16FrameLowering.cpp index 93706c2..6070276 100644 --- a/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/lib/Target/Mips/Mips16FrameLowering.cpp @@ -36,7 +36,7 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); uint64_t StackSize = MFI->getStackSize(); @@ -84,7 +84,7 @@ void Mips16FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo *MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); uint64_t StackSize = MFI->getStackSize(); @@ -154,7 +154,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, Amount = -Amount; const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); TII.adjustStackPtr(Mips::SP, Amount, MBB, I); } @@ -174,7 +174,7 @@ void Mips16FrameLowering:: processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const Mips16InstrInfo *>(MF.getSubtarget().getInstrInfo()); const MipsRegisterInfo &RI = TII.getRegisterInfo(); const BitVector Reserved = RI.getReservedRegs(MF); bool SaveS2 = Reserved[Mips::S2]; diff --git a/lib/Target/Mips/Mips16FrameLowering.h b/lib/Target/Mips/Mips16FrameLowering.h index 1fb7eda..012d558 100644 --- a/lib/Target/Mips/Mips16FrameLowering.h +++ b/lib/Target/Mips/Mips16FrameLowering.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16_FRAMEINFO_H -#define MIPS16_FRAMEINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16FRAMELOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPS16FRAMELOWERING_H #include "MipsFrameLowering.h" diff --git a/lib/Target/Mips/Mips16HardFloat.cpp b/lib/Target/Mips/Mips16HardFloat.cpp index 14055d6..9488e63 100644 --- a/lib/Target/Mips/Mips16HardFloat.cpp +++ b/lib/Target/Mips/Mips16HardFloat.cpp @@ -403,7 +403,7 @@ static bool fixupFPReturnAndCall Attribute::ReadNone); A = A.addAttribute(C, AttributeSet::FunctionIndex, Attribute::NoInline); - Value *F = (M->getOrInsertFunction(Name, A, MyVoid, T, NULL)); + Value *F = (M->getOrInsertFunction(Name, A, MyVoid, T, nullptr)); CallInst::Create(F, Params, "", &Inst ); } else if (const CallInst *CI = dyn_cast<CallInst>(I)) { const Value* V = CI->getCalledValue(); diff --git a/lib/Target/Mips/Mips16HardFloat.h b/lib/Target/Mips/Mips16HardFloat.h index 826887e..19b7bf2 100644 --- a/lib/Target/Mips/Mips16HardFloat.h +++ b/lib/Target/Mips/Mips16HardFloat.h @@ -12,15 +12,14 @@ // //===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOAT_H +#define LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOAT_H + #include "MCTargetDesc/MipsMCTargetDesc.h" #include "MipsTargetMachine.h" #include "llvm/Pass.h" #include "llvm/Target/TargetMachine.h" - -#ifndef MIPS16HARDFLOAT_H -#define MIPS16HARDFLOAT_H - using namespace llvm; namespace llvm { diff --git a/lib/Target/Mips/Mips16HardFloatInfo.h b/lib/Target/Mips/Mips16HardFloatInfo.h index 02444d9..7295c28 100644 --- a/lib/Target/Mips/Mips16HardFloatInfo.h +++ b/lib/Target/Mips/Mips16HardFloatInfo.h @@ -13,8 +13,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16HARDFLOATINFO_H -#define MIPS16HARDFLOATINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOATINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPS16HARDFLOATINFO_H namespace llvm { diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 6672aef..7732be4 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -37,6 +37,7 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" bool Mips16DAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &TM.getSubtarget<MipsSubtarget>(); if (!Subtarget->inMips16Mode()) return false; return MipsDAGToDAGISel::runOnMachineFunction(MF); @@ -71,7 +72,7 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); const TargetRegisterClass *RC = @@ -102,7 +103,7 @@ void Mips16DAGToDAGISel::initMips16SPAliasReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned Mips16SPAliasReg = MipsFI->getMips16SPAliasReg(); @@ -134,8 +135,9 @@ void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) { switch (SD->getMemoryVT().getSizeInBits()) { case 8: case 16: - AliasReg = TM.getFrameLowering()->hasFP(*MF)? - AliasFPReg: getMips16SPAliasReg(); + AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF) + ? AliasFPReg + : getMips16SPAliasReg(); return; } break; @@ -145,8 +147,9 @@ void Mips16DAGToDAGISel::getMips16SPRefReg(SDNode *Parent, SDValue &AliasReg) { switch (SD->getMemoryVT().getSizeInBits()) { case 8: case 16: - AliasReg = TM.getFrameLowering()->hasFP(*MF)? - AliasFPReg: getMips16SPAliasReg(); + AliasReg = TM.getSubtargetImpl()->getFrameLowering()->hasFP(*MF) + ? AliasFPReg + : getMips16SPAliasReg(); return; } break; diff --git a/lib/Target/Mips/Mips16ISelDAGToDAG.h b/lib/Target/Mips/Mips16ISelDAGToDAG.h index e653b39..ae0e61e 100644 --- a/lib/Target/Mips/Mips16ISelDAGToDAG.h +++ b/lib/Target/Mips/Mips16ISelDAGToDAG.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16ISELDAGTODAG_H -#define MIPS16ISELDAGTODAG_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16ISELDAGTODAG_H +#define LLVM_LIB_TARGET_MIPS_MIPS16ISELDAGTODAG_H #include "MipsISelDAGToDAG.h" diff --git a/lib/Target/Mips/Mips16ISelLowering.cpp b/lib/Target/Mips/Mips16ISelLowering.cpp index 81a05df..d4852c4 100644 --- a/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/lib/Target/Mips/Mips16ISelLowering.cpp @@ -12,6 +12,8 @@ //===----------------------------------------------------------------------===// #include "Mips16ISelLowering.h" #include "MCTargetDesc/MipsBaseInfo.h" +#include "Mips16HardFloatInfo.h" +#include "MipsMachineFunction.h" #include "MipsRegisterInfo.h" #include "MipsTargetMachine.h" #include "llvm/ADT/StringRef.h" @@ -27,7 +29,7 @@ using namespace llvm; static cl::opt<bool> DontExpandCondPseudos16( "mips16-dont-expand-cond-pseudo", cl::init(false), - cl::desc("Dont expand conditional move related " + cl::desc("Don't expand conditional move related " "pseudos for Mips 16"), cl::Hidden); @@ -118,13 +120,14 @@ static const Mips16IntrinsicHelperType Mips16IntrinsicHelper[] = { {"truncf", "__mips16_call_stub_sf_1"}, }; -Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) - : MipsTargetLowering(TM) { +Mips16TargetLowering::Mips16TargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI) + : MipsTargetLowering(TM, STI) { // Set up the register classes addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); - if (Subtarget->inMips16HardFloat()) + if (!TM.Options.UseSoftFloat) setMips16HardFloatLibCalls(); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); @@ -150,14 +153,16 @@ Mips16TargetLowering::Mips16TargetLowering(MipsTargetMachine &TM) } const MipsTargetLowering * -llvm::createMips16TargetLowering(MipsTargetMachine &TM) { - return new Mips16TargetLowering(TM); +llvm::createMips16TargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI) { + return new Mips16TargetLowering(TM, STI); } bool -Mips16TargetLowering::allowsUnalignedMemoryAccesses(EVT VT, - unsigned, - bool *Fast) const { +Mips16TargetLowering::allowsMisalignedMemoryAccesses(EVT VT, + unsigned, + unsigned, + bool *Fast) const { return false; } @@ -239,10 +244,9 @@ Mips16TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, } } -bool Mips16TargetLowering:: -isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const { +bool Mips16TargetLowering::isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const { // No tail call optimization for mips16. return false; } @@ -317,7 +321,7 @@ unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber } // -// prefixs are attached to stub numbers depending on the return type . +// Prefixes are attached to stub numbers depending on the return type. // return type: float sf_ // double df_ // single complex sc_ @@ -328,17 +332,16 @@ unsigned int Mips16TargetLowering::getMips16HelperFunctionStubNumber // The full name of a helper function is__mips16_call_stub + // return type dependent prefix + stub number // -// -// This is something that probably should be in a different source file and -// perhaps done differently but my main purpose is to not waste runtime +// FIXME: This is something that probably should be in a different source file +// and perhaps done differently but my main purpose is to not waste runtime // on something that we can enumerate in the source. Another possibility is // to have a python script to generate these mapping tables. This will do // for now. There are a whole series of helper function mapping arrays, one // for each return type class as outlined above. There there are 11 possible -// entries. Ones with 0 are ones which should never be selected +// entries. Ones with 0 are ones which should never be selected. // // All the arrays are similar except for ones which return neither -// sf, df, sc, dc, in which only care about ones which have sf or df as a +// sf, df, sc, dc, in which we only care about ones which have sf or df as a // first parameter. // #define P_ "__mips16_call_stub_" @@ -420,14 +423,15 @@ void Mips16TargetLowering:: getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const { SelectionDAG &DAG = CLI.DAG; MachineFunction &MF = DAG.getMachineFunction(); MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); const char* Mips16HelperFunction = nullptr; bool NeedMips16Helper = false; - if (Subtarget->inMips16HardFloat()) { + if (Subtarget.inMips16HardFloat()) { // // currently we don't have symbols tagged with the mips16 or mips32 // qualifier so we will assume that we don't know what kind it is. @@ -510,14 +514,16 @@ getOpndList(SmallVectorImpl<SDValue> &Ops, Ops.push_back(JumpTarget); MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, - InternalLinkage, CLI, Callee, Chain); + InternalLinkage, IsCallReloc, CLI, Callee, + Chain); } MachineBasicBlock *Mips16TargetLowering:: emitSel16(unsigned Opc, MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -579,7 +585,8 @@ MachineBasicBlock *Mips16TargetLowering::emitSelT16 MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -643,7 +650,8 @@ MachineBasicBlock *Mips16TargetLowering::emitSeliT16 MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the @@ -708,7 +716,8 @@ MachineBasicBlock MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); unsigned regX = MI->getOperand(0).getReg(); unsigned regY = MI->getOperand(1).getReg(); MachineBasicBlock *target = MI->getOperand(2).getMBB(); @@ -724,7 +733,8 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_T8I8I16_ins( MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); unsigned regX = MI->getOperand(0).getReg(); int64_t imm = MI->getOperand(1).getImm(); MachineBasicBlock *target = MI->getOperand(2).getMBB(); @@ -758,7 +768,8 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRX16_ins( MachineInstr *MI, MachineBasicBlock *BB) const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); unsigned CC = MI->getOperand(0).getReg(); unsigned regX = MI->getOperand(1).getReg(); unsigned regY = MI->getOperand(2).getReg(); @@ -775,7 +786,8 @@ MachineBasicBlock *Mips16TargetLowering::emitFEXT_CCRXI16_ins( MachineInstr *MI, MachineBasicBlock *BB )const { if (DontExpandCondPseudos16) return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); unsigned CC = MI->getOperand(0).getReg(); unsigned regX = MI->getOperand(1).getReg(); int64_t Imm = MI->getOperand(2).getImm(); diff --git a/lib/Target/Mips/Mips16ISelLowering.h b/lib/Target/Mips/Mips16ISelLowering.h index 2a5eec5..d3b9f75 100644 --- a/lib/Target/Mips/Mips16ISelLowering.h +++ b/lib/Target/Mips/Mips16ISelLowering.h @@ -11,27 +11,29 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16ISELLOWERING_H -#define MIPS16ISELLOWERING_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H #include "MipsISelLowering.h" namespace llvm { class Mips16TargetLowering : public MipsTargetLowering { public: - explicit Mips16TargetLowering(MipsTargetMachine &TM); + explicit Mips16TargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); - bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace, - bool *Fast) const override; + bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace, + unsigned Align, + bool *Fast) const override; MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override; private: - bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const override; + bool isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const override; void setMips16HardFloatLibCalls(); @@ -45,7 +47,7 @@ namespace llvm { getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const override; MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI, @@ -77,4 +79,4 @@ namespace llvm { }; } -#endif // Mips16ISELLOWERING_H +#endif diff --git a/lib/Target/Mips/Mips16InstrFormats.td b/lib/Target/Mips/Mips16InstrFormats.td index da3a1f1..4ff68be 100644 --- a/lib/Target/Mips/Mips16InstrFormats.td +++ b/lib/Target/Mips/Mips16InstrFormats.td @@ -591,7 +591,7 @@ class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr, bits<3> funct; let funct = _funct; - let I8 = 0b0110; + let I8 = 0b00110; let Inst{26-21} = imm16{10-5}; let Inst{20-16} = imm16{15-11}; diff --git a/lib/Target/Mips/Mips16InstrInfo.cpp b/lib/Target/Mips/Mips16InstrInfo.cpp index 79607de..4dd9af2 100644 --- a/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/lib/Target/Mips/Mips16InstrInfo.cpp @@ -31,9 +31,8 @@ using namespace llvm; #define DEBUG_TYPE "mips16-instrinfo" -Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm) - : MipsInstrInfo(tm, Mips::Bimm16), - RI(*tm.getSubtargetImpl()) {} +Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI) + : MipsInstrInfo(STI, Mips::Bimm16), RI(STI) {} const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { return RI; @@ -44,9 +43,8 @@ const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned Mips16InstrInfo:: -isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const -{ +unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, + int &FrameIndex) const { return 0; } @@ -55,9 +53,8 @@ isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned Mips16InstrInfo:: -isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const -{ +unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr *MI, + int &FrameIndex) const { return 0; } @@ -93,11 +90,12 @@ void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB, MIB.addReg(SrcReg, getKillRegState(KillSrc)); } -void Mips16InstrInfo:: -storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned SrcReg, bool isKill, int FI, - const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, - int64_t Offset) const { +void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned SrcReg, bool isKill, int FI, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + int64_t Offset) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); @@ -110,10 +108,12 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, .addMemOperand(MMO); } -void Mips16InstrInfo:: -loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, - unsigned DestReg, int FI, const TargetRegisterClass *RC, - const TargetRegisterInfo *TRI, int64_t Offset) const { +void Mips16InstrInfo::loadRegFromStack(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + unsigned DestReg, int FI, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + int64_t Offset) const { DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); @@ -171,7 +171,8 @@ unsigned Mips16InstrInfo::getOppositeBranchOpc(unsigned Opc) const { } static void addSaveRestoreRegs(MachineInstrBuilder &MIB, - const std::vector<CalleeSavedInfo> &CSI, unsigned Flags=0) { + const std::vector<CalleeSavedInfo> &CSI, + unsigned Flags = 0) { for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is // RA and return address is taken, because it has already been added in @@ -195,8 +196,8 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB, } // Adjust SP by FrameSize bytes. Save RA, S0, S1 void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); MachineFunction &MF = *MBB.getParent(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -265,9 +266,6 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MachineBasicBlock::iterator I, unsigned Reg1, unsigned Reg2) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); -// MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); -// unsigned Reg1 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass); -// unsigned Reg2 = RegInfo.createVirtualRegister(&Mips::CPU16RegsRegClass); // // li reg1, constant // move reg2, sp @@ -287,9 +285,9 @@ void Mips16InstrInfo::adjustStackPtrBig(unsigned SP, int64_t Amount, MIB4.addReg(Reg1, RegState::Kill); } -void Mips16InstrInfo::adjustStackPtrBigUnrestricted(unsigned SP, int64_t Amount, - MachineBasicBlock &MBB, - MachineBasicBlock::iterator I) const { +void Mips16InstrInfo::adjustStackPtrBigUnrestricted( + unsigned SP, int64_t Amount, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { assert(false && "adjust stack pointer amount exceeded"); } @@ -305,11 +303,10 @@ void Mips16InstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, /// This function generates the sequence of instructions needed to get the /// result of adding register REG and immediate IMM. -unsigned -Mips16InstrInfo::loadImmediate(unsigned FrameReg, - int64_t Imm, MachineBasicBlock &MBB, - MachineBasicBlock::iterator II, DebugLoc DL, - unsigned &NewImm) const { +unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator II, + DebugLoc DL, unsigned &NewImm) const { // // given original instruction is: // Instr rx, T[offset] where offset is too big. @@ -345,7 +342,7 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg, !TargetRegisterInfo::isVirtualRegister(MO.getReg())) Candidates.reset(MO.getReg()); } - // + // If the same register was used and defined in an instruction, then // it will not be in the list of candidates. // @@ -354,7 +351,6 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg, // present as an operand of the instruction. this tells // whether the register is live before the instruction. if it's not // then we don't need to save it in case there are no free registers. - // int DefReg = 0; for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { MachineOperand &MO = II->getOperand(i); @@ -363,9 +359,8 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg, break; } } - // - BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); + BitVector Available = rs.getRegsAvailable(&Mips::CPU16RegsRegClass); Available &= Candidates; // // we use T0 for the first register, if we need to save something away. @@ -374,7 +369,6 @@ Mips16InstrInfo::loadImmediate(unsigned FrameReg, unsigned FirstRegSaved =0, SecondRegSaved=0; unsigned FirstRegSavedTo = 0, SecondRegSavedTo = 0; - Reg = Available.find_first(); if (Reg == -1) { @@ -442,7 +436,6 @@ void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB, BuildMI(MBB, I, I->getDebugLoc(), get(Opc)); } - const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const { if (validSpImm8(Imm)) return get(Mips::AddiuSpImm16); @@ -456,8 +449,8 @@ void Mips16InstrInfo::BuildAddiuSpImm BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm); } -const MipsInstrInfo *llvm::createMips16InstrInfo(MipsTargetMachine &TM) { - return new Mips16InstrInfo(TM); +const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) { + return new Mips16InstrInfo(STI); } bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg, @@ -497,7 +490,6 @@ bool Mips16InstrInfo::validImmediate(unsigned Opcode, unsigned Reg, unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str, const MCAsmInfo &MAI) const { - // Count the number of instructions in the asm. bool atInsnStart = true; unsigned Length = 0; diff --git a/lib/Target/Mips/Mips16InstrInfo.h b/lib/Target/Mips/Mips16InstrInfo.h index 0dc0046..e7d0c07 100644 --- a/lib/Target/Mips/Mips16InstrInfo.h +++ b/lib/Target/Mips/Mips16InstrInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16INSTRUCTIONINFO_H -#define MIPS16INSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPS16INSTRINFO_H #include "Mips16RegisterInfo.h" #include "MipsInstrInfo.h" @@ -23,7 +23,7 @@ class Mips16InstrInfo : public MipsInstrInfo { const Mips16RegisterInfo RI; public: - explicit Mips16InstrInfo(MipsTargetMachine &TM); + explicit Mips16InstrInfo(const MipsSubtarget &STI); const MipsRegisterInfo &getRegisterInfo() const override; diff --git a/lib/Target/Mips/Mips16InstrInfo.td b/lib/Target/Mips/Mips16InstrInfo.td index 5e4eebb..2364f4d 100644 --- a/lib/Target/Mips/Mips16InstrInfo.td +++ b/lib/Target/Mips/Mips16InstrInfo.td @@ -1771,9 +1771,9 @@ def: Mips16Pat // // For constants, llvm transforms this to: -// x > (k -1) and then reverses the operands to use setlt. So this pattern +// x > (k - 1) and then reverses the operands to use setlt. So this pattern // is not used now by the compiler. (Presumably checking that k-1 does not -// overflow). The compiler never uses this at a the current time, due to +// overflow). The compiler never uses this at the current time, due to // other optimizations. // //def: Mips16Pat diff --git a/lib/Target/Mips/Mips16RegisterInfo.cpp b/lib/Target/Mips/Mips16RegisterInfo.cpp index dbee774..0bb452a 100644 --- a/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -65,7 +65,7 @@ bool Mips16RegisterInfo::saveScavengerRegister const TargetRegisterClass *RC, unsigned Reg) const { DebugLoc DL; - const TargetInstrInfo &TII = *MBB.getParent()->getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MBB.getParent()->getSubtarget().getInstrInfo(); TII.copyPhysReg(MBB, I, DL, Mips::T0, Reg, true); TII.copyPhysReg(MBB, UseMI, DL, Reg, Mips::T0, true); return true; @@ -106,7 +106,7 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, if (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) FrameReg = Mips::SP; else { - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (TFI->hasFP(MF)) { FrameReg = Mips::S0; } @@ -140,8 +140,8 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, DebugLoc DL = II->getDebugLoc(); unsigned NewImm; const Mips16InstrInfo &TII = - *static_cast<const Mips16InstrInfo*>( - MBB.getParent()->getTarget().getInstrInfo()); + *static_cast<const Mips16InstrInfo *>( + MBB.getParent()->getSubtarget().getInstrInfo()); FrameReg = TII.loadImmediate(FrameReg, Offset, MBB, II, DL, NewImm); Offset = SignExtend64<16>(NewImm); IsKill = true; diff --git a/lib/Target/Mips/Mips16RegisterInfo.h b/lib/Target/Mips/Mips16RegisterInfo.h index f59f1a7..3cdf836 100644 --- a/lib/Target/Mips/Mips16RegisterInfo.h +++ b/lib/Target/Mips/Mips16RegisterInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS16REGISTERINFO_H -#define MIPS16REGISTERINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPS16REGISTERINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPS16REGISTERINFO_H #include "MipsRegisterInfo.h" diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index e4ec96a..e9a4289 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -403,7 +403,7 @@ class JMP_IDX_COMPACT_FM<bits<6> funct> : MipsR6Inst { bits<32> Inst; let Inst{31-26} = funct; - let Inst{25-21} = 0b000000; + let Inst{25-21} = 0b00000; let Inst{20-16} = rt; let Inst{15-0} = offset; } diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index d06e5ca..6d6735b 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -796,8 +796,8 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i32:$t, i32:$f), (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>, ISA_MIPS32R6; def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i32:$t, i32:$f), - (OR (SELNEZ i32:$f, (XORi i32:$cond, immZExt16:$imm)), - (SELEQZ i32:$t, (XORi i32:$cond, immZExt16:$imm)))>, + (OR (SELNEZ i32:$t, (XORi i32:$cond, immZExt16:$imm)), + (SELEQZ i32:$f, (XORi i32:$cond, immZExt16:$imm)))>, ISA_MIPS32R6; def : MipsPat<(select (i32 (setgt i32:$cond, immSExt16Plus1:$imm)), i32:$t, i32:$f), diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index f0b6814..4e2dcd8 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -419,6 +419,10 @@ defm : SetgePats<GPR64, SLT64, SLTu64>; defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; // truncate +def : MipsPat<(trunc (assertsext GPR64:$src)), + (EXTRACT_SUBREG GPR64:$src, sub_32)>; +def : MipsPat<(trunc (assertzext GPR64:$src)), + (EXTRACT_SUBREG GPR64:$src, sub_32)>; def : MipsPat<(i32 (trunc GPR64:$src)), (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>; @@ -442,28 +446,22 @@ def : MipsInstAlias<"move $dst, $src", GPR_64; def : MipsInstAlias<"daddu $rs, $rt, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), - 0>; + 0>, ISA_MIPS3; def : MipsInstAlias<"dadd $rs, $rt, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 0>, ISA_MIPS3_NOT_32R6_64R6; def : MipsInstAlias<"daddu $rs, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), - 0>; + 0>, ISA_MIPS3; def : MipsInstAlias<"dadd $rs, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm), 0>, ISA_MIPS3_NOT_32R6_64R6; -def : MipsInstAlias<"add $rs, $imm", - (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), - 0>; -def : MipsInstAlias<"addu $rs, $imm", - (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), - 0>; def : MipsInstAlias<"dsll $rd, $rt, $rs", (DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS3; def : MipsInstAlias<"dsubu $rt, $rs, $imm", (DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs, - InvertedImOperand64:$imm), 0>; + InvertedImOperand64:$imm), 0>, ISA_MIPS3; def : MipsInstAlias<"dsubi $rs, $rt, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, InvertedImOperand64:$imm), @@ -483,7 +481,7 @@ def : MipsInstAlias<"dsub $rs, $imm", def : MipsInstAlias<"dsubu $rs, $imm", (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm), - 0>; + 0>, ISA_MIPS3; def : MipsInstAlias<"dsra $rd, $rt, $rs", (DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS3; @@ -510,3 +508,9 @@ def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0 def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; +let Predicates = [HasMips64, HasCnMips] in { +def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>; +def : MipsInstAlias<"syncs", (SYNC 0x6), 0>; +def : MipsInstAlias<"syncw", (SYNC 0x4), 0>; +def : MipsInstAlias<"syncws", (SYNC 0x5), 0>; +} diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index 63cf60b..6b546e8 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -191,9 +191,9 @@ def : MipsPat<(select (i32 (seteq i32:$cond, immZExt16:$imm)), i64:$t, i64:$f), immZExt16:$imm))))>, ISA_MIPS64R6; def : MipsPat<(select (i32 (setne i32:$cond, immZExt16:$imm)), i64:$t, i64:$f), - (OR64 (SELNEZ64 i64:$f, (SLL64_32 (XORi i32:$cond, + (OR64 (SELNEZ64 i64:$t, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))), - (SELEQZ64 i64:$t, (SLL64_32 (XORi i32:$cond, + (SELEQZ64 i64:$f, (SLL64_32 (XORi i32:$cond, immZExt16:$imm))))>, ISA_MIPS64R6; diff --git a/lib/Target/Mips/MipsABIInfo.cpp b/lib/Target/Mips/MipsABIInfo.cpp new file mode 100644 index 0000000..f885369 --- /dev/null +++ b/lib/Target/Mips/MipsABIInfo.cpp @@ -0,0 +1,45 @@ +//===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MipsABIInfo.h" +#include "MipsRegisterInfo.h" + +using namespace llvm; + +namespace { +static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3}; + +static const MCPhysReg Mips64IntRegs[8] = { + Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, + Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}; +} + +const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const { + if (IsO32()) + return makeArrayRef(O32IntRegs); + if (IsN32() || IsN64()) + return makeArrayRef(Mips64IntRegs); + llvm_unreachable("Unhandled ABI"); +} + +const ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const { + if (IsO32()) + return makeArrayRef(O32IntRegs); + if (IsN32() || IsN64()) + return makeArrayRef(Mips64IntRegs); + llvm_unreachable("Unhandled ABI"); +} + +unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const { + if (IsO32()) + return CC != CallingConv::Fast ? 16 : 0; + if (IsN32() || IsN64() || IsEABI()) + return 0; + llvm_unreachable("Unhandled ABI"); +} diff --git a/lib/Target/Mips/MipsABIInfo.h b/lib/Target/Mips/MipsABIInfo.h new file mode 100644 index 0000000..bea585e --- /dev/null +++ b/lib/Target/Mips/MipsABIInfo.h @@ -0,0 +1,61 @@ +//===---- MipsABIInfo.h - Information about MIPS ABI's --------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSABIINFO_H +#define MIPSABIINFO_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/MC/MCRegisterInfo.h" +#include "llvm/IR/CallingConv.h" + +namespace llvm { + +class MipsABIInfo { +public: + enum class ABI { Unknown, O32, N32, N64, EABI }; + +protected: + ABI ThisABI; + +public: + MipsABIInfo(ABI ThisABI) : ThisABI(ThisABI) {} + + static MipsABIInfo Unknown() { return MipsABIInfo(ABI::Unknown); } + static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); } + static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); } + static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); } + static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); } + + bool IsKnown() const { return ThisABI != ABI::Unknown; } + bool IsO32() const { return ThisABI == ABI::O32; } + bool IsN32() const { return ThisABI == ABI::N32; } + bool IsN64() const { return ThisABI == ABI::N64; } + bool IsEABI() const { return ThisABI == ABI::EABI; } + ABI GetEnumValue() const { return ThisABI; } + + /// The registers to use for byval arguments. + const ArrayRef<MCPhysReg> GetByValArgRegs() const; + + /// The registers to use for the variable argument list. + const ArrayRef<MCPhysReg> GetVarArgRegs() const; + + /// Obtain the size of the area allocated by the callee for arguments. + /// CallingConv::FastCall affects the value for O32. + unsigned GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const; + + /// Ordering of ABI's + /// MipsGenSubtargetInfo.inc will use this to resolve conflicts when given + /// multiple ABI options. + bool operator<(const MipsABIInfo Other) const { + return ThisABI < Other.GetEnumValue(); + } +}; +} + +#endif diff --git a/lib/Target/Mips/MipsAnalyzeImmediate.cpp b/lib/Target/Mips/MipsAnalyzeImmediate.cpp index 31a9b7d..161345d 100644 --- a/lib/Target/Mips/MipsAnalyzeImmediate.cpp +++ b/lib/Target/Mips/MipsAnalyzeImmediate.cpp @@ -72,7 +72,8 @@ void MipsAnalyzeImmediate::GetInstSeqLs(uint64_t Imm, unsigned RemSize, if (Imm & 0x8000) { InstSeqLs SeqLsORi; GetInstSeqLsORi(Imm, RemSize, SeqLsORi); - SeqLs.insert(SeqLs.end(), SeqLsORi.begin(), SeqLsORi.end()); + SeqLs.append(std::make_move_iterator(SeqLsORi.begin()), + std::make_move_iterator(SeqLsORi.end())); } } diff --git a/lib/Target/Mips/MipsAnalyzeImmediate.h b/lib/Target/Mips/MipsAnalyzeImmediate.h index cc09034..ae3c38c 100644 --- a/lib/Target/Mips/MipsAnalyzeImmediate.h +++ b/lib/Target/Mips/MipsAnalyzeImmediate.h @@ -6,8 +6,8 @@ // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// -#ifndef MIPS_ANALYZE_IMMEDIATE_H -#define MIPS_ANALYZE_IMMEDIATE_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H +#define LLVM_LIB_TARGET_MIPS_MIPSANALYZEIMMEDIATE_H #include "llvm/ADT/SmallVector.h" #include "llvm/Support/DataTypes.h" diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 1fb75a2..832fa05 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -58,10 +58,12 @@ MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() { } bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &TM.getSubtarget<MipsSubtarget>(); + // Initialize TargetLoweringObjectFile. - if (Subtarget->allowMixed16_32()) - const_cast<TargetLoweringObjectFile&>(getObjFileLowering()) + const_cast<TargetLoweringObjectFile &>(getObjFileLowering()) .Initialize(OutContext, TM); + MipsFI = MF.getInfo<MipsFunctionInfo>(); if (Subtarget->inMips16Mode()) for (std::map< @@ -129,7 +131,7 @@ void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer, void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { MipsTargetStreamer &TS = getTargetStreamer(); - TS.setCanHaveModuleDir(false); + TS.forbidModuleDirective(); if (MI->isDebugValue()) { SmallString<128> Str; @@ -264,7 +266,8 @@ void MipsAsmPrinter::printSavedRegsBitmask() { if (Mips::GPR32RegClass.contains(Reg)) break; - unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); + unsigned RegNum = + TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg); if (Mips::AFGR64RegClass.contains(Reg)) { FPUBitmask |= (3 << RegNum); CSFPRegsSize += AFGR64RegSize; @@ -279,7 +282,8 @@ void MipsAsmPrinter::printSavedRegsBitmask() { // Set CPU Bitmask. for (; i != e; ++i) { unsigned Reg = CSI[i].getReg(); - unsigned RegNum = TM.getRegisterInfo()->getEncodingValue(Reg); + unsigned RegNum = + TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(Reg); CPUBitmask |= (1 << RegNum); } @@ -304,7 +308,7 @@ void MipsAsmPrinter::printSavedRegsBitmask() { /// Frame Directive void MipsAsmPrinter::emitFrameDirective() { - const TargetRegisterInfo &RI = *TM.getRegisterInfo(); + const TargetRegisterInfo &RI = *TM.getSubtargetImpl()->getRegisterInfo(); unsigned stackReg = RI.getFrameRegister(*MF); unsigned returnReg = RI.getRARegister(); @@ -315,11 +319,11 @@ void MipsAsmPrinter::emitFrameDirective() { /// Emit Set directives. const char *MipsAsmPrinter::getCurrentABIString() const { - switch (Subtarget->getTargetABI()) { - case MipsSubtarget::O32: return "abi32"; - case MipsSubtarget::N32: return "abiN32"; - case MipsSubtarget::N64: return "abi64"; - case MipsSubtarget::EABI: return "eabi32"; // TODO: handle eabi64 + switch (Subtarget->getABI().GetEnumValue()) { + case MipsABIInfo::ABI::O32: return "abi32"; + case MipsABIInfo::ABI::N32: return "abiN32"; + case MipsABIInfo::ABI::N64: return "abi64"; + case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64 default: llvm_unreachable("Unknown Mips ABI"); } } @@ -469,14 +473,12 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, return false; case 'z': { // $0 if zero, regular printing otherwise - if (MO.getType() != MachineOperand::MO_Immediate) - return true; - int64_t Val = MO.getImm(); - if (Val) - O << Val; - else + if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) { O << "$0"; - return false; + return false; + } + // If not, call printOperand as normal. + break; } case 'D': // Second part of a double word register operand case 'L': // Low order register of a double word register operand @@ -558,7 +560,7 @@ bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { - const DataLayout *DL = TM.getDataLayout(); + const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout(); const MachineOperand &MO = MI->getOperand(opNum); bool closeP = false; @@ -643,6 +645,18 @@ printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { // Load/Store memory operands -- imm($reg) // If PIC target the target is loaded as the // pattern lw $25,%call16($28) + + // opNum can be invalid if instruction has reglist as operand. + // MemOperand is always last operand of instruction (base + offset). + switch (MI->getOpcode()) { + default: + break; + case Mips::SWM32_MM: + case Mips::LWM32_MM: + opNum = MI->getNumOperands() - 2; + break; + } + printOperand(MI, opNum+1, O); O << "("; printOperand(MI, opNum, O); @@ -666,13 +680,19 @@ printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); } +void MipsAsmPrinter:: +printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { + for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) { + if (i != opNum) O << ", "; + printOperand(MI, i, O); + } +} + void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { - // TODO: Need to add -mabicalls and -mno-abicalls flags. - // Currently we assume that -mabicalls is the default. - bool IsABICalls = true; + bool IsABICalls = Subtarget->isABICalls(); if (IsABICalls) { getTargetStreamer().emitDirectiveAbiCalls(); - Reloc::Model RM = Subtarget->getRelocationModel(); + Reloc::Model RM = TM.getRelocationModel(); // FIXME: This condition should be a lot more complicated that it is here. // Ideally it should test for properties of the ABI and not the ABI // itself. @@ -706,9 +726,19 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { } getTargetStreamer().updateABIInfo(*Subtarget); - getTargetStreamer().emitDirectiveModuleFP(); - if (Subtarget->isABI_O32()) + // We should always emit a '.module fp=...' but binutils 2.24 does not accept + // it. We therefore emit it when it contradicts the ABI defaults (-mfpxx or + // -mfp64) and omit it otherwise. + if (Subtarget->isABI_O32() && (Subtarget->isABI_FPXX() || + Subtarget->isFP64bit())) + getTargetStreamer().emitDirectiveModuleFP(); + + // We should always emit a '.module [no]oddspreg' but binutils 2.24 does not + // accept it. We therefore emit it when it contradicts the default or an + // option has changed the default (i.e. FPXX) and omit it otherwise. + if (Subtarget->isABI_O32() && (!Subtarget->useOddSPReg() || + Subtarget->isABI_FPXX())) getTargetStreamer().emitDirectiveModuleOddSPReg(Subtarget->useOddSPReg(), Subtarget->isABI_O32()); } diff --git a/lib/Target/Mips/MipsAsmPrinter.h b/lib/Target/Mips/MipsAsmPrinter.h index 967aa0b..0582e21 100644 --- a/lib/Target/Mips/MipsAsmPrinter.h +++ b/lib/Target/Mips/MipsAsmPrinter.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSASMPRINTER_H -#define MIPSASMPRINTER_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H +#define LLVM_LIB_TARGET_MIPS_MIPSASMPRINTER_H #include "Mips16HardFloatInfo.h" #include "MipsMCInstLower.h" @@ -89,11 +89,14 @@ public: const MipsFunctionInfo *MipsFI; MipsMCInstLower MCInstLowering; - explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) - : AsmPrinter(TM, Streamer), MCP(nullptr), InConstantPool(false), - MCInstLowering(*this) { - Subtarget = &TM.getSubtarget<MipsSubtarget>(); - } + // We initialize the subtarget here and in runOnMachineFunction + // since there are certain target specific flags (ABI) that could + // reside on the TargetMachine, but are on the subtarget currently + // and we need them for the beginning of file output before we've + // seen a single function. + explicit MipsAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) + : AsmPrinter(TM, Streamer), MCP(nullptr), InConstantPool(false), + Subtarget(&TM.getSubtarget<MipsSubtarget>()), MCInstLowering(*this) {} const char *getPassName() const override { return "Mips Assembly Printer"; @@ -131,6 +134,7 @@ public: void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, const char *Modifier = nullptr); + void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O); void EmitStartOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); diff --git a/lib/Target/Mips/MipsCCState.cpp b/lib/Target/Mips/MipsCCState.cpp new file mode 100644 index 0000000..e18cc8b --- /dev/null +++ b/lib/Target/Mips/MipsCCState.cpp @@ -0,0 +1,142 @@ +//===---- MipsCCState.cpp - CCState with Mips specific extensions ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MipsCCState.h" +#include "MipsSubtarget.h" +#include "llvm/IR/Module.h" + +using namespace llvm; + +/// This function returns true if CallSym is a long double emulation routine. +static bool isF128SoftLibCall(const char *CallSym) { + const char *const LibCalls[] = { + "__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", + "__extendsftf2", "__fixtfdi", "__fixtfsi", "__fixtfti", + "__fixunstfdi", "__fixunstfsi", "__fixunstfti", "__floatditf", + "__floatsitf", "__floattitf", "__floatunditf", "__floatunsitf", + "__floatuntitf", "__getf2", "__gttf2", "__letf2", + "__lttf2", "__multf3", "__netf2", "__powitf2", + "__subtf3", "__trunctfdf2", "__trunctfsf2", "__unordtf2", + "ceill", "copysignl", "cosl", "exp2l", + "expl", "floorl", "fmal", "fmodl", + "log10l", "log2l", "logl", "nearbyintl", + "powl", "rintl", "sinl", "sqrtl", + "truncl"}; + + const char *const *End = LibCalls + array_lengthof(LibCalls); + + // Check that LibCalls is sorted alphabetically. + MipsTargetLowering::LTStr Comp; + +#ifndef NDEBUG + for (const char *const *I = LibCalls; I < End - 1; ++I) + assert(Comp(*I, *(I + 1))); +#endif + + return std::binary_search(LibCalls, End, CallSym, Comp); +} + +/// This function returns true if Ty is fp128, {f128} or i128 which was +/// originally a fp128. +static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { + if (Ty->isFP128Ty()) + return true; + + if (Ty->isStructTy() && Ty->getStructNumElements() == 1 && + Ty->getStructElementType(0)->isFP128Ty()) + return true; + + const ExternalSymbolSDNode *ES = + dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); + + // If the Ty is i128 and the function being called is a long double emulation + // routine, then the original type is f128. + return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); +} + +MipsCCState::SpecialCallingConvType +MipsCCState::getSpecialCallingConvForCallee(const SDNode *Callee, + const MipsSubtarget &Subtarget) { + MipsCCState::SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv; + if (Subtarget.inMips16HardFloat()) { + if (const GlobalAddressSDNode *G = + dyn_cast<const GlobalAddressSDNode>(Callee)) { + llvm::StringRef Sym = G->getGlobal()->getName(); + Function *F = G->getGlobal()->getParent()->getFunction(Sym); + if (F && F->hasFnAttribute("__Mips16RetHelper")) { + SpecialCallingConv = Mips16RetHelperConv; + } + } + } + return SpecialCallingConv; +} + +void MipsCCState::PreAnalyzeCallResultForF128( + const SmallVectorImpl<ISD::InputArg> &Ins, + const TargetLowering::CallLoweringInfo &CLI) { + for (unsigned i = 0; i < Ins.size(); ++i) { + OriginalArgWasF128.push_back( + originalTypeIsF128(CLI.RetTy, CLI.Callee.getNode())); + OriginalArgWasFloat.push_back(CLI.RetTy->isFloatingPointTy()); + } +} + +/// Identify lowered values that originated from f128 arguments and record +/// this for use by RetCC_MipsN. +void MipsCCState::PreAnalyzeReturnForF128( + const SmallVectorImpl<ISD::OutputArg> &Outs) { + const MachineFunction &MF = getMachineFunction(); + for (unsigned i = 0; i < Outs.size(); ++i) { + OriginalArgWasF128.push_back( + originalTypeIsF128(MF.getFunction()->getReturnType(), nullptr)); + OriginalArgWasFloat.push_back( + MF.getFunction()->getReturnType()->isFloatingPointTy()); + } +} + +/// Identify lowered values that originated from f128 arguments and record +/// this. +void MipsCCState::PreAnalyzeCallOperands( + const SmallVectorImpl<ISD::OutputArg> &Outs, + std::vector<TargetLowering::ArgListEntry> &FuncArgs, + const SDNode *CallNode) { + for (unsigned i = 0; i < Outs.size(); ++i) { + OriginalArgWasF128.push_back( + originalTypeIsF128(FuncArgs[Outs[i].OrigArgIndex].Ty, CallNode)); + OriginalArgWasFloat.push_back( + FuncArgs[Outs[i].OrigArgIndex].Ty->isFloatingPointTy()); + CallOperandIsFixed.push_back(Outs[i].IsFixed); + } +} + +/// Identify lowered values that originated from f128 arguments and record +/// this. +void MipsCCState::PreAnalyzeFormalArgumentsForF128( + const SmallVectorImpl<ISD::InputArg> &Ins) { + const MachineFunction &MF = getMachineFunction(); + for (unsigned i = 0; i < Ins.size(); ++i) { + Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin(); + + // SRet arguments cannot originate from f128 or {f128} returns so we just + // push false. We have to handle this specially since SRet arguments + // aren't mapped to an original argument. + if (Ins[i].Flags.isSRet()) { + OriginalArgWasF128.push_back(false); + OriginalArgWasFloat.push_back(false); + continue; + } + + assert(Ins[i].OrigArgIndex < MF.getFunction()->arg_size()); + std::advance(FuncArg, Ins[i].OrigArgIndex); + + OriginalArgWasF128.push_back( + originalTypeIsF128(FuncArg->getType(), nullptr)); + OriginalArgWasFloat.push_back(FuncArg->getType()->isFloatingPointTy()); + } +} diff --git a/lib/Target/Mips/MipsCCState.h b/lib/Target/Mips/MipsCCState.h new file mode 100644 index 0000000..cc4531d --- /dev/null +++ b/lib/Target/Mips/MipsCCState.h @@ -0,0 +1,136 @@ +//===---- MipsCCState.h - CCState with Mips specific extensions -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef MIPSCCSTATE_H +#define MIPSCCSTATE_H + +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/CallingConvLower.h" +#include "MipsISelLowering.h" + +namespace llvm { +class SDNode; +class MipsSubtarget; + +class MipsCCState : public CCState { +public: + enum SpecialCallingConvType { Mips16RetHelperConv, NoSpecialCallingConv }; + + /// Determine the SpecialCallingConvType for the given callee + static SpecialCallingConvType + getSpecialCallingConvForCallee(const SDNode *Callee, + const MipsSubtarget &Subtarget); + +private: + /// Identify lowered values that originated from f128 arguments and record + /// this for use by RetCC_MipsN. + void PreAnalyzeCallResultForF128(const SmallVectorImpl<ISD::InputArg> &Ins, + const TargetLowering::CallLoweringInfo &CLI); + + /// Identify lowered values that originated from f128 arguments and record + /// this for use by RetCC_MipsN. + void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs); + + /// Identify lowered values that originated from f128 arguments and record + /// this. + void + PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, + std::vector<TargetLowering::ArgListEntry> &FuncArgs, + const SDNode *CallNode); + + /// Identify lowered values that originated from f128 arguments and record + /// this. + void + PreAnalyzeFormalArgumentsForF128(const SmallVectorImpl<ISD::InputArg> &Ins); + + /// Records whether the value has been lowered from an f128. + SmallVector<bool, 4> OriginalArgWasF128; + + /// Records whether the value has been lowered from float. + SmallVector<bool, 4> OriginalArgWasFloat; + + /// Records whether the value was a fixed argument. + /// See ISD::OutputArg::IsFixed, + SmallVector<bool, 4> CallOperandIsFixed; + + // Used to handle MIPS16-specific calling convention tweaks. + // FIXME: This should probably be a fully fledged calling convention. + SpecialCallingConvType SpecialCallingConv; + +public: + MipsCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, + SmallVectorImpl<CCValAssign> &locs, LLVMContext &C, + SpecialCallingConvType SpecialCC = NoSpecialCallingConv) + : CCState(CC, isVarArg, MF, locs, C), SpecialCallingConv(SpecialCC) {} + + void + AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, + CCAssignFn Fn, + std::vector<TargetLowering::ArgListEntry> &FuncArgs, + const SDNode *CallNode) { + PreAnalyzeCallOperands(Outs, FuncArgs, CallNode); + CCState::AnalyzeCallOperands(Outs, Fn); + OriginalArgWasF128.clear(); + OriginalArgWasFloat.clear(); + CallOperandIsFixed.clear(); + } + + // The AnalyzeCallOperands in the base class is not usable since we must + // provide a means of accessing ArgListEntry::IsFixed. Delete them from this + // class. This doesn't stop them being used via the base class though. + void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, + CCAssignFn Fn) LLVM_DELETED_FUNCTION; + void AnalyzeCallOperands(const SmallVectorImpl<MVT> &Outs, + SmallVectorImpl<ISD::ArgFlagsTy> &Flags, + CCAssignFn Fn) LLVM_DELETED_FUNCTION; + + void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, + CCAssignFn Fn) { + PreAnalyzeFormalArgumentsForF128(Ins); + CCState::AnalyzeFormalArguments(Ins, Fn); + OriginalArgWasFloat.clear(); + OriginalArgWasF128.clear(); + } + + void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, + CCAssignFn Fn, + const TargetLowering::CallLoweringInfo &CLI) { + PreAnalyzeCallResultForF128(Ins, CLI); + CCState::AnalyzeCallResult(Ins, Fn); + OriginalArgWasFloat.clear(); + OriginalArgWasF128.clear(); + } + + void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, + CCAssignFn Fn) { + PreAnalyzeReturnForF128(Outs); + CCState::AnalyzeReturn(Outs, Fn); + OriginalArgWasFloat.clear(); + OriginalArgWasF128.clear(); + } + + bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, + CCAssignFn Fn) { + PreAnalyzeReturnForF128(ArgsFlags); + bool Return = CCState::CheckReturn(ArgsFlags, Fn); + OriginalArgWasFloat.clear(); + OriginalArgWasF128.clear(); + return Return; + } + + bool WasOriginalArgF128(unsigned ValNo) { return OriginalArgWasF128[ValNo]; } + bool WasOriginalArgFloat(unsigned ValNo) { + return OriginalArgWasFloat[ValNo]; + } + bool IsCallOperandFixed(unsigned ValNo) { return CallOperandIsFixed[ValNo]; } + SpecialCallingConvType getSpecialCallingConv() { return SpecialCallingConv; } +}; +} + +#endif diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td index 007213c..7318de2 100644 --- a/lib/Target/Mips/MipsCallingConv.td +++ b/lib/Target/Mips/MipsCallingConv.td @@ -10,13 +10,60 @@ //===----------------------------------------------------------------------===// /// CCIfSubtarget - Match if the current subtarget has a feature F. -class CCIfSubtarget<string F, CCAction A>: - CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; +class CCIfSubtarget<string F, CCAction A, string Invert = ""> + : CCIf<!strconcat(Invert, + "static_cast<const MipsSubtarget&>" + "(State.getMachineFunction().getSubtarget()).", + F), + A>; + +// The inverse of CCIfSubtarget +class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">; + +// For soft-float, f128 values are returned in A0_64 rather than V1_64. +def RetCC_F128SoftFloat : CallingConv<[ + CCAssignToReg<[V0_64, A0_64]> +]>; + +// For hard-float, f128 values are returned as a pair of f64's rather than a +// pair of i64's. +def RetCC_F128HardFloat : CallingConv<[ + CCBitConvertToType<f64>, + + // Contrary to the ABI documentation, a struct containing a long double is + // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to + // match the de facto ABI as implemented by GCC. + CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>, + + CCAssignToReg<[D0_64, D2_64]> +]>; + +// Handle F128 specially since we can't identify the original type during the +// tablegen-erated code. +def RetCC_F128 : CallingConv<[ + CCIfSubtarget<"abiUsesSoftFloat()", + CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, + CCIfSubtargetNot<"abiUsesSoftFloat()", + CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> +]>; //===----------------------------------------------------------------------===// // Mips O32 Calling Convention //===----------------------------------------------------------------------===// +def CC_MipsO32 : CallingConv<[ + // Promote i8/i16 arguments to i32. + CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, + + // Integer values get stored in stack slots that are 4 bytes in + // size and 4-byte aligned. + CCIfType<[i32, f32], CCAssignToStack<4, 4>>, + + // Integer values get stored in stack slots that are 8 bytes in + // size and 8-byte aligned. + CCIfType<[f64], CCAssignToStack<8, 8>> +]>; + // Only the return rules are defined here for O32. The rules for argument // passing are defined in MipsISelLowering.cpp. def RetCC_MipsO32 : CallingConv<[ @@ -26,26 +73,46 @@ def RetCC_MipsO32 : CallingConv<[ // f32 are returned in registers F0, F2 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, - // f64 arguments are returned in D0_64 and D1_64 in FP64bit mode or + // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or // in D0 and D1 in FP32bit mode. - CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D1_64]>>>, - CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", CCAssignToReg<[D0, D1]>>> + CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, + CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> +]>; + +def CC_MipsO32_FP32 : CustomCallingConv; +def CC_MipsO32_FP64 : CustomCallingConv; + +def CC_MipsO32_FP : CallingConv<[ + CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, + CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> ]>; //===----------------------------------------------------------------------===// // Mips N32/64 Calling Convention //===----------------------------------------------------------------------===// +def CC_MipsN_SoftFloat : CallingConv<[ + CCAssignToRegWithShadow<[A0, A1, A2, A3, + T0, T1, T2, T3], + [D12_64, D13_64, D14_64, D15_64, + D16_64, D17_64, D18_64, D19_64]>, + CCAssignToStack<4, 8> +]>; + def CC_MipsN : CallingConv<[ - // Promote i8/i16 arguments to i32. - CCIfType<[i8, i16], CCPromoteToType<i32>>, + CCIfType<[i8, i16, i32], + CCIfSubtargetNot<"isLittle()", + CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, - // Integer arguments are passed in integer registers. - CCIfType<[i32], CCAssignToRegWithShadow<[A0, A1, A2, A3, - T0, T1, T2, T3], - [F12, F13, F14, F15, - F16, F17, F18, F19]>>, + // All integers (except soft-float integers) are promoted to 64-bit. + CCIfType<[i8, i16, i32], + CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)", + CCPromoteToType<i64>>>, + + // The only i32's we have left are soft-float arguments. + CCIfSubtarget<"abiUsesSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, + // Integer arguments are passed in integer registers. CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, T2_64, T3_64], [D12_64, D13_64, D14_64, D15_64, @@ -64,29 +131,49 @@ def CC_MipsN : CallingConv<[ T0_64, T1_64, T2_64, T3_64]>>, // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. - CCIfType<[i32, f32], CCAssignToStack<4, 8>>, + CCIfType<[f32], CCAssignToStack<4, 8>>, CCIfType<[i64, f64], CCAssignToStack<8, 8>> ]>; // N32/64 variable arguments. // All arguments are passed in integer registers. def CC_MipsN_VarArg : CallingConv<[ - // Promote i8/i16 arguments to i32. - CCIfType<[i8, i16], CCPromoteToType<i32>>, + // All integers are promoted to 64-bit. + CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, - CCIfType<[i32, f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, + CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, T2_64, T3_64]>>, // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. - CCIfType<[i32, f32], CCAssignToStack<4, 8>>, + CCIfType<[f32], CCAssignToStack<4, 8>>, CCIfType<[i64, f64], CCAssignToStack<8, 8>> ]>; def RetCC_MipsN : CallingConv<[ - // i32 are returned in registers V0, V1 - CCIfType<[i32], CCAssignToReg<[V0, V1]>>, + // f128 needs to be handled similarly to f32 and f64. However, f128 is not + // legal and is lowered to i128 which is further lowered to a pair of i64's. + // This presents us with a problem for the calling convention since hard-float + // still needs to pass them in FPU registers, and soft-float needs to use $v0, + // and $a0 instead of the usual $v0, and $v1. We therefore resort to a + // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on + // whether the result was originally an f128 into the tablegen-erated code. + // + // f128 should only occur for the N64 ABI where long double is 128-bit. On + // N32, long double is equivalent to double. + CCIfType<[i64], + CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", + CCDelegateTo<RetCC_F128>>>, + + // Aggregate returns are positioned at the lowest address in the slot for + // both little and big-endian targets. When passing in registers, this + // requires that big-endian targets shift the value into the upper bits. + CCIfSubtarget<"isLittle()", + CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>, + CCIfSubtargetNot<"isLittle()", + CCIfType<[i8, i16, i32, i64], + CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, // i64 are returned in registers V0_64, V1_64 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, @@ -98,12 +185,6 @@ def RetCC_MipsN : CallingConv<[ CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> ]>; -// In soft-mode, register A0_64, instead of V1_64, is used to return a long -// double value. -def RetCC_F128Soft : CallingConv<[ - CCIfType<[i64], CCAssignToReg<[V0_64, A0_64]>> -]>; - //===----------------------------------------------------------------------===// // Mips EABI Calling Convention //===----------------------------------------------------------------------===// @@ -119,11 +200,11 @@ def CC_MipsEABI : CallingConv<[ CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, - CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()", + CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[F12, F14, F16, F18]>>>, // The first 4 double fp arguments are passed in single fp registers. - CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", + CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D6, D7, D8, D9]>>>, // Integer values get stored in stack slots that are 4 bytes in @@ -132,7 +213,7 @@ def CC_MipsEABI : CallingConv<[ // Integer values get stored in stack slots that are 8 bytes in // size and 8-byte aligned. - CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToStack<8, 8>>> + CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>> ]>; def RetCC_MipsEABI : CallingConv<[ @@ -143,7 +224,7 @@ def RetCC_MipsEABI : CallingConv<[ CCIfType<[f32], CCAssignToReg<[F0, F1]>>, // f64 are returned in register D0 - CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> + CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>> ]>; //===----------------------------------------------------------------------===// @@ -151,16 +232,20 @@ def RetCC_MipsEABI : CallingConv<[ //===----------------------------------------------------------------------===// def CC_MipsO32_FastCC : CallingConv<[ // f64 arguments are passed in double-precision floating pointer registers. - CCIfType<[f64], CCIfSubtarget<"isNotFP64bit()", - CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7, - D8, D9]>>>, - CCIfType<[f64], CCIfSubtarget<"isFP64bit()", + CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", + CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, + D7, D8, D9]>>>, + CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, D18_64, - D19_64]>>>, + D19_64]>>>>, + CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()", + CCAssignToReg<[D0_64, D2_64, D4_64, D6_64, + D8_64, D10_64, D12_64, D14_64, + D16_64, D18_64]>>>>, // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. CCIfType<[f64], CCAssignToStack<8, 8>> @@ -192,7 +277,7 @@ def CC_Mips_FastCC : CallingConv<[ // Integer arguments are passed in integer registers. All scratch registers, // except for AT, V0 and T9, are available to be used as argument registers. - CCIfType<[i32], CCIfSubtarget<"isNotTargetNaCl()", + CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()", CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>, // In NaCl, T6, T7 and T8 are reserved and not available as argument @@ -203,8 +288,13 @@ def CC_Mips_FastCC : CallingConv<[ CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>, // f32 arguments are passed in single-precision floating pointer registers. - CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, - F11, F12, F13, F14, F15, F16, F17, F18, F19]>>, + CCIfType<[f32], CCIfSubtarget<"useOddSPReg()", + CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, + F14, F15, F16, F17, F18, F19]>>>, + + // Don't use odd numbered single-precision registers for -mno-odd-spreg. + CCIfType<[f32], CCIfSubtarget<"noOddSPReg()", + CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>, // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, @@ -214,13 +304,6 @@ def CC_Mips_FastCC : CallingConv<[ CCDelegateTo<CC_MipsN_FastCC> ]>; -//== - -def CC_Mips16RetHelper : CallingConv<[ - // Integer arguments are passed in integer registers. - CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> -]>; - //===----------------------------------------------------------------------===// // Mips Calling Convention Dispatch //===----------------------------------------------------------------------===// @@ -232,6 +315,66 @@ def RetCC_Mips : CallingConv<[ CCDelegateTo<RetCC_MipsO32> ]>; +def CC_Mips_ByVal : CallingConv<[ + CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>, + CCIfByVal<CCPassByVal<8, 8>> +]>; + +def CC_Mips16RetHelper : CallingConv<[ + CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, + + // Integer arguments are passed in integer registers. + CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> +]>; + +def CC_Mips_FixedArg : CallingConv<[ + // Mips16 needs special handling on some functions. + CCIf<"State.getCallingConv() != CallingConv::Fast", + CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == " + "MipsCCState::Mips16RetHelperConv", + CCDelegateTo<CC_Mips16RetHelper>>>, + + CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, + + // f128 needs to be handled similarly to f32 and f64 on hard-float. However, + // f128 is not legal and is lowered to i128 which is further lowered to a pair + // of i64's. + // This presents us with a problem for the calling convention since hard-float + // still needs to pass them in FPU registers. We therefore resort to a + // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on + // whether the argument was originally an f128 into the tablegen-erated code. + // + // f128 should only occur for the N64 ABI where long double is 128-bit. On + // N32, long double is equivalent to double. + CCIfType<[i64], + CCIfSubtargetNot<"abiUsesSoftFloat()", + CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", + CCBitConvertToType<f64>>>>, + + CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, + + // FIXME: There wasn't an EABI case in the original code and it seems unlikely + // that it's the same as CC_MipsN + CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, + CCDelegateTo<CC_MipsN> +]>; + +def CC_Mips_VarArg : CallingConv<[ + CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, + + // FIXME: There wasn't an EABI case in the original code and it seems unlikely + // that it's the same as CC_MipsN_VarArg + CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, + CCDelegateTo<CC_MipsN_VarArg> +]>; + +def CC_Mips : CallingConv<[ + CCIfVarArg< + CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", + CCDelegateTo<CC_Mips_VarArg>>>, + CCDelegateTo<CC_Mips_FixedArg> +]>; + //===----------------------------------------------------------------------===// // Callee-saved register lists. //===----------------------------------------------------------------------===// @@ -247,8 +390,9 @@ def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, (sequence "S%u", 7, 0))>; -def CSR_O32_FP64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 20), RA, FP, - (sequence "S%u", 7, 0))>; +def CSR_O32_FP64 : + CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, + (sequence "S%u", 7, 0))>; def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, D30_64, RA_64, FP_64, GP_64, diff --git a/lib/Target/Mips/MipsCodeEmitter.cpp b/lib/Target/Mips/MipsCodeEmitter.cpp deleted file mode 100644 index 151ef13..0000000 --- a/lib/Target/Mips/MipsCodeEmitter.cpp +++ /dev/null @@ -1,434 +0,0 @@ -//===-- Mips/MipsCodeEmitter.cpp - Convert Mips Code to Machine Code ------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===---------------------------------------------------------------------===// -// -// This file contains the pass that transforms the Mips machine instructions -// into relocatable machine code. -// -//===---------------------------------------------------------------------===// - -#include "Mips.h" -#include "MCTargetDesc/MipsBaseInfo.h" -#include "MipsInstrInfo.h" -#include "MipsRelocations.h" -#include "MipsSubtarget.h" -#include "MipsTargetMachine.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/JITCodeEmitter.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineInstr.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineJumpTableInfo.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineOperand.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/IR/Constants.h" -#include "llvm/IR/DerivedTypes.h" -#include "llvm/PassManager.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" -#ifndef NDEBUG -#include <iomanip> -#endif - -using namespace llvm; - -#define DEBUG_TYPE "jit" - -STATISTIC(NumEmitted, "Number of machine instructions emitted"); - -namespace { - -class MipsCodeEmitter : public MachineFunctionPass { - MipsJITInfo *JTI; - const MipsInstrInfo *II; - const DataLayout *TD; - const MipsSubtarget *Subtarget; - TargetMachine &TM; - JITCodeEmitter &MCE; - const std::vector<MachineConstantPoolEntry> *MCPEs; - const std::vector<MachineJumpTableEntry> *MJTEs; - bool IsPIC; - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired<MachineModuleInfo> (); - MachineFunctionPass::getAnalysisUsage(AU); - } - - static char ID; - -public: - MipsCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) - : MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr), - TM(tm), MCE(mce), MCPEs(nullptr), MJTEs(nullptr), - IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - - bool runOnMachineFunction(MachineFunction &MF) override; - - const char *getPassName() const override { - return "Mips Machine Code Emitter"; - } - - /// getBinaryCodeForInstr - This function, generated by the - /// CodeEmitterGenerator using TableGen, produces the binary encoding for - /// machine instructions. - uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; - - void emitInstruction(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB); - -private: - - void emitWord(unsigned Word); - - /// Routines that handle operands which add machine relocations which are - /// fixed up by the relocation stage. - void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, - bool MayNeedFarStub) const; - void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; - void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; - void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; - void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const; - - /// getMachineOpValue - Return binary encoding of operand. If the machine - /// operand requires relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) const; - - unsigned getRelocation(const MachineInstr &MI, - const MachineOperand &MO) const; - - unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const; - unsigned getJumpTargetOpValueMM(const MachineInstr &MI, unsigned OpNo) const; - unsigned getBranchTargetOpValueMM(const MachineInstr &MI, - unsigned OpNo) const; - - unsigned getBranchTarget21OpValue(const MachineInstr &MI, - unsigned OpNo) const; - unsigned getBranchTarget26OpValue(const MachineInstr &MI, - unsigned OpNo) const; - unsigned getJumpOffset16OpValue(const MachineInstr &MI, unsigned OpNo) const; - - unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned OpNo) const; - unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getMemEncodingMMImm12(const MachineInstr &MI, unsigned OpNo) const; - unsigned getMSAMemEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getLSAImmEncoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getSimm19Lsl2Encoding(const MachineInstr &MI, unsigned OpNo) const; - unsigned getSimm18Lsl3Encoding(const MachineInstr &MI, unsigned OpNo) const; - - /// Expand pseudo instructions with accumulator register operands. - void expandACCInstr(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB, unsigned Opc) const; - - /// \brief Expand pseudo instruction. Return true if MI was expanded. - bool expandPseudos(MachineBasicBlock::instr_iterator &MI, - MachineBasicBlock &MBB) const; -}; -} - -char MipsCodeEmitter::ID = 0; - -bool MipsCodeEmitter::runOnMachineFunction(MachineFunction &MF) { - MipsTargetMachine &Target = static_cast<MipsTargetMachine &>( - const_cast<TargetMachine &>(MF.getTarget())); - - JTI = Target.getJITInfo(); - II = Target.getInstrInfo(); - TD = Target.getDataLayout(); - Subtarget = &TM.getSubtarget<MipsSubtarget> (); - MCPEs = &MF.getConstantPool()->getConstants(); - MJTEs = nullptr; - if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); - JTI->Initialize(MF, IsPIC, Subtarget->isLittle()); - MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ()); - - do { - DEBUG(errs() << "JITTing function '" - << MF.getName() << "'\n"); - MCE.startFunction(MF); - - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB){ - MCE.StartMachineBasicBlock(MBB); - for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(), - E = MBB->instr_end(); I != E;) - emitInstruction(*I++, *MBB); - } - } while (MCE.finishFunction(MF)); - - return false; -} - -unsigned MipsCodeEmitter::getRelocation(const MachineInstr &MI, - const MachineOperand &MO) const { - // NOTE: This relocations are for static. - uint64_t TSFlags = MI.getDesc().TSFlags; - uint64_t Form = TSFlags & MipsII::FormMask; - if (Form == MipsII::FrmJ) - return Mips::reloc_mips_26; - if ((Form == MipsII::FrmI || Form == MipsII::FrmFI) - && MI.isBranch()) - return Mips::reloc_mips_pc16; - if (Form == MipsII::FrmI && MI.getOpcode() == Mips::LUi) - return Mips::reloc_mips_hi; - return Mips::reloc_mips_lo; -} - -unsigned MipsCodeEmitter::getJumpTargetOpValue(const MachineInstr &MI, - unsigned OpNo) const { - MachineOperand MO = MI.getOperand(OpNo); - if (MO.isGlobal()) - emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true); - else if (MO.isSymbol()) - emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO)); - else if (MO.isMBB()) - emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO)); - else - llvm_unreachable("Unexpected jump target operand kind."); - return 0; -} - -unsigned MipsCodeEmitter::getJumpTargetOpValueMM(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getBranchTargetOpValueMM(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getBranchTarget21OpValue(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getBranchTarget26OpValue(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getJumpOffset16OpValue(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI, - unsigned OpNo) const { - MachineOperand MO = MI.getOperand(OpNo); - emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO)); - return 0; -} - -unsigned MipsCodeEmitter::getMemEncoding(const MachineInstr &MI, - unsigned OpNo) const { - // Base register is encoded in bits 20-16, offset is encoded in bits 15-0. - assert(MI.getOperand(OpNo).isReg()); - unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; - return (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; -} - -unsigned MipsCodeEmitter::getMemEncodingMMImm12(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getMSAMemEncoding(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getSizeExtEncoding(const MachineInstr &MI, - unsigned OpNo) const { - // size is encoded as size-1. - return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; -} - -unsigned MipsCodeEmitter::getSizeInsEncoding(const MachineInstr &MI, - unsigned OpNo) const { - // size is encoded as pos+size-1. - return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + - getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; -} - -unsigned MipsCodeEmitter::getLSAImmEncoding(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getSimm18Lsl3Encoding(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -unsigned MipsCodeEmitter::getSimm19Lsl2Encoding(const MachineInstr &MI, - unsigned OpNo) const { - llvm_unreachable("Unimplemented function."); - return 0; -} - -/// getMachineOpValue - Return binary encoding of operand. If the machine -/// operand requires relocation, record the relocation and return zero. -unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) const { - if (MO.isReg()) - return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); - else if (MO.isImm()) - return static_cast<unsigned>(MO.getImm()); - else if (MO.isGlobal()) - emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO), true); - else if (MO.isSymbol()) - emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO)); - else if (MO.isCPI()) - emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO)); - else if (MO.isJTI()) - emitJumpTableAddress(MO.getIndex(), getRelocation(MI, MO)); - else if (MO.isMBB()) - emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO)); - else - llvm_unreachable("Unable to encode MachineOperand!"); - return 0; -} - -void MipsCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, - bool MayNeedFarStub) const { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, - const_cast<GlobalValue *>(GV), 0, - MayNeedFarStub)); -} - -void MipsCodeEmitter:: -emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), - Reloc, ES, 0, 0)); -} - -void MipsCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), - Reloc, CPI, 0, false)); -} - -void MipsCodeEmitter:: -emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), - Reloc, JTIndex, 0, false)); -} - -void MipsCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, - unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), - Reloc, BB)); -} - -void MipsCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB) { - DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI); - - // Expand pseudo instruction. Skip if MI was not expanded. - if (((MI->getDesc().TSFlags & MipsII::FormMask) == MipsII::Pseudo) && - !expandPseudos(MI, MBB)) - return; - - MCE.processDebugLoc(MI->getDebugLoc(), true); - - emitWord(getBinaryCodeForInstr(*MI)); - ++NumEmitted; // Keep track of the # of mi's emitted - - MCE.processDebugLoc(MI->getDebugLoc(), false); -} - -void MipsCodeEmitter::emitWord(unsigned Word) { - DEBUG(errs() << " 0x"; - errs().write_hex(Word) << "\n"); - if (Subtarget->isLittle()) - MCE.emitWordLE(Word); - else - MCE.emitWordBE(Word); -} - -void MipsCodeEmitter::expandACCInstr(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB, - unsigned Opc) const { - // Expand "pseudomult $ac0, $t0, $t1" to "mult $t0, $t1". - BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Opc)) - .addReg(MI->getOperand(1).getReg()).addReg(MI->getOperand(2).getReg()); -} - -bool MipsCodeEmitter::expandPseudos(MachineBasicBlock::instr_iterator &MI, - MachineBasicBlock &MBB) const { - switch (MI->getOpcode()) { - case Mips::NOP: - BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::SLL), Mips::ZERO) - .addReg(Mips::ZERO).addImm(0); - break; - case Mips::B: - BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BEQ)).addReg(Mips::ZERO) - .addReg(Mips::ZERO).addOperand(MI->getOperand(0)); - break; - case Mips::TRAP: - BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::BREAK)).addImm(0) - .addImm(0); - break; - case Mips::JALRPseudo: - BuildMI(MBB, &*MI, MI->getDebugLoc(), II->get(Mips::JALR), Mips::RA) - .addReg(MI->getOperand(0).getReg()); - break; - case Mips::PseudoMULT: - expandACCInstr(MI, MBB, Mips::MULT); - break; - case Mips::PseudoMULTu: - expandACCInstr(MI, MBB, Mips::MULTu); - break; - case Mips::PseudoSDIV: - expandACCInstr(MI, MBB, Mips::SDIV); - break; - case Mips::PseudoUDIV: - expandACCInstr(MI, MBB, Mips::UDIV); - break; - case Mips::PseudoMADD: - expandACCInstr(MI, MBB, Mips::MADD); - break; - case Mips::PseudoMADDU: - expandACCInstr(MI, MBB, Mips::MADDU); - break; - case Mips::PseudoMSUB: - expandACCInstr(MI, MBB, Mips::MSUB); - break; - case Mips::PseudoMSUBU: - expandACCInstr(MI, MBB, Mips::MSUBU); - break; - default: - return false; - } - - (MI--)->eraseFromBundle(); - return true; -} - -/// createMipsJITCodeEmitterPass - Return a pass that emits the collected Mips -/// code to the specified MCE object. -FunctionPass *llvm::createMipsJITCodeEmitterPass(MipsTargetMachine &TM, - JITCodeEmitter &JCE) { - return new MipsCodeEmitter(TM, JCE); -} - -#include "MipsGenCodeEmitter.inc" diff --git a/lib/Target/Mips/MipsConstantIslandPass.cpp b/lib/Target/Mips/MipsConstantIslandPass.cpp index a37062f..c4e5ac0 100644 --- a/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -28,6 +28,7 @@ #include "MipsTargetMachine.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -343,7 +344,6 @@ namespace { const TargetMachine &TM; bool IsPIC; - unsigned ABI; const MipsSubtarget *STI; const Mips16InstrInfo *TII; MipsFunctionInfo *MFI; @@ -365,11 +365,9 @@ namespace { public: static char ID; MipsConstantIslands(TargetMachine &tm) - : MachineFunctionPass(ID), TM(tm), - IsPIC(TM.getRelocationModel() == Reloc::PIC_), - ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()), - STI(&TM.getSubtarget<MipsSubtarget>()), MF(nullptr), MCP(nullptr), - PrescannedForConstants(false){} + : MachineFunctionPass(ID), TM(tm), + IsPIC(TM.getRelocationModel() == Reloc::PIC_), STI(nullptr), + MF(nullptr), MCP(nullptr), PrescannedForConstants(false) {} const char *getPassName() const override { return "Mips Constant Islands"; @@ -450,12 +448,14 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { // FIXME: MF = &mf; MCP = mf.getConstantPool(); + STI = &mf.getTarget().getSubtarget<MipsSubtarget>(); DEBUG(dbgs() << "constant island machine function " << "\n"); - if (!TM.getSubtarget<MipsSubtarget>().inMips16Mode() || - !MipsSubtarget::useConstantIslands()) { + if (!STI->inMips16Mode() || !MipsSubtarget::useConstantIslands()) { return false; } - TII = (const Mips16InstrInfo*)MF->getTarget().getInstrInfo(); + TII = (const Mips16InstrInfo *)MF->getTarget() + .getSubtargetImpl() + ->getInstrInfo(); MFI = MF->getInfo<MipsFunctionInfo>(); DEBUG(dbgs() << "constant island processing " << "\n"); // @@ -562,7 +562,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { // identity mapping of CPI's to CPE's. const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants(); - const DataLayout &TD = *MF->getTarget().getDataLayout(); + const DataLayout &TD = *MF->getSubtarget().getDataLayout(); for (unsigned i = 0, e = CPs.size(); i != e; ++i) { unsigned Size = TD.getTypeAllocSize(CPs[i].getType()); assert(Size >= 4 && "Too small constant pool entry"); @@ -588,9 +588,7 @@ MipsConstantIslands::doInitialPlacement(std::vector<MachineInstr*> &CPEMIs) { if (InsPoint[a] == InsAt) InsPoint[a] = CPEMI; // Add a new CPEntry, but no corresponding CPUser yet. - std::vector<CPEntry> CPEs; - CPEs.push_back(CPEntry(CPEMI, i)); - CPEntries.push_back(CPEs); + CPEntries.emplace_back(1, CPEntry(CPEMI, i)); ++NumCPEs; DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = " << Size << ", align = " << Align <<'\n'); diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp index bcfbc12..d7ba6d4 100644 --- a/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -275,7 +275,11 @@ static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { #ifndef NDEBUG const MachineFunction &MF = *MBB.getParent(); - assert(MF.getTarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && + assert(MF.getTarget() + .getSubtargetImpl() + ->getRegisterInfo() + ->getAllocatableSet(MF) + .test(R) && "Shouldn't move an instruction with unallocatable registers across " "basic block boundaries."); #endif @@ -286,8 +290,8 @@ static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { } RegDefsUses::RegDefsUses(TargetMachine &TM) - : TRI(*TM.getRegisterInfo()), Defs(TRI.getNumRegs(), false), - Uses(TRI.getNumRegs(), false) {} + : TRI(*TM.getSubtargetImpl()->getRegisterInfo()), + Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} void RegDefsUses::init(const MachineInstr &MI) { // Add all register operands which are explicit and non-variadic. @@ -451,7 +455,8 @@ bool MemDefsUses::hasHazard_(const MachineInstr &MI) { bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) { if (MayStore) - return !Defs.insert(V) || Uses.count(V) || SeenNoObjStore || SeenNoObjLoad; + return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore || + SeenNoObjLoad; Uses.insert(V); return Defs.count(V) || SeenNoObjStore; @@ -493,30 +498,38 @@ getUnderlyingObjects(const MachineInstr &MI, /// We assume there is only one delay slot per delayed instruction. bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; + bool InMicroMipsMode = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode(); for (Iter I = MBB.begin(); I != MBB.end(); ++I) { if (!hasUnoccupiedSlot(&*I)) continue; - ++FilledSlots; - Changed = true; - - // Delay slot filling is disabled at -O0. - if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { - if (searchBackward(MBB, I)) - continue; + // For microMIPS, at the moment, do not fill delay slots of call + // instructions. + // + // TODO: Support for replacing regular call instructions with corresponding + // short delay slot instructions should be implemented. + if (!InMicroMipsMode || !I->isCall()) { + ++FilledSlots; + Changed = true; + + // Delay slot filling is disabled at -O0. + if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { + if (searchBackward(MBB, I)) + continue; - if (I->isTerminator()) { - if (searchSuccBBs(MBB, I)) + if (I->isTerminator()) { + if (searchSuccBBs(MBB, I)) + continue; + } else if (searchForward(MBB, I)) { continue; - } else if (searchForward(MBB, I)) { - continue; + } } } // Bundle the NOP to the instruction with the delay slot. - const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>( + TM.getSubtargetImpl()->getInstrInfo()); BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); MIBundleBuilder(MBB, I, std::next(I, 2)); } @@ -554,9 +567,10 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, // branches are not checked because non-NaCl targets never put them in // delay slots. unsigned AddrIdx; - if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) - && baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) - || I->modifiesRegister(Mips::SP, TM.getRegisterInfo())) + if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) && + baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) || + I->modifiesRegister(Mips::SP, + TM.getSubtargetImpl()->getRegisterInfo())) continue; } @@ -667,7 +681,7 @@ MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const { std::pair<MipsInstrInfo::BranchType, MachineInstr *> Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const { const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo()); MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr; SmallVector<MachineInstr*, 2> BranchInstrs; SmallVector<MachineOperand, 2> Cond; diff --git a/lib/Target/Mips/MipsFastISel.cpp b/lib/Target/Mips/MipsFastISel.cpp index 617801b..2bb16e3 100644 --- a/lib/Target/Mips/MipsFastISel.cpp +++ b/lib/Target/Mips/MipsFastISel.cpp @@ -8,6 +8,7 @@ #include "llvm/IR/GlobalVariable.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLibraryInfo.h" +#include "MipsCCState.h" #include "MipsRegisterInfo.h" #include "MipsISelLowering.h" #include "MipsMachineFunction.h" @@ -18,22 +19,43 @@ using namespace llvm; namespace { -// All possible address modes. -typedef struct Address { - enum { RegBase, FrameIndexBase } BaseType; +class MipsFastISel final : public FastISel { - union { - unsigned Reg; - int FI; - } Base; + // All possible address modes. + class Address { + public: + typedef enum { RegBase, FrameIndexBase } BaseKind; - int64_t Offset; + private: + BaseKind Kind; + union { + unsigned Reg; + int FI; + } Base; - // Innocuous defaults for our address. - Address() : BaseType(RegBase), Offset(0) { Base.Reg = 0; } -} Address; + int64_t Offset; -class MipsFastISel final : public FastISel { + const GlobalValue *GV; + + public: + // Innocuous defaults for our address. + Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; } + void setKind(BaseKind K) { Kind = K; } + BaseKind getKind() const { return Kind; } + bool isRegBase() const { return Kind == RegBase; } + void setReg(unsigned Reg) { + assert(isRegBase() && "Invalid base register access!"); + Base.Reg = Reg; + } + unsigned getReg() const { + assert(isRegBase() && "Invalid base register access!"); + return Base.Reg; + } + void setOffset(int64_t Offset_) { Offset = Offset_; } + int64_t getOffset() const { return Offset; } + void setGlobalValue(const GlobalValue *G) { GV = G; } + const GlobalValue *getGlobalValue() { return GV; } + }; /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can /// make the right decision when generating code for different targets. @@ -47,74 +69,267 @@ class MipsFastISel final : public FastISel { // Convenience variables to avoid some queries. LLVMContext *Context; + bool fastLowerCall(CallLoweringInfo &CLI) override; + bool TargetSupported; + bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle + // floating point but not reject doing fast-isel in other + // situations + +private: + // Selection routines. + bool selectLoad(const Instruction *I); + bool selectStore(const Instruction *I); + bool selectBranch(const Instruction *I); + bool selectCmp(const Instruction *I); + bool selectFPExt(const Instruction *I); + bool selectFPTrunc(const Instruction *I); + bool selectFPToInt(const Instruction *I, bool IsSigned); + bool selectRet(const Instruction *I); + bool selectTrunc(const Instruction *I); + bool selectIntExt(const Instruction *I); + + // Utility helper routines. + bool isTypeLegal(Type *Ty, MVT &VT); + bool isLoadTypeLegal(Type *Ty, MVT &VT); + bool computeAddress(const Value *Obj, Address &Addr); + bool computeCallAddress(const Value *V, Address &Addr); + + // Emit helper routines. + bool emitCmp(unsigned DestReg, const CmpInst *CI); + bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, + unsigned Alignment = 0); + bool emitStore(MVT VT, unsigned SrcReg, Address Addr, + MachineMemOperand *MMO = nullptr); + bool emitStore(MVT VT, unsigned SrcReg, Address &Addr, + unsigned Alignment = 0); + unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); + bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg, + + bool IsZExt); + bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); + + bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg); + bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg); + bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg); + + unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned); + + unsigned materializeFP(const ConstantFP *CFP, MVT VT); + unsigned materializeGV(const GlobalValue *GV, MVT VT); + unsigned materializeInt(const Constant *C, MVT VT); + unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC); + + MachineInstrBuilder emitInst(unsigned Opc) { + return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)); + } + MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) { + return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), + DstReg); + } + MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg, + unsigned MemReg, int64_t MemOffset) { + return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); + } + MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg, + unsigned MemReg, int64_t MemOffset) { + return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); + } + // for some reason, this default is not generated by tablegen + // so we explicitly generate it here. + // + unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, + unsigned Op0, bool Op0IsKill, uint64_t imm1, + uint64_t imm2, unsigned Op3, bool Op3IsKill) { + return 0; + } + + // Call handling routines. +private: + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const; + bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs, + unsigned &NumBytes); + bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes); public: + // Backend specific FastISel code. explicit MipsFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) : FastISel(funcInfo, libInfo), M(const_cast<Module &>(*funcInfo.Fn->getParent())), - TM(funcInfo.MF->getTarget()), TII(*TM.getInstrInfo()), - TLI(*TM.getTargetLowering()), + TM(funcInfo.MF->getTarget()), + TII(*TM.getSubtargetImpl()->getInstrInfo()), + TLI(*TM.getSubtargetImpl()->getTargetLowering()), Subtarget(&TM.getSubtarget<MipsSubtarget>()) { MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); Context = &funcInfo.Fn->getContext(); TargetSupported = ((Subtarget->getRelocationModel() == Reloc::PIC_) && - (Subtarget->hasMips32r2() && (Subtarget->isABI_O32()))); + ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) && + (Subtarget->isABI_O32()))); + UnsupportedFPMode = Subtarget->isFP64bit(); } - bool TargetSelectInstruction(const Instruction *I) override; - unsigned TargetMaterializeConstant(const Constant *C) override; + unsigned fastMaterializeConstant(const Constant *C) override; + bool fastSelectInstruction(const Instruction *I) override; - bool ComputeAddress(const Value *Obj, Address &Addr); +#include "MipsGenFastISel.inc" +}; +} // end anonymous namespace. -private: - bool EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, - unsigned Alignment = 0); - bool EmitStore(MVT VT, unsigned SrcReg, Address &Addr, - unsigned Alignment = 0); - bool SelectLoad(const Instruction *I); - bool SelectRet(const Instruction *I); - bool SelectStore(const Instruction *I); +static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State) LLVM_ATTRIBUTE_UNUSED; - bool isTypeLegal(Type *Ty, MVT &VT); - bool isLoadTypeLegal(Type *Ty, MVT &VT); +static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State) { + llvm_unreachable("should not be called"); +} - unsigned MaterializeFP(const ConstantFP *CFP, MVT VT); - unsigned MaterializeGV(const GlobalValue *GV, MVT VT); - unsigned MaterializeInt(const Constant *C, MVT VT); - unsigned Materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC); +bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State) { + llvm_unreachable("should not be called"); +} - // for some reason, this default is not generated by tablegen - // so we explicitly generate it here. - // - unsigned FastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, - unsigned Op0, bool Op0IsKill, uint64_t imm1, - uint64_t imm2, unsigned Op3, bool Op3IsKill) { +#include "MipsGenCallingConv.inc" + +CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const { + return CC_MipsO32; +} + +unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) { + if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) return 0; - } + const TargetRegisterClass *RC = &Mips::GPR32RegClass; + const ConstantInt *CI = cast<ConstantInt>(C); + int64_t Imm; + if ((VT != MVT::i1) && CI->isNegative()) + Imm = CI->getSExtValue(); + else + Imm = CI->getZExtValue(); + return materialize32BitInt(Imm, RC); +} - MachineInstrBuilder EmitInst(unsigned Opc) { - return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)); - } +unsigned MipsFastISel::materialize32BitInt(int64_t Imm, + const TargetRegisterClass *RC) { + unsigned ResultReg = createResultReg(RC); - MachineInstrBuilder EmitInst(unsigned Opc, unsigned DstReg) { - return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), - DstReg); + if (isInt<16>(Imm)) { + unsigned Opc = Mips::ADDiu; + emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); + return ResultReg; + } else if (isUInt<16>(Imm)) { + emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); + return ResultReg; } + unsigned Lo = Imm & 0xFFFF; + unsigned Hi = (Imm >> 16) & 0xFFFF; + if (Lo) { + // Both Lo and Hi have nonzero bits. + unsigned TmpReg = createResultReg(RC); + emitInst(Mips::LUi, TmpReg).addImm(Hi); + emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); + } else { + emitInst(Mips::LUi, ResultReg).addImm(Hi); + } + return ResultReg; +} - MachineInstrBuilder EmitInstStore(unsigned Opc, unsigned SrcReg, - unsigned MemReg, int64_t MemOffset) { - return EmitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset); +unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) { + if (UnsupportedFPMode) + return 0; + int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); + if (VT == MVT::f32) { + const TargetRegisterClass *RC = &Mips::FGR32RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass); + emitInst(Mips::MTC1, DestReg).addReg(TempReg); + return DestReg; + } else if (VT == MVT::f64) { + const TargetRegisterClass *RC = &Mips::AFGR64RegClass; + unsigned DestReg = createResultReg(RC); + unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); + unsigned TempReg2 = + materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); + emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); + return DestReg; } + return 0; +} - MachineInstrBuilder EmitInstLoad(unsigned Opc, unsigned DstReg, - unsigned MemReg, int64_t MemOffset) { - return EmitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset); +unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) { + // For now 32-bit only. + if (VT != MVT::i32) + return 0; + const TargetRegisterClass *RC = &Mips::GPR32RegClass; + unsigned DestReg = createResultReg(RC); + const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); + bool IsThreadLocal = GVar && GVar->isThreadLocal(); + // TLS not supported at this time. + if (IsThreadLocal) + return 0; + emitInst(Mips::LW, DestReg) + .addReg(MFI->getGlobalBaseReg()) + .addGlobalAddress(GV, 0, MipsII::MO_GOT); + if ((GV->hasInternalLinkage() || + (GV->hasLocalLinkage() && !isa<Function>(GV)))) { + unsigned TempReg = createResultReg(RC); + emitInst(Mips::ADDiu, TempReg) + .addReg(DestReg) + .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO); + DestReg = TempReg; } + return DestReg; +} -#include "MipsGenFastISel.inc" -}; +// Materialize a constant into a register, and return the register +// number (or zero if we failed to handle it). +unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) { + EVT CEVT = TLI.getValueType(C->getType(), true); + + // Only handle simple types. + if (!CEVT.isSimple()) + return 0; + MVT VT = CEVT.getSimpleVT(); + + if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) + return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT); + else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) + return materializeGV(GV, VT); + else if (isa<ConstantInt>(C)) + return materializeInt(C, VT); + + return 0; +} + +bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) { + // This construct looks a big awkward but it is how other ports handle this + // and as this function is more fully completed, these cases which + // return false will have additional code in them. + // + if (isa<Instruction>(Obj)) + return false; + else if (isa<ConstantExpr>(Obj)) + return false; + Addr.setReg(getRegForValue(Obj)); + return Addr.getReg() != 0; +} + +bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) { + const GlobalValue *GV = dyn_cast<GlobalValue>(V); + if (GV && isa<Function>(GV) && dyn_cast<Function>(GV)->isIntrinsic()) + return false; + if (!GV) + return false; + if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { + Addr.setGlobalValue(GV); + return true; + } + return false; +} bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) { EVT evt = TLI.getValueType(Ty, true); @@ -138,21 +353,134 @@ bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { return true; return false; } - -bool MipsFastISel::ComputeAddress(const Value *Obj, Address &Addr) { - // This construct looks a big awkward but it is how other ports handle this - // and as this function is more fully completed, these cases which - // return false will have additional code in them. - // - if (isa<Instruction>(Obj)) +// Because of how EmitCmp is called with fast-isel, you can +// end up with redundant "andi" instructions after the sequences emitted below. +// We should try and solve this issue in the future. +// +bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { + const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1); + bool IsUnsigned = CI->isUnsigned(); + unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned); + if (LeftReg == 0) return false; - else if (isa<ConstantExpr>(Obj)) + unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned); + if (RightReg == 0) return false; - Addr.Base.Reg = getRegForValue(Obj); - return Addr.Base.Reg != 0; -} + CmpInst::Predicate P = CI->getPredicate(); -bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, + switch (P) { + default: + return false; + case CmpInst::ICMP_EQ: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); + emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1); + break; + } + case CmpInst::ICMP_NE: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg); + emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg); + break; + } + case CmpInst::ICMP_UGT: { + emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg); + break; + } + case CmpInst::ICMP_ULT: { + emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg); + break; + } + case CmpInst::ICMP_UGE: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg); + emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); + break; + } + case CmpInst::ICMP_ULE: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg); + emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); + break; + } + case CmpInst::ICMP_SGT: { + emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); + break; + } + case CmpInst::ICMP_SLT: { + emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); + break; + } + case CmpInst::ICMP_SGE: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); + emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); + break; + } + case CmpInst::ICMP_SLE: { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); + emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1); + break; + } + case CmpInst::FCMP_OEQ: + case CmpInst::FCMP_UNE: + case CmpInst::FCMP_OLT: + case CmpInst::FCMP_OLE: + case CmpInst::FCMP_OGT: + case CmpInst::FCMP_OGE: { + if (UnsupportedFPMode) + return false; + bool IsFloat = Left->getType()->isFloatTy(); + bool IsDouble = Left->getType()->isDoubleTy(); + if (!IsFloat && !IsDouble) + return false; + unsigned Opc, CondMovOpc; + switch (P) { + case CmpInst::FCMP_OEQ: + Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; + CondMovOpc = Mips::MOVT_I; + break; + case CmpInst::FCMP_UNE: + Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32; + CondMovOpc = Mips::MOVF_I; + break; + case CmpInst::FCMP_OLT: + Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32; + CondMovOpc = Mips::MOVT_I; + break; + case CmpInst::FCMP_OLE: + Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32; + CondMovOpc = Mips::MOVT_I; + break; + case CmpInst::FCMP_OGT: + Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32; + CondMovOpc = Mips::MOVF_I; + break; + case CmpInst::FCMP_OGE: + Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32; + CondMovOpc = Mips::MOVF_I; + break; + default: + llvm_unreachable("Only switching of a subset of CCs."); + } + unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass); + unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); + emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); + emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( + Mips::FCC0, RegState::ImplicitDefine); + MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg) + .addReg(RegWithOne) + .addReg(Mips::FCC0) + .addReg(RegWithZero, RegState::Implicit); + MI->tieOperands(0, 3); + break; + } + } + return true; +} +bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, unsigned Alignment) { // // more cases will be handled here in following patches. @@ -175,11 +503,15 @@ bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, break; } case MVT::f32: { + if (UnsupportedFPMode) + return false; ResultReg = createResultReg(&Mips::FGR32RegClass); Opc = Mips::LWC1; break; } case MVT::f64: { + if (UnsupportedFPMode) + return false; ResultReg = createResultReg(&Mips::AFGR64RegClass); Opc = Mips::LDC1; break; @@ -187,31 +519,11 @@ bool MipsFastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, default: return false; } - EmitInstLoad(Opc, ResultReg, Addr.Base.Reg, Addr.Offset); + emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset()); return true; } -// Materialize a constant into a register, and return the register -// number (or zero if we failed to handle it). -unsigned MipsFastISel::TargetMaterializeConstant(const Constant *C) { - EVT CEVT = TLI.getValueType(C->getType(), true); - - // Only handle simple types. - if (!CEVT.isSimple()) - return 0; - MVT VT = CEVT.getSimpleVT(); - - if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) - return MaterializeFP(CFP, VT); - else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) - return MaterializeGV(GV, VT); - else if (isa<ConstantInt>(C)) - return MaterializeInt(C, VT); - - return 0; -} - -bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, +bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, unsigned Alignment) { // // more cases will be handled here in following patches. @@ -228,19 +540,23 @@ bool MipsFastISel::EmitStore(MVT VT, unsigned SrcReg, Address &Addr, Opc = Mips::SW; break; case MVT::f32: + if (UnsupportedFPMode) + return false; Opc = Mips::SWC1; break; case MVT::f64: + if (UnsupportedFPMode) + return false; Opc = Mips::SDC1; break; default: return false; } - EmitInstStore(Opc, SrcReg, Addr.Base.Reg, Addr.Offset); + emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset()); return true; } -bool MipsFastISel::SelectLoad(const Instruction *I) { +bool MipsFastISel::selectLoad(const Instruction *I) { // Atomic loads need special handling. if (cast<LoadInst>(I)->isAtomic()) return false; @@ -252,17 +568,17 @@ bool MipsFastISel::SelectLoad(const Instruction *I) { // See if we can handle this address. Address Addr; - if (!ComputeAddress(I->getOperand(0), Addr)) + if (!computeAddress(I->getOperand(0), Addr)) return false; unsigned ResultReg; - if (!EmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) + if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) return false; - UpdateValueMap(I, ResultReg); + updateValueMap(I, ResultReg); return true; } -bool MipsFastISel::SelectStore(const Instruction *I) { +bool MipsFastISel::selectStore(const Instruction *I) { Value *Op0 = I->getOperand(0); unsigned SrcReg = 0; @@ -282,15 +598,394 @@ bool MipsFastISel::SelectStore(const Instruction *I) { // See if we can handle this address. Address Addr; - if (!ComputeAddress(I->getOperand(1), Addr)) + if (!computeAddress(I->getOperand(1), Addr)) return false; - if (!EmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) + if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) return false; return true; } -bool MipsFastISel::SelectRet(const Instruction *I) { +// +// This can cause a redundant sltiu to be generated. +// FIXME: try and eliminate this in a future patch. +// +bool MipsFastISel::selectBranch(const Instruction *I) { + const BranchInst *BI = cast<BranchInst>(I); + MachineBasicBlock *BrBB = FuncInfo.MBB; + // + // TBB is the basic block for the case where the comparison is true. + // FBB is the basic block for the case where the comparison is false. + // if (cond) goto TBB + // goto FBB + // TBB: + // + MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; + MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; + BI->getCondition(); + // For now, just try the simplest case where it's fed by a compare. + if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { + unsigned CondReg = createResultReg(&Mips::GPR32RegClass); + if (!emitCmp(CondReg, CI)) + return false; + BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ)) + .addReg(CondReg) + .addMBB(TBB); + fastEmitBranch(FBB, DbgLoc); + FuncInfo.MBB->addSuccessor(TBB); + return true; + } + return false; +} + +bool MipsFastISel::selectCmp(const Instruction *I) { + const CmpInst *CI = cast<CmpInst>(I); + unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); + if (!emitCmp(ResultReg, CI)) + return false; + updateValueMap(I, ResultReg); + return true; +} + +// Attempt to fast-select a floating-point extend instruction. +bool MipsFastISel::selectFPExt(const Instruction *I) { + if (UnsupportedFPMode) + return false; + Value *Src = I->getOperand(0); + EVT SrcVT = TLI.getValueType(Src->getType(), true); + EVT DestVT = TLI.getValueType(I->getType(), true); + + if (SrcVT != MVT::f32 || DestVT != MVT::f64) + return false; + + unsigned SrcReg = + getRegForValue(Src); // his must be a 32 bit floating point register class + // maybe we should handle this differently + if (!SrcReg) + return false; + + unsigned DestReg = createResultReg(&Mips::AFGR64RegClass); + emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg); + updateValueMap(I, DestReg); + return true; +} + +// Attempt to fast-select a floating-point truncate instruction. +bool MipsFastISel::selectFPTrunc(const Instruction *I) { + if (UnsupportedFPMode) + return false; + Value *Src = I->getOperand(0); + EVT SrcVT = TLI.getValueType(Src->getType(), true); + EVT DestVT = TLI.getValueType(I->getType(), true); + + if (SrcVT != MVT::f64 || DestVT != MVT::f32) + return false; + + unsigned SrcReg = getRegForValue(Src); + if (!SrcReg) + return false; + + unsigned DestReg = createResultReg(&Mips::FGR32RegClass); + if (!DestReg) + return false; + + emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg); + updateValueMap(I, DestReg); + return true; +} + +// Attempt to fast-select a floating-point-to-integer conversion. +bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) { + if (UnsupportedFPMode) + return false; + MVT DstVT, SrcVT; + if (!IsSigned) + return false; // We don't handle this case yet. There is no native + // instruction for this but it can be synthesized. + Type *DstTy = I->getType(); + if (!isTypeLegal(DstTy, DstVT)) + return false; + + if (DstVT != MVT::i32) + return false; + + Value *Src = I->getOperand(0); + Type *SrcTy = Src->getType(); + if (!isTypeLegal(SrcTy, SrcVT)) + return false; + + if (SrcVT != MVT::f32 && SrcVT != MVT::f64) + return false; + + unsigned SrcReg = getRegForValue(Src); + if (SrcReg == 0) + return false; + + // Determine the opcode for the conversion, which takes place + // entirely within FPRs. + unsigned DestReg = createResultReg(&Mips::GPR32RegClass); + unsigned TempReg = createResultReg(&Mips::FGR32RegClass); + unsigned Opc; + + if (SrcVT == MVT::f32) + Opc = Mips::TRUNC_W_S; + else + Opc = Mips::TRUNC_W_D32; + + // Generate the convert. + emitInst(Opc, TempReg).addReg(SrcReg); + + emitInst(Mips::MFC1, DestReg).addReg(TempReg); + + updateValueMap(I, DestReg); + return true; +} +// +bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI, + SmallVectorImpl<MVT> &OutVTs, + unsigned &NumBytes) { + CallingConv::ID CC = CLI.CallConv; + SmallVector<CCValAssign, 16> ArgLocs; + CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context); + CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC)); + // Get a count of how many bytes are to be pushed on the stack. + NumBytes = CCInfo.getNextStackOffset(); + // This is the minimum argument area used for A0-A3. + if (NumBytes < 16) + NumBytes = 16; + + emitInst(Mips::ADJCALLSTACKDOWN).addImm(16); + // Process the args. + MVT firstMVT; + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + const Value *ArgVal = CLI.OutVals[VA.getValNo()]; + MVT ArgVT = OutVTs[VA.getValNo()]; + + if (i == 0) { + firstMVT = ArgVT; + if (ArgVT == MVT::f32) { + VA.convertToReg(Mips::F12); + } else if (ArgVT == MVT::f64) { + VA.convertToReg(Mips::D6); + } + } else if (i == 1) { + if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) { + if (ArgVT == MVT::f32) { + VA.convertToReg(Mips::F14); + } else if (ArgVT == MVT::f64) { + VA.convertToReg(Mips::D7); + } + } + } + if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) { + switch (VA.getLocMemOffset()) { + case 0: + VA.convertToReg(Mips::A0); + break; + case 4: + VA.convertToReg(Mips::A1); + break; + case 8: + VA.convertToReg(Mips::A2); + break; + case 12: + VA.convertToReg(Mips::A3); + break; + default: + break; + } + } + unsigned ArgReg = getRegForValue(ArgVal); + if (!ArgReg) + return false; + + // Handle arg promotion: SExt, ZExt, AExt. + switch (VA.getLocInfo()) { + case CCValAssign::Full: + break; + case CCValAssign::AExt: + case CCValAssign::SExt: { + MVT DestVT = VA.getLocVT(); + MVT SrcVT = ArgVT; + ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false); + if (!ArgReg) + return false; + break; + } + case CCValAssign::ZExt: { + MVT DestVT = VA.getLocVT(); + MVT SrcVT = ArgVT; + ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true); + if (!ArgReg) + return false; + break; + } + default: + llvm_unreachable("Unknown arg promotion!"); + } + + // Now copy/store arg to correct locations. + if (VA.isRegLoc() && !VA.needsCustom()) { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); + CLI.OutRegs.push_back(VA.getLocReg()); + } else if (VA.needsCustom()) { + llvm_unreachable("Mips does not use custom args."); + return false; + } else { + // + // FIXME: This path will currently return false. It was copied + // from the AArch64 port and should be essentially fine for Mips too. + // The work to finish up this path will be done in a follow-on patch. + // + assert(VA.isMemLoc() && "Assuming store on stack."); + // Don't emit stores for undef values. + if (isa<UndefValue>(ArgVal)) + continue; + + // Need to store on the stack. + // FIXME: This alignment is incorrect but this path is disabled + // for now (will return false). We need to determine the right alignment + // based on the normal alignment for the underlying machine type. + // + unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4); + + unsigned BEAlign = 0; + if (ArgSize < 8 && !Subtarget->isLittle()) + BEAlign = 8 - ArgSize; + + Address Addr; + Addr.setKind(Address::RegBase); + Addr.setReg(Mips::SP); + Addr.setOffset(VA.getLocMemOffset() + BEAlign); + + unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType()); + MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( + MachinePointerInfo::getStack(Addr.getOffset()), + MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment); + (void)(MMO); + // if (!emitStore(ArgVT, ArgReg, Addr, MMO)) + return false; // can't store on the stack yet. + } + } + + return true; +} + +bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, + unsigned NumBytes) { + CallingConv::ID CC = CLI.CallConv; + emitInst(Mips::ADJCALLSTACKUP).addImm(16); + if (RetVT != MVT::isVoid) { + SmallVector<CCValAssign, 16> RVLocs; + CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context); + CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips); + + // Only handle a single return value. + if (RVLocs.size() != 1) + return false; + // Copy all of the result registers out of their specified physreg. + MVT CopyVT = RVLocs[0].getValVT(); + // Special handling for extended integers. + if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) + CopyVT = MVT::i32; + + unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), + ResultReg).addReg(RVLocs[0].getLocReg()); + CLI.InRegs.push_back(RVLocs[0].getLocReg()); + + CLI.ResultReg = ResultReg; + CLI.NumResultRegs = 1; + } + return true; +} + +bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) { + CallingConv::ID CC = CLI.CallConv; + bool IsTailCall = CLI.IsTailCall; + bool IsVarArg = CLI.IsVarArg; + const Value *Callee = CLI.Callee; + // const char *SymName = CLI.SymName; + + // Allow SelectionDAG isel to handle tail calls. + if (IsTailCall) + return false; + + // Let SDISel handle vararg functions. + if (IsVarArg) + return false; + + // FIXME: Only handle *simple* calls for now. + MVT RetVT; + if (CLI.RetTy->isVoidTy()) + RetVT = MVT::isVoid; + else if (!isTypeLegal(CLI.RetTy, RetVT)) + return false; + + for (auto Flag : CLI.OutFlags) + if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal()) + return false; + + // Set up the argument vectors. + SmallVector<MVT, 16> OutVTs; + OutVTs.reserve(CLI.OutVals.size()); + + for (auto *Val : CLI.OutVals) { + MVT VT; + if (!isTypeLegal(Val->getType(), VT) && + !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)) + return false; + + // We don't handle vector parameters yet. + if (VT.isVector() || VT.getSizeInBits() > 64) + return false; + + OutVTs.push_back(VT); + } + + Address Addr; + if (!computeCallAddress(Callee, Addr)) + return false; + + // Handle the arguments now that we've gotten them. + unsigned NumBytes; + if (!processCallArgs(CLI, OutVTs, NumBytes)) + return false; + + // Issue the call. + unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32); + emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress); + MachineInstrBuilder MIB = + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR), + Mips::RA).addReg(Mips::T9); + + // Add implicit physical register uses to the call. + for (auto Reg : CLI.OutRegs) + MIB.addReg(Reg, RegState::Implicit); + + // Add a register mask with the call-preserved registers. + // Proper defs for return values will be added by setPhysRegsDeadExcept(). + MIB.addRegMask(TRI.getCallPreservedMask(CC)); + + CLI.Call = MIB; + + // Add implicit physical register uses to the call. + for (auto Reg : CLI.OutRegs) + MIB.addReg(Reg, RegState::Implicit); + + // Add a register mask with the call-preserved registers. Proper + // defs for return values will be added by setPhysRegsDeadExcept(). + MIB.addRegMask(TRI.getCallPreservedMask(CC)); + + CLI.Call = MIB; + // Finish off the call including any return values. + return finishCall(CLI, RetVT, NumBytes); +} + +bool MipsFastISel::selectRet(const Instruction *I) { const ReturnInst *Ret = cast<ReturnInst>(I); if (!FuncInfo.CanLowerReturn) @@ -298,98 +993,181 @@ bool MipsFastISel::SelectRet(const Instruction *I) { if (Ret->getNumOperands() > 0) { return false; } - EmitInst(Mips::RetRA); + emitInst(Mips::RetRA); return true; } -bool MipsFastISel::TargetSelectInstruction(const Instruction *I) { - if (!TargetSupported) +bool MipsFastISel::selectTrunc(const Instruction *I) { + // The high bits for a type smaller than the register size are assumed to be + // undefined. + Value *Op = I->getOperand(0); + + EVT SrcVT, DestVT; + SrcVT = TLI.getValueType(Op->getType(), true); + DestVT = TLI.getValueType(I->getType(), true); + + if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) return false; - switch (I->getOpcode()) { + if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) + return false; + + unsigned SrcReg = getRegForValue(Op); + if (!SrcReg) + return false; + + // Because the high bits are undefined, a truncate doesn't generate + // any code. + updateValueMap(I, SrcReg); + return true; +} +bool MipsFastISel::selectIntExt(const Instruction *I) { + Type *DestTy = I->getType(); + Value *Src = I->getOperand(0); + Type *SrcTy = Src->getType(); + + bool isZExt = isa<ZExtInst>(I); + unsigned SrcReg = getRegForValue(Src); + if (!SrcReg) + return false; + + EVT SrcEVT, DestEVT; + SrcEVT = TLI.getValueType(SrcTy, true); + DestEVT = TLI.getValueType(DestTy, true); + if (!SrcEVT.isSimple()) + return false; + if (!DestEVT.isSimple()) + return false; + + MVT SrcVT = SrcEVT.getSimpleVT(); + MVT DestVT = DestEVT.getSimpleVT(); + unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); + + if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt)) + return false; + updateValueMap(I, ResultReg); + return true; +} +bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg) { + unsigned ShiftAmt; + switch (SrcVT.SimpleTy) { default: + return false; + case MVT::i8: + ShiftAmt = 24; + break; + case MVT::i16: + ShiftAmt = 16; break; - case Instruction::Load: - return SelectLoad(I); - case Instruction::Store: - return SelectStore(I); - case Instruction::Ret: - return SelectRet(I); } - return false; -} + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); + emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt); + return true; } -unsigned MipsFastISel::MaterializeFP(const ConstantFP *CFP, MVT VT) { - int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); - if (VT == MVT::f32) { - const TargetRegisterClass *RC = &Mips::FGR32RegClass; - unsigned DestReg = createResultReg(RC); - unsigned TempReg = Materialize32BitInt(Imm, &Mips::GPR32RegClass); - EmitInst(Mips::MTC1, DestReg).addReg(TempReg); - return DestReg; - } else if (VT == MVT::f64) { - const TargetRegisterClass *RC = &Mips::AFGR64RegClass; - unsigned DestReg = createResultReg(RC); - unsigned TempReg1 = Materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass); - unsigned TempReg2 = - Materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass); - EmitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1); - return DestReg; +bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg) { + switch (SrcVT.SimpleTy) { + default: + return false; + case MVT::i8: + emitInst(Mips::SEB, DestReg).addReg(SrcReg); + break; + case MVT::i16: + emitInst(Mips::SEH, DestReg).addReg(SrcReg); + break; } - return 0; + return true; } -unsigned MipsFastISel::MaterializeGV(const GlobalValue *GV, MVT VT) { - // For now 32-bit only. - if (VT != MVT::i32) - return 0; - const TargetRegisterClass *RC = &Mips::GPR32RegClass; - unsigned DestReg = createResultReg(RC); - const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); - bool IsThreadLocal = GVar && GVar->isThreadLocal(); - // TLS not supported at this time. - if (IsThreadLocal) - return 0; - EmitInst(Mips::LW, DestReg).addReg(MFI->getGlobalBaseReg()).addGlobalAddress( - GV, 0, MipsII::MO_GOT); - return DestReg; +bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg) { + if ((DestVT != MVT::i32) && (DestVT != MVT::i16)) + return false; + if (Subtarget->hasMips32r2()) + return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg); + return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg); } -unsigned MipsFastISel::MaterializeInt(const Constant *C, MVT VT) { - if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) - return 0; - const TargetRegisterClass *RC = &Mips::GPR32RegClass; - const ConstantInt *CI = cast<ConstantInt>(C); - int64_t Imm; - if (CI->isNegative()) - Imm = CI->getSExtValue(); - else - Imm = CI->getZExtValue(); - return Materialize32BitInt(Imm, RC); + +bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg) { + switch (SrcVT.SimpleTy) { + default: + return false; + case MVT::i1: + emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1); + break; + case MVT::i8: + emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff); + break; + case MVT::i16: + emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff); + break; + } + return true; } -unsigned MipsFastISel::Materialize32BitInt(int64_t Imm, - const TargetRegisterClass *RC) { - unsigned ResultReg = createResultReg(RC); +bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, + unsigned DestReg, bool IsZExt) { + if (IsZExt) + return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg); + return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg); +} - if (isInt<16>(Imm)) { - unsigned Opc = Mips::ADDiu; - EmitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); - return ResultReg; - } else if (isUInt<16>(Imm)) { - EmitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm); - return ResultReg; +unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, + bool isZExt) { + unsigned DestReg = createResultReg(&Mips::GPR32RegClass); + return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt); +} + +bool MipsFastISel::fastSelectInstruction(const Instruction *I) { + if (!TargetSupported) + return false; + switch (I->getOpcode()) { + default: + break; + case Instruction::Load: + return selectLoad(I); + case Instruction::Store: + return selectStore(I); + case Instruction::Br: + return selectBranch(I); + case Instruction::Ret: + return selectRet(I); + case Instruction::Trunc: + return selectTrunc(I); + case Instruction::ZExt: + case Instruction::SExt: + return selectIntExt(I); + case Instruction::FPTrunc: + return selectFPTrunc(I); + case Instruction::FPExt: + return selectFPExt(I); + case Instruction::FPToSI: + return selectFPToInt(I, /*isSigned*/ true); + case Instruction::FPToUI: + return selectFPToInt(I, /*isSigned*/ false); + case Instruction::ICmp: + case Instruction::FCmp: + return selectCmp(I); } - unsigned Lo = Imm & 0xFFFF; - unsigned Hi = (Imm >> 16) & 0xFFFF; - if (Lo) { - // Both Lo and Hi have nonzero bits. - unsigned TmpReg = createResultReg(RC); - EmitInst(Mips::LUi, TmpReg).addImm(Hi); - EmitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo); - } else { - EmitInst(Mips::LUi, ResultReg).addImm(Hi); + return false; +} + +unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V, + bool IsUnsigned) { + unsigned VReg = getRegForValue(V); + if (VReg == 0) + return 0; + MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT(); + if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) { + unsigned TempReg = createResultReg(&Mips::GPR32RegClass); + if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned)) + return 0; + VReg = TempReg; } - return ResultReg; + return VReg; } namespace llvm { diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp index 8ba35fa..3014a0d 100644 --- a/lib/Target/Mips/MipsFrameLowering.cpp +++ b/lib/Target/Mips/MipsFrameLowering.cpp @@ -82,9 +82,8 @@ using namespace llvm; // //===----------------------------------------------------------------------===// -const MipsFrameLowering *MipsFrameLowering::create(MipsTargetMachine &TM, - const MipsSubtarget &ST) { - if (TM.getSubtargetImpl()->inMips16Mode()) +const MipsFrameLowering *MipsFrameLowering::create(const MipsSubtarget &ST) { + if (ST.inMips16Mode()) return llvm::createMips16FrameLowering(ST); return llvm::createMipsSEFrameLowering(ST); @@ -101,7 +100,7 @@ bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); int64_t Offset = 0; diff --git a/lib/Target/Mips/MipsFrameLowering.h b/lib/Target/Mips/MipsFrameLowering.h index 8e9196c..90a8d2a 100644 --- a/lib/Target/Mips/MipsFrameLowering.h +++ b/lib/Target/Mips/MipsFrameLowering.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS_FRAMEINFO_H -#define MIPS_FRAMEINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSFRAMELOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPSFRAMELOWERING_H #include "Mips.h" #include "llvm/Target/TargetFrameLowering.h" @@ -28,8 +28,7 @@ public: explicit MipsFrameLowering(const MipsSubtarget &sti, unsigned Alignment) : TargetFrameLowering(StackGrowsDown, Alignment, 0, Alignment), STI(sti) {} - static const MipsFrameLowering *create(MipsTargetMachine &TM, - const MipsSubtarget &ST); + static const MipsFrameLowering *create(const MipsSubtarget &ST); bool hasFP(const MachineFunction &MF) const override; diff --git a/lib/Target/Mips/MipsISelDAGToDAG.h b/lib/Target/Mips/MipsISelDAGToDAG.h index 2a6c875..ff8760d 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/lib/Target/Mips/MipsISelDAGToDAG.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSISELDAGTODAG_H -#define MIPSISELDAGTODAG_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H +#define LLVM_LIB_TARGET_MIPS_MIPSISELDAGTODAG_H #include "Mips.h" #include "MipsSubtarget.h" @@ -32,7 +32,7 @@ namespace llvm { class MipsDAGToDAGISel : public SelectionDAGISel { public: explicit MipsDAGToDAGISel(MipsTargetMachine &TM) - : SelectionDAGISel(TM), Subtarget(&TM.getSubtarget<MipsSubtarget>()) {} + : SelectionDAGISel(TM), Subtarget(nullptr) {} // Pass Name const char *getPassName() const override { diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index b7af2d4..ff2bfb3 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -14,6 +14,7 @@ #include "MipsISelLowering.h" #include "InstPrinter/MipsInstPrinter.h" #include "MCTargetDesc/MipsBaseInfo.h" +#include "MipsCCState.h" #include "MipsMachineFunction.h" #include "MipsSubtarget.h" #include "MipsTargetMachine.h" @@ -24,6 +25,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" #include "llvm/CodeGen/ValueTypes.h" @@ -56,15 +58,6 @@ EnableMipsFastISel("mips-fast-isel", cl::Hidden, cl::desc("Allow mips-fast-isel to be used"), cl::init(false)); -static const MCPhysReg O32IntRegs[4] = { - Mips::A0, Mips::A1, Mips::A2, Mips::A3 -}; - -static const MCPhysReg Mips64IntRegs[8] = { - Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, - Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 -}; - static const MCPhysReg Mips64DPRegs[8] = { Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 @@ -208,16 +201,16 @@ const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) - : TargetLowering(TM, new MipsTargetObjectFile()), - Subtarget(&TM.getSubtarget<MipsSubtarget>()) { +MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI) + : TargetLowering(TM), Subtarget(STI) { // Mips does not have i1 type, so use i32 for // setcc operations results (slt, sgt, ...). setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA // does. Integer booleans still use 0 and 1. - if (Subtarget->hasMips32r6()) + if (Subtarget.hasMips32r6()) setBooleanContents(ZeroOrOneBooleanContent, ZeroOrNegativeOneBooleanContent); @@ -251,12 +244,11 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::SETCC, MVT::f32, Custom); setOperationAction(ISD::SETCC, MVT::f64, Custom); setOperationAction(ISD::BRCOND, MVT::Other, Custom); - setOperationAction(ISD::VASTART, MVT::Other, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); - if (Subtarget->isGP64bit()) { + if (Subtarget.isGP64bit()) { setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); @@ -268,14 +260,14 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); } - if (!Subtarget->isGP64bit()) { + if (!Subtarget.isGP64bit()) { setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); } setOperationAction(ISD::ADD, MVT::i32, Custom); - if (Subtarget->isGP64bit()) + if (Subtarget.isGP64bit()) setOperationAction(ISD::ADD, MVT::i64, Custom); setOperationAction(ISD::SDIV, MVT::i32, Expand); @@ -299,7 +291,7 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - if (Subtarget->hasCnMips()) { + if (Subtarget.hasCnMips()) { setOperationAction(ISD::CTPOP, MVT::i32, Legal); setOperationAction(ISD::CTPOP, MVT::i64, Legal); } else { @@ -317,10 +309,10 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - if (!Subtarget->hasMips32r2()) + if (!Subtarget.hasMips32r2()) setOperationAction(ISD::ROTR, MVT::i32, Expand); - if (!Subtarget->hasMips64r2()) + if (!Subtarget.hasMips64r2()) setOperationAction(ISD::ROTR, MVT::i64, Expand); setOperationAction(ISD::FSIN, MVT::f32, Expand); @@ -343,7 +335,8 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::EH_RETURN, MVT::Other, Custom); - setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAARG, MVT::Other, Custom); setOperationAction(ISD::VACOPY, MVT::Other, Expand); setOperationAction(ISD::VAEND, MVT::Other, Expand); @@ -358,23 +351,23 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setInsertFencesForAtomic(true); - if (!Subtarget->hasMips32r2()) { + if (!Subtarget.hasMips32r2()) { setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); } // MIPS16 lacks MIPS32's clz and clo instructions. - if (!Subtarget->hasMips32() || Subtarget->inMips16Mode()) + if (!Subtarget.hasMips32() || Subtarget.inMips16Mode()) setOperationAction(ISD::CTLZ, MVT::i32, Expand); - if (!Subtarget->hasMips64()) + if (!Subtarget.hasMips64()) setOperationAction(ISD::CTLZ, MVT::i64, Expand); - if (!Subtarget->hasMips32r2()) + if (!Subtarget.hasMips32r2()) setOperationAction(ISD::BSWAP, MVT::i32, Expand); - if (!Subtarget->hasMips64r2()) + if (!Subtarget.hasMips64r2()) setOperationAction(ISD::BSWAP, MVT::i64, Expand); - if (Subtarget->isGP64bit()) { + if (Subtarget.isGP64bit()) { setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Custom); setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Custom); setLoadExtAction(ISD::EXTLOAD, MVT::i32, Custom); @@ -390,24 +383,30 @@ MipsTargetLowering::MipsTargetLowering(MipsTargetMachine &TM) setTargetDAGCombine(ISD::OR); setTargetDAGCombine(ISD::ADD); - setMinFunctionAlignment(Subtarget->isGP64bit() ? 3 : 2); + setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); + + // The arguments on the stack are defined in terms of 4-byte slots on O32 + // and 8-byte slots on N32/N64. + setMinStackArgumentAlignment( + (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4); - setStackPointerRegisterToSaveRestore(Subtarget->isABI_N64() ? Mips::SP_64 - : Mips::SP); + setStackPointerRegisterToSaveRestore(Subtarget.isABI_N64() ? Mips::SP_64 + : Mips::SP); - setExceptionPointerRegister(Subtarget->isABI_N64() ? Mips::A0_64 : Mips::A0); - setExceptionSelectorRegister(Subtarget->isABI_N64() ? Mips::A1_64 : Mips::A1); + setExceptionPointerRegister(Subtarget.isABI_N64() ? Mips::A0_64 : Mips::A0); + setExceptionSelectorRegister(Subtarget.isABI_N64() ? Mips::A1_64 : Mips::A1); MaxStoresPerMemcpy = 16; - isMicroMips = Subtarget->inMicroMipsMode(); + isMicroMips = Subtarget.inMicroMipsMode(); } -const MipsTargetLowering *MipsTargetLowering::create(MipsTargetMachine &TM) { - if (TM.getSubtargetImpl()->inMips16Mode()) - return llvm::createMips16TargetLowering(TM); +const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM, + const MipsSubtarget &STI) { + if (STI.inMips16Mode()) + return llvm::createMips16TargetLowering(TM, STI); - return llvm::createMipsSETargetLowering(TM); + return llvm::createMipsSETargetLowering(TM, STI); } // Create a fast isel object. @@ -427,7 +426,7 @@ EVT MipsTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); @@ -537,7 +536,7 @@ static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); @@ -616,11 +615,11 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { // Pattern match EXT. // $dst = and ((sra or srl) $src , pos), (2**size - 1) // => ext $dst, $src, size, pos - if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) + if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) return SDValue(); SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); @@ -656,12 +655,12 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { // Pattern match INS. // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 // => ins $dst, $src, size, pos, $src1 - if (DCI.isBeforeLegalizeOps() || !Subtarget->hasExtractInsert()) + if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) return SDValue(); SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); @@ -710,7 +709,7 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt)) if (DCI.isBeforeLegalizeOps()) @@ -791,6 +790,7 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const case ISD::SELECT_CC: return lowerSELECT_CC(Op, DAG); case ISD::SETCC: return lowerSETCC(Op, DAG); case ISD::VASTART: return lowerVASTART(Op, DAG); + case ISD::VAARG: return lowerVAARG(Op, DAG); case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG); case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG); @@ -933,16 +933,16 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case Mips::DIVU: case Mips::MOD: case Mips::MODU: - return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(), - false); + return insertDivByZeroTrap( + MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), false); case Mips::PseudoDSDIV: case Mips::PseudoDUDIV: case Mips::DDIV: case Mips::DDIVU: case Mips::DMOD: case Mips::DMODU: - return insertDivByZeroTrap(MI, *BB, *getTargetMachine().getInstrInfo(), - true); + return insertDivByZeroTrap( + MI, *BB, *getTargetMachine().getSubtargetImpl()->getInstrInfo(), true); case Mips::SEL_D: return emitSEL_D(MI, BB); } @@ -959,7 +959,8 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned LL, SC, AND, NOR, ZERO, BEQ; @@ -968,16 +969,16 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, LL = Mips::LL_MM; SC = Mips::SC_MM; } else { - LL = Subtarget->hasMips32r6() ? Mips::LL : Mips::LL_R6; - SC = Subtarget->hasMips32r6() ? Mips::SC : Mips::SC_R6; + LL = Subtarget.hasMips32r6() ? Mips::LL_R6 : Mips::LL; + SC = Subtarget.hasMips32r6() ? Mips::SC_R6 : Mips::SC; } AND = Mips::AND; NOR = Mips::NOR; ZERO = Mips::ZERO; BEQ = Mips::BEQ; } else { - LL = Subtarget->hasMips64r6() ? Mips::LLD : Mips::LLD_R6; - SC = Subtarget->hasMips64r6() ? Mips::SCD : Mips::SCD_R6; + LL = Subtarget.hasMips64r6() ? Mips::LLD_R6 : Mips::LLD; + SC = Subtarget.hasMips64r6() ? Mips::SCD_R6 : Mips::SCD; AND = Mips::AND64; NOR = Mips::NOR64; ZERO = Mips::ZERO_64; @@ -1042,15 +1043,16 @@ MipsTargetLowering::emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg( MachineInstr *MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg, unsigned SrcReg) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); - if (Subtarget->hasMips32r2() && Size == 1) { + if (Subtarget.hasMips32r2() && Size == 1) { BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg); return BB; } - if (Subtarget->hasMips32r2() && Size == 2) { + if (Subtarget.hasMips32r2() && Size == 2) { BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg); return BB; } @@ -1078,7 +1080,8 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Dest = MI->getOperand(0).getReg(); @@ -1140,7 +1143,7 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword( BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) .addReg(Ptr).addReg(MaskLSB2); BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); - if (Subtarget->isLittle()) { + if (Subtarget.isLittle()) { BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); } else { unsigned Off = RegInfo.createVirtualRegister(RC); @@ -1228,7 +1231,8 @@ MachineBasicBlock * MipsTargetLowering::emitAtomicCmpSwap(MachineInstr *MI, MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned LL, SC, ZERO, BNE, BEQ; @@ -1310,7 +1314,8 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, MachineFunction *MF = BB->getParent(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); const TargetRegisterClass *RC = getRegClassFor(MVT::i32); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Dest = MI->getOperand(0).getReg(); @@ -1380,7 +1385,7 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, BuildMI(BB, DL, TII->get(Mips::AND), AlignedAddr) .addReg(Ptr).addReg(MaskLSB2); BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); - if (Subtarget->isLittle()) { + if (Subtarget.isLittle()) { BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); } else { unsigned Off = RegInfo.createVirtualRegister(RC); @@ -1445,8 +1450,10 @@ MipsTargetLowering::emitAtomicCmpSwapPartword(MachineInstr *MI, MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr *MI, MachineBasicBlock *BB) const { MachineFunction *MF = BB->getParent(); - const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetRegisterInfo *TRI = + getTargetMachine().getSubtargetImpl()->getRegisterInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = MF->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); MachineBasicBlock::iterator II(MI); @@ -1487,11 +1494,11 @@ SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); Addr = DAG.getExtLoad(ISD::SEXTLOAD, DL, PTy, Chain, Addr, MachinePointerInfo::getJumpTable(), MemVT, false, false, - 0); + false, 0); Chain = Addr.getValue(1); if ((getTargetMachine().getRelocationModel() == Reloc::PIC_) || - Subtarget->isABI_N64()) { + Subtarget.isABI_N64()) { // For PIC, the sequence is: // BRIND(load(Jumptable + index) + RelocBase) // RelocBase can be JumpTable, GOT or some sort of global base. @@ -1509,7 +1516,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue Dest = Op.getOperand(2); SDLoc DL(Op); - assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); + assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); // Return if flag is not set by a floating point comparison. @@ -1529,7 +1536,7 @@ SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { SDValue MipsTargetLowering:: lowerSELECT(SDValue Op, SelectionDAG &DAG) const { - assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); + assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); // Return if flag is not set by a floating point comparison. @@ -1555,7 +1562,7 @@ lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const } SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { - assert(!Subtarget->hasMips32r6() && !Subtarget->hasMips64r6()); + assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); SDValue Cond = createFPCmp(DAG, Op); assert(Cond.getOpcode() == MipsISD::FPCmp && @@ -1569,26 +1576,18 @@ SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { - // FIXME there isn't actually debug info here - SDLoc DL(Op); EVT Ty = Op.getValueType(); GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op); const GlobalValue *GV = N->getGlobal(); if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && - !Subtarget->isABI_N64()) { + !Subtarget.isABI_N64()) { const MipsTargetObjectFile &TLOF = (const MipsTargetObjectFile&)getObjFileLowering(); - // %gp_rel relocation - if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { - SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, 0, - MipsII::MO_GPREL); - SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, DL, - DAG.getVTList(MVT::i32), GA); - SDValue GPReg = DAG.getRegister(Mips::GP, MVT::i32); - return DAG.getNode(ISD::ADD, DL, MVT::i32, GPReg, GPRelNode); - } + if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) + // %gp_rel relocation + return getAddrGPRel(N, Ty, DAG); // %hi/%lo relocation return getAddrNonPIC(N, Ty, DAG); @@ -1596,7 +1595,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, if (GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa<Function>(GV))) return getAddrLocal(N, Ty, DAG, - Subtarget->isABI_N32() || Subtarget->isABI_N64()); + Subtarget.isABI_N32() || Subtarget.isABI_N64()); if (LargeGOT) return getAddrGlobalLargeGOT(N, Ty, DAG, MipsII::MO_GOT_HI16, @@ -1604,7 +1603,7 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, MachinePointerInfo::getGOT()); return getAddrGlobal(N, Ty, DAG, - (Subtarget->isABI_N32() || Subtarget->isABI_N64()) + (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT16, DAG.getEntryNode(), MachinePointerInfo::getGOT()); @@ -1616,11 +1615,11 @@ SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op, EVT Ty = Op.getValueType(); if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && - !Subtarget->isABI_N64()) + !Subtarget.isABI_N64()) return getAddrNonPIC(N, Ty, DAG); return getAddrLocal(N, Ty, DAG, - Subtarget->isABI_N32() || Subtarget->isABI_N64()); + Subtarget.isABI_N32() || Subtarget.isABI_N64()); } SDValue MipsTargetLowering:: @@ -1709,34 +1708,33 @@ lowerJumpTable(SDValue Op, SelectionDAG &DAG) const EVT Ty = Op.getValueType(); if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && - !Subtarget->isABI_N64()) + !Subtarget.isABI_N64()) return getAddrNonPIC(N, Ty, DAG); return getAddrLocal(N, Ty, DAG, - Subtarget->isABI_N32() || Subtarget->isABI_N64()); + Subtarget.isABI_N32() || Subtarget.isABI_N64()); } SDValue MipsTargetLowering:: lowerConstantPool(SDValue Op, SelectionDAG &DAG) const { - // gp_rel relocation - // FIXME: we should reference the constant pool using small data sections, - // but the asm printer currently doesn't support this feature without - // hacking it. This feature should come soon so we can uncomment the - // stuff below. - //if (IsInSmallSection(C->getType())) { - // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); - // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); - // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); EVT Ty = Op.getValueType(); if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && - !Subtarget->isABI_N64()) + !Subtarget.isABI_N64()) { + const MipsTargetObjectFile &TLOF = + (const MipsTargetObjectFile&)getObjFileLowering(); + + if (TLOF.IsConstantInSmallSection(N->getConstVal(), getTargetMachine())) + // %gp_rel relocation + return getAddrGPRel(N, Ty, DAG); + return getAddrNonPIC(N, Ty, DAG); + } return getAddrLocal(N, Ty, DAG, - Subtarget->isABI_N32() || Subtarget->isABI_N64()); + Subtarget.isABI_N32() || Subtarget.isABI_N64()); } SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { @@ -1754,6 +1752,65 @@ SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const { MachinePointerInfo(SV), false, false, 0); } +SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const { + SDNode *Node = Op.getNode(); + EVT VT = Node->getValueType(0); + SDValue Chain = Node->getOperand(0); + SDValue VAListPtr = Node->getOperand(1); + unsigned Align = Node->getConstantOperandVal(3); + const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); + SDLoc DL(Node); + unsigned ArgSlotSizeInBytes = + (Subtarget.isABI_N32() || Subtarget.isABI_N64()) ? 8 : 4; + + SDValue VAListLoad = DAG.getLoad(getPointerTy(), DL, Chain, VAListPtr, + MachinePointerInfo(SV), false, false, false, + 0); + SDValue VAList = VAListLoad; + + // Re-align the pointer if necessary. + // It should only ever be necessary for 64-bit types on O32 since the minimum + // argument alignment is the same as the maximum type alignment for N32/N64. + // + // FIXME: We currently align too often. The code generator doesn't notice + // when the pointer is still aligned from the last va_arg (or pair of + // va_args for the i64 on O32 case). + if (Align > getMinStackArgumentAlignment()) { + assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); + + VAList = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, + DAG.getConstant(Align - 1, + VAList.getValueType())); + + VAList = DAG.getNode(ISD::AND, DL, VAList.getValueType(), VAList, + DAG.getConstant(-(int64_t)Align, + VAList.getValueType())); + } + + // Increment the pointer, VAList, to the next vaarg. + unsigned ArgSizeInBytes = getDataLayout()->getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())); + SDValue Tmp3 = DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList, + DAG.getConstant(RoundUpToAlignment(ArgSizeInBytes, ArgSlotSizeInBytes), + VAList.getValueType())); + // Store the incremented VAList to the legalized pointer + Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr, + MachinePointerInfo(SV), false, false, 0); + + // In big-endian mode we must adjust the pointer when the load size is smaller + // than the argument slot size. We must also reduce the known alignment to + // match. For example in the N64 ABI, we must add 4 bytes to the offset to get + // the correct half of the slot, and reduce the alignment from 8 (slot + // alignment) down to 4 (type alignment). + if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) { + unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes; + VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList, + DAG.getIntPtrConstant(Adjustment)); + } + // Load the actual argument out of the pointer VAList + return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo(), false, false, + false, 0); +} + static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG, bool HasExtractInsert) { EVT TyX = Op.getOperand(0).getValueType(); @@ -1851,10 +1908,10 @@ static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, SDValue MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { - if (Subtarget->isGP64bit()) - return lowerFCOPYSIGN64(Op, DAG, Subtarget->hasExtractInsert()); + if (Subtarget.isGP64bit()) + return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert()); - return lowerFCOPYSIGN32(Op, DAG, Subtarget->hasExtractInsert()); + return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert()); } SDValue MipsTargetLowering:: @@ -1869,7 +1926,7 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, - Subtarget->isABI_N64() ? Mips::FP_64 : Mips::FP, VT); + Subtarget.isABI_N64() ? Mips::FP_64 : Mips::FP, VT); return FrameAddr; } @@ -1885,7 +1942,7 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MVT VT = Op.getSimpleValueType(); - unsigned RA = Subtarget->isABI_N64() ? Mips::RA_64 : Mips::RA; + unsigned RA = Subtarget.isABI_N64() ? Mips::RA_64 : Mips::RA; MFI->setReturnAddressIsTaken(true); // Return RA, which contains the return address. Mark it an implicit live-in. @@ -1907,12 +1964,12 @@ SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) SDValue Offset = Op.getOperand(1); SDValue Handler = Op.getOperand(2); SDLoc DL(Op); - EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32; + EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32; // Store stack offset in V1, store jump target in V0. Glue CopyToReg and // EH_RETURN nodes, so that instructions are emitted back-to-back. - unsigned OffsetReg = Subtarget->isABI_N64() ? Mips::V1_64 : Mips::V1; - unsigned AddrReg = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0; + unsigned OffsetReg = Subtarget.isABI_N64() ? Mips::V1_64 : Mips::V1; + unsigned AddrReg = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0; Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue()); Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1)); return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain, @@ -2025,7 +2082,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { LoadSDNode *LD = cast<LoadSDNode>(Op); EVT MemVT = LD->getMemoryVT(); - if (Subtarget->systemSupportsUnalignedAccess()) + if (Subtarget.systemSupportsUnalignedAccess()) return Op; // Return if load is aligned or if MemVT is neither i32 nor i64. @@ -2033,7 +2090,7 @@ SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { ((MemVT != MVT::i32) && (MemVT != MVT::i64))) return SDValue(); - bool IsLittle = Subtarget->isLittle(); + bool IsLittle = Subtarget.isLittle(); EVT VT = Op.getValueType(); ISD::LoadExtType ExtType = LD->getExtensionType(); SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); @@ -2151,10 +2208,10 @@ SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { EVT MemVT = SD->getMemoryVT(); // Lower unaligned integer stores. - if (!Subtarget->systemSupportsUnalignedAccess() && + if (!Subtarget.systemSupportsUnalignedAccess() && (SD->getAlignment() < MemVT.getSizeInBits() / 8) && ((MemVT == MVT::i32) || (MemVT == MVT::i64))) - return lowerUnalignedIntStore(SD, DAG, Subtarget->isLittle()); + return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle()); return lowerFP_TO_SINT_STORE(SD, DAG); } @@ -2201,7 +2258,7 @@ SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op, // an argument. Otherwise, passed in A1, A2, A3 and stack. // f64 - Only passed in two aliased f32 registers if no int reg has been used // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is -// not used, it must be shadowed. If only A3 is avaiable, shadow it and +// not used, it must be shadowed. If only A3 is available, shadow it and // go to stack. // // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. @@ -2299,6 +2356,10 @@ static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs); } +static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, + CCState &State) LLVM_ATTRIBUTE_UNUSED; + #include "MipsGenCallingConv.inc" //===----------------------------------------------------------------------===// @@ -2333,15 +2394,21 @@ void MipsTargetLowering:: getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const { // Insert node "GP copy globalreg" before call to function. // // R_MIPS_CALL* operators (emitted when non-internal functions are called // in PIC mode) allow symbols to be resolved via lazy binding. // The lazy binding stub requires GP to point to the GOT. - if (IsPICCall && !InternalLinkage) { - unsigned GPReg = Subtarget->isABI_N64() ? Mips::GP_64 : Mips::GP; - EVT Ty = Subtarget->isABI_N64() ? MVT::i64 : MVT::i32; + // Note that we don't need GP to point to the GOT for indirect calls + // (when R_MIPS_CALL* is not used for the call) because Mips linker generates + // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs + // used for the function (that is, Mips linker doesn't generate lazy binding + // stub for a function whose address is taken in the program). + if (IsPICCall && !InternalLinkage && IsCallReloc) { + unsigned GPReg = Subtarget.isABI_N64() ? Mips::GP_64 : Mips::GP; + EVT Ty = Subtarget.isABI_N64() ? MVT::i64 : MVT::i32; RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty))); } @@ -2364,10 +2431,11 @@ getOpndList(SmallVectorImpl<SDValue> &Ops, RegsToPass[i].second.getValueType())); // Add a register mask operand representing the call-preserved registers. - const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); + const TargetRegisterInfo *TRI = + getTargetMachine().getSubtargetImpl()->getRegisterInfo(); const uint32_t *Mask = TRI->getCallPreservedMask(CLI.CallConv); assert(Mask && "Missing call preserved mask for calling convention"); - if (Subtarget->inMips16HardFloat()) { + if (Subtarget.inMips16HardFloat()) { if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) { llvm::StringRef Sym = G->getGlobal()->getName(); Function *F = G->getGlobal()->getParent()->getFunction(Sym); @@ -2400,31 +2468,30 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); - MipsCC::SpecialCallingConvType SpecialCallingConv = - getSpecialCallingConv(Callee); - MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), - CCInfo, SpecialCallingConv); + MipsCCState CCInfo( + CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(), + MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget)); - MipsCCInfo.analyzeCallOperands(Outs, IsVarArg, - Subtarget->mipsSEUsesSoftFloat(), - Callee.getNode(), CLI.getArgs()); + // Allocate the reserved argument area. It seems strange to do this from the + // caller side but removing it breaks the frame size calculation. + const MipsABIInfo &ABI = Subtarget.getABI(); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); + + CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(), Callee.getNode()); // Get a count of how many bytes are to be pushed on the stack. unsigned NextStackOffset = CCInfo.getNextStackOffset(); // Check if it's really possible to do a tail call. if (IsTailCall) - IsTailCall = - isEligibleForTailCallOptimization(MipsCCInfo, NextStackOffset, - *MF.getInfo<MipsFunctionInfo>()); + IsTailCall = isEligibleForTailCallOptimization( + CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " @@ -2444,13 +2511,14 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Chain = DAG.getCALLSEQ_START(Chain, NextStackOffsetVal, DL); SDValue StackPtr = DAG.getCopyFromReg( - Chain, DL, Subtarget->isABI_N64() ? Mips::SP_64 : Mips::SP, + Chain, DL, Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP, getPointerTy()); // With EABI is it possible to have 16 args on registers. std::deque< std::pair<unsigned, SDValue> > RegsToPass; SmallVector<SDValue, 8> MemOpChains; - MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); + + CCInfo.rewindByValRegsInfo(); // Walk the register/memloc assignments, inserting copies/loads. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { @@ -2458,23 +2526,30 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, CCValAssign &VA = ArgLocs[i]; MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); ISD::ArgFlagsTy Flags = Outs[i].Flags; + bool UseUpperBits = false; // ByVal Arg. if (Flags.isByVal()) { + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); - assert(ByValArg != MipsCCInfo.byval_end()); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); assert(!IsTailCall && "Do not tail-call optimize if there is a byval argument."); passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg, - MipsCCInfo, *ByValArg, Flags, Subtarget->isLittle()); - ++ByValArg; + FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(), + VA); + CCInfo.nextInRegsParam(); continue; } // Promote the value if needed. switch (VA.getLocInfo()) { - default: llvm_unreachable("Unknown loc info!"); + default: + llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: if (VA.isRegLoc()) { if ((ValVT == MVT::f32 && LocVT == MVT::i32) || @@ -2486,7 +2561,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, Arg, DAG.getConstant(0, MVT::i32)); SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Arg, DAG.getConstant(1, MVT::i32)); - if (!Subtarget->isLittle()) + if (!Subtarget.isLittle()) std::swap(Lo, Hi); unsigned LocRegLo = VA.getLocReg(); unsigned LocRegHigh = getNextIntArgReg(LocRegLo); @@ -2496,17 +2571,37 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, } } break; + case CCValAssign::BCvt: + Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + // Fallthrough case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + // Fallthrough case CCValAssign::ZExt: Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + // Fallthrough case CCValAssign::AExt: Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); break; } + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Arg = DAG.getNode( + ISD::SHL, DL, VA.getLocVT(), Arg, + DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); + } + // Arguments that can be passed on register must be kept at // RegsToPass vector if (VA.isRegLoc()) { @@ -2532,9 +2627,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol // node so that legalize doesn't hack it. bool IsPICCall = - (Subtarget->isABI_N64() || IsPIC); // true if calls are translated to + (Subtarget.isABI_N64() || IsPIC); // true if calls are translated to // jalr $25 - bool GlobalOrExternal = false, InternalLinkage = false; + bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; SDValue CalleeLo; EVT Ty = Callee.getValueType(); @@ -2545,14 +2640,17 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (InternalLinkage) Callee = getAddrLocal(G, Ty, DAG, - Subtarget->isABI_N32() || Subtarget->isABI_N64()); - else if (LargeGOT) + Subtarget.isABI_N32() || Subtarget.isABI_N64()); + else if (LargeGOT) { Callee = getAddrGlobalLargeGOT(G, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(Val)); - else + IsCallReloc = true; + } else { Callee = getAddrGlobal(G, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(Val)); + IsCallReloc = true; + } } else Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, MipsII::MO_NO_FLAG); @@ -2561,16 +2659,19 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { const char *Sym = S->getSymbol(); - if (!Subtarget->isABI_N64() && !IsPIC) // !N64 && static + if (!Subtarget.isABI_N64() && !IsPIC) // !N64 && static Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), MipsII::MO_NO_FLAG); - else if (LargeGOT) + else if (LargeGOT) { Callee = getAddrGlobalLargeGOT(S, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, FuncInfo->callPtrInfo(Sym)); - else // N64 || PIC + IsCallReloc = true; + } else { // N64 || PIC Callee = getAddrGlobal(S, Ty, DAG, MipsII::MO_GOT_CALL, Chain, FuncInfo->callPtrInfo(Sym)); + IsCallReloc = true; + } GlobalOrExternal = true; } @@ -2579,7 +2680,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, - CLI, Callee, Chain); + IsCallReloc, CLI, Callee, Chain); if (IsTailCall) return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); @@ -2594,39 +2695,68 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Handle result values, copying them out of physregs into vregs that we // return. - return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, - Ins, DL, DAG, InVals, CLI.Callee.getNode(), CLI.RetTy); + return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG, + InVals, CLI); } /// LowerCallResult - Lower the result values of a call into the /// appropriate copies out of appropriate physical registers. -SDValue -MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, - CallingConv::ID CallConv, bool IsVarArg, - const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc DL, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals, - const SDNode *CallNode, - const Type *RetTy) const { +SDValue MipsTargetLowering::LowerCallResult( + SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, + const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals, + TargetLowering::CallLoweringInfo &CLI) const { // Assign locations to each value returned by this call. SmallVector<CCValAssign, 16> RVLocs; - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - getTargetMachine(), RVLocs, *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), - CCInfo); - - MipsCCInfo.analyzeCallResult(Ins, Subtarget->mipsSEUsesSoftFloat(), - CallNode, RetTy); + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); + CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI); // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { + CCValAssign &VA = RVLocs[i]; + assert(VA.isRegLoc() && "Can only return in registers!"); + SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(), RVLocs[i].getLocVT(), InFlag); Chain = Val.getValue(1); InFlag = Val.getValue(2); - if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) - Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getValVT(), Val); + if (VA.isUpperBitsInLoc()) { + unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + unsigned Shift = + VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; + Val = DAG.getNode( + Shift, DL, VA.getLocVT(), Val, + DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); + } + + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val); + break; + case CCValAssign::AExt: + case CCValAssign::AExtUpper: + Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); + break; + case CCValAssign::ZExt: + case CCValAssign::ZExtUpper: + Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, + DAG.getValueType(VA.getValVT())); + Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); + break; + case CCValAssign::SExt: + case CCValAssign::SExtUpper: + Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, + DAG.getValueType(VA.getValVT())); + Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); + break; + } InVals.push_back(Val); } @@ -2634,6 +2764,60 @@ MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, return Chain; } +static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA, + EVT ArgVT, SDLoc DL, SelectionDAG &DAG) { + MVT LocVT = VA.getLocVT(); + EVT ValVT = VA.getValVT(); + + // Shift into the upper bits if necessary. + switch (VA.getLocInfo()) { + default: + break; + case CCValAssign::AExtUpper: + case CCValAssign::SExtUpper: + case CCValAssign::ZExtUpper: { + unsigned ValSizeInBits = ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + unsigned Opcode = + VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA; + Val = DAG.getNode( + Opcode, DL, VA.getLocVT(), Val, + DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); + break; + } + } + + // If this is an value smaller than the argument slot size (32-bit for O32, + // 64-bit for N32/N64), it has been promoted in some way to the argument slot + // size. Extract the value and insert any appropriate assertions regarding + // sign/zero extension. + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::AExtUpper: + case CCValAssign::AExt: + Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); + break; + case CCValAssign::SExtUpper: + case CCValAssign::SExt: + Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT)); + Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); + break; + case CCValAssign::ZExtUpper: + case CCValAssign::ZExt: + Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT)); + Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val); + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val); + break; + } + + return Val; +} + //===----------------------------------------------------------------------===// // Formal Arguments Calling Convention Implementation //===----------------------------------------------------------------------===// @@ -2658,20 +2842,19 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // Assign locations to all of the incoming arguments. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), - CCInfo); + MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + const MipsABIInfo &ABI = Subtarget.getABI(); + CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1); Function::const_arg_iterator FuncArg = DAG.getMachineFunction().getFunction()->arg_begin(); - bool UseSoftFloat = Subtarget->mipsSEUsesSoftFloat(); - MipsCCInfo.analyzeFormalArguments(Ins, UseSoftFloat, FuncArg); + CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg); MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(), - MipsCCInfo.hasByValArg()); + CCInfo.getInRegsParamsCount() > 0); unsigned CurArgIdx = 0; - MipsCC::byval_iterator ByValArg = MipsCCInfo.byval_begin(); + CCInfo.rewindByValRegsInfo(); for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; @@ -2682,12 +2865,16 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, bool IsRegLoc = VA.isRegLoc(); if (Flags.isByVal()) { + unsigned FirstByValReg, LastByValReg; + unsigned ByValIdx = CCInfo.getInRegsParamsProcessed(); + CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg); + assert(Flags.getByValSize() && "ByVal args of size 0 should have been ignored by front-end."); - assert(ByValArg != MipsCCInfo.byval_end()); + assert(ByValIdx < CCInfo.getInRegsParamsCount()); copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg, - MipsCCInfo, *ByValArg); - ++ByValArg; + FirstByValReg, LastByValReg, VA, CCInfo); + CCInfo.nextInRegsParam(); continue; } @@ -2702,20 +2889,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC); SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); - // If this is an 8 or 16-bit value, it has been passed promoted - // to 32 bits. Insert an assert[sz]ext to capture this, then - // truncate to the right size. - if (VA.getLocInfo() != CCValAssign::Full) { - unsigned Opcode = 0; - if (VA.getLocInfo() == CCValAssign::SExt) - Opcode = ISD::AssertSext; - else if (VA.getLocInfo() == CCValAssign::ZExt) - Opcode = ISD::AssertZext; - if (Opcode) - ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, - DAG.getValueType(ValVT)); - ArgValue = DAG.getNode(ISD::TRUNCATE, DL, ValVT, ArgValue); - } + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); // Handle floating point arguments passed in integer registers and // long double arguments passed in floating point registers. @@ -2723,12 +2897,12 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, (RegVT == MVT::i64 && ValVT == MVT::f64) || (RegVT == MVT::f64 && ValVT == MVT::i64)) ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue); - else if (Subtarget->isABI_O32() && RegVT == MVT::i32 && + else if (Subtarget.isABI_O32() && RegVT == MVT::i32 && ValVT == MVT::f64) { unsigned Reg2 = addLiveIn(DAG.getMachineFunction(), getNextIntArgReg(ArgReg), RC); SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT); - if (!Subtarget->isLittle()) + if (!Subtarget.isLittle()) std::swap(ArgValue, ArgValue2); ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, ArgValue, ArgValue2); @@ -2736,21 +2910,34 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, InVals.push_back(ArgValue); } else { // VA.isRegLoc() + MVT LocVT = VA.getLocVT(); + + if (Subtarget.isABI_O32()) { + // We ought to be able to use LocVT directly but O32 sets it to i32 + // when allocating floating point values to integer registers. + // This shouldn't influence how we load the value into registers unless + // we are targetting softfloat. + if (VA.getValVT().isFloatingPoint() && !Subtarget.abiUsesSoftFloat()) + LocVT = VA.getValVT(); + } // sanity check assert(VA.isMemLoc()); // The stack pointer offset is relative to the caller stack frame. - int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, + int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8, VA.getLocMemOffset(), true); // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - SDValue Load = DAG.getLoad(ValVT, DL, Chain, FIN, - MachinePointerInfo::getFixedStack(FI), - false, false, false, 0); - InVals.push_back(Load); - OutChains.push_back(Load.getValue(1)); + SDValue ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(FI), + false, false, false, 0); + OutChains.push_back(ArgValue.getValue(1)); + + ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG); + + InVals.push_back(ArgValue); } } @@ -2762,7 +2949,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, unsigned Reg = MipsFI->getSRetReturnReg(); if (!Reg) { Reg = MF.getRegInfo().createVirtualRegister( - getRegClassFor(Subtarget->isABI_N64() ? MVT::i64 : MVT::i32)); + getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32)); MipsFI->setSRetReturnReg(Reg); } SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); @@ -2772,7 +2959,7 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, } if (IsVarArg) - writeVarArgRegs(OutChains, MipsCCInfo, Chain, DL, DAG); + writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo); // All stores are grouped in one node to allow the matching between // the size of Ins and InVals. This only happens when on varg functions @@ -2794,8 +2981,7 @@ MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const { SmallVector<CCValAssign, 16> RVLocs; - CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), - RVLocs, Context); + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); return CCInfo.CheckReturn(Outs, RetCC_Mips); } @@ -2811,14 +2997,10 @@ MipsTargetLowering::LowerReturn(SDValue Chain, MachineFunction &MF = DAG.getMachineFunction(); // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, IsVarArg, MF, getTargetMachine(), RVLocs, - *DAG.getContext()); - MipsCC MipsCCInfo(CallConv, Subtarget->isABI_O32(), Subtarget->isFP64bit(), - CCInfo); + MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext()); // Analyze return values. - MipsCCInfo.analyzeReturn(Outs, Subtarget->mipsSEUsesSoftFloat(), - MF.getFunction()->getReturnType()); + CCInfo.AnalyzeReturn(Outs, RetCC_Mips); SDValue Flag; SmallVector<SDValue, 4> RetOps(1, Chain); @@ -2828,9 +3010,43 @@ MipsTargetLowering::LowerReturn(SDValue Chain, SDValue Val = OutVals[i]; CCValAssign &VA = RVLocs[i]; assert(VA.isRegLoc() && "Can only return in registers!"); + bool UseUpperBits = false; - if (RVLocs[i].getValVT() != RVLocs[i].getLocVT()) - Val = DAG.getNode(ISD::BITCAST, DL, RVLocs[i].getLocVT(), Val); + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val); + break; + case CCValAssign::AExtUpper: + UseUpperBits = true; + // Fallthrough + case CCValAssign::AExt: + Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::ZExtUpper: + UseUpperBits = true; + // Fallthrough + case CCValAssign::ZExt: + Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); + break; + case CCValAssign::SExtUpper: + UseUpperBits = true; + // Fallthrough + case CCValAssign::SExt: + Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); + break; + } + + if (UseUpperBits) { + unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits(); + unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); + Val = DAG.getNode( + ISD::SHL, DL, VA.getLocVT(), Val, + DAG.getConstant(LocSizeInBits - ValSizeInBits, VA.getLocVT())); + } Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag); @@ -2850,7 +3066,7 @@ MipsTargetLowering::LowerReturn(SDValue Chain, if (!Reg) llvm_unreachable("sret virtual register not created in the entry block"); SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); - unsigned V0 = Subtarget->isABI_N64() ? Mips::V0_64 : Mips::V0; + unsigned V0 = Subtarget.isABI_N64() ? Mips::V0_64 : Mips::V0; Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag); Flag = Chain.getValue(1); @@ -2928,7 +3144,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight( weight = CW_Register; break; case 'f': // FPU or MSA register - if (Subtarget->hasMSA() && type->isVectorTy() && + if (Subtarget.hasMSA() && type->isVectorTy() && cast<VectorType>(type)->getBitWidth() == 128) weight = CW_Register; else if (type->isFloatTy()) @@ -2962,7 +3178,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight( /// that is returned indicates whether parsing was successful. The second flag /// is true if the numeric part exists. static std::pair<bool, bool> -parsePhysicalReg(const StringRef &C, std::string &Prefix, +parsePhysicalReg(StringRef C, std::string &Prefix, unsigned long long &Reg) { if (C.front() != '{' || C.back() != '}') return std::make_pair(false, false); @@ -2983,8 +3199,9 @@ parsePhysicalReg(const StringRef &C, std::string &Prefix, } std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering:: -parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { - const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); +parseRegForInlineAsmConstraint(StringRef C, MVT VT) const { + const TargetRegisterInfo *TRI = + getTargetMachine().getSubtargetImpl()->getRegisterInfo(); const TargetRegisterClass *RC; std::string Prefix; unsigned long long Reg; @@ -3034,7 +3251,7 @@ parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const { // If the size of FP registers is 64-bit or Reg is an even number, select // the 64-bit register class. Otherwise, select the 32-bit register class. if (VT == MVT::Other) - VT = (Subtarget->isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; + VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32; RC = getRegClassFor(VT); @@ -3067,13 +3284,13 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const case 'y': // Same as 'r'. Exists for compatibility. case 'r': if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) { - if (Subtarget->inMips16Mode()) + if (Subtarget.inMips16Mode()) return std::make_pair(0U, &Mips::CPU16RegsRegClass); return std::make_pair(0U, &Mips::GPR32RegClass); } - if (VT == MVT::i64 && !Subtarget->isGP64bit()) + if (VT == MVT::i64 && !Subtarget.isGP64bit()) return std::make_pair(0U, &Mips::GPR32RegClass); - if (VT == MVT::i64 && Subtarget->isGP64bit()) + if (VT == MVT::i64 && Subtarget.isGP64bit()) return std::make_pair(0U, &Mips::GPR64RegClass); // This will generate an error message return std::make_pair(0U, nullptr); @@ -3088,8 +3305,8 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const return std::make_pair(0U, &Mips::MSA128DRegClass); else if (VT == MVT::f32) return std::make_pair(0U, &Mips::FGR32RegClass); - else if ((VT == MVT::f64) && (!Subtarget->isSingleFloat())) { - if (Subtarget->isFP64bit()) + else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) { + if (Subtarget.isFP64bit()) return std::make_pair(0U, &Mips::FGR64RegClass); return std::make_pair(0U, &Mips::AFGR64RegClass); } @@ -3245,7 +3462,7 @@ EVT MipsTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const { - if (Subtarget->hasMips64()) + if (Subtarget.hasMips64()) return MVT::i64; return MVT::i32; @@ -3260,291 +3477,33 @@ bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { } unsigned MipsTargetLowering::getJumpTableEncoding() const { - if (Subtarget->isABI_N64()) + if (Subtarget.isABI_N64()) return MachineJumpTableInfo::EK_GPRel64BlockAddress; return TargetLowering::getJumpTableEncoding(); } -/// This function returns true if CallSym is a long double emulation routine. -static bool isF128SoftLibCall(const char *CallSym) { - const char *const LibCalls[] = - {"__addtf3", "__divtf3", "__eqtf2", "__extenddftf2", "__extendsftf2", - "__fixtfdi", "__fixtfsi", "__fixtfti", "__fixunstfdi", "__fixunstfsi", - "__fixunstfti", "__floatditf", "__floatsitf", "__floattitf", - "__floatunditf", "__floatunsitf", "__floatuntitf", "__getf2", "__gttf2", - "__letf2", "__lttf2", "__multf3", "__netf2", "__powitf2", "__subtf3", - "__trunctfdf2", "__trunctfsf2", "__unordtf2", - "ceill", "copysignl", "cosl", "exp2l", "expl", "floorl", "fmal", "fmodl", - "log10l", "log2l", "logl", "nearbyintl", "powl", "rintl", "sinl", "sqrtl", - "truncl"}; - - const char *const *End = LibCalls + array_lengthof(LibCalls); - - // Check that LibCalls is sorted alphabetically. - MipsTargetLowering::LTStr Comp; - -#ifndef NDEBUG - for (const char *const *I = LibCalls; I < End - 1; ++I) - assert(Comp(*I, *(I + 1))); -#endif - - return std::binary_search(LibCalls, End, CallSym, Comp); -} - -/// This function returns true if Ty is fp128 or i128 which was originally a -/// fp128. -static bool originalTypeIsF128(const Type *Ty, const SDNode *CallNode) { - if (Ty->isFP128Ty()) - return true; - - const ExternalSymbolSDNode *ES = - dyn_cast_or_null<const ExternalSymbolSDNode>(CallNode); - - // If the Ty is i128 and the function being called is a long double emulation - // routine, then the original type is f128. - return (ES && Ty->isIntegerTy(128) && isF128SoftLibCall(ES->getSymbol())); -} - -MipsTargetLowering::MipsCC::SpecialCallingConvType - MipsTargetLowering::getSpecialCallingConv(SDValue Callee) const { - MipsCC::SpecialCallingConvType SpecialCallingConv = - MipsCC::NoSpecialCallingConv; - if (Subtarget->inMips16HardFloat()) { - if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { - llvm::StringRef Sym = G->getGlobal()->getName(); - Function *F = G->getGlobal()->getParent()->getFunction(Sym); - if (F && F->hasFnAttribute("__Mips16RetHelper")) { - SpecialCallingConv = MipsCC::Mips16RetHelperConv; - } - } - } - return SpecialCallingConv; -} - -MipsTargetLowering::MipsCC::MipsCC( - CallingConv::ID CC, bool IsO32_, bool IsFP64_, CCState &Info, - MipsCC::SpecialCallingConvType SpecialCallingConv_) - : CCInfo(Info), CallConv(CC), IsO32(IsO32_), IsFP64(IsFP64_), - SpecialCallingConv(SpecialCallingConv_){ - // Pre-allocate reserved argument area. - CCInfo.AllocateStack(reservedArgArea(), 1); -} - - -void MipsTargetLowering::MipsCC:: -analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Args, - bool IsVarArg, bool IsSoftFloat, const SDNode *CallNode, - std::vector<ArgListEntry> &FuncArgs) { - assert((CallConv != CallingConv::Fast || !IsVarArg) && - "CallingConv::Fast shouldn't be used for vararg functions."); - - unsigned NumOpnds = Args.size(); - llvm::CCAssignFn *FixedFn = fixedArgFn(), *VarFn = varArgFn(); - - for (unsigned I = 0; I != NumOpnds; ++I) { - MVT ArgVT = Args[I].VT; - ISD::ArgFlagsTy ArgFlags = Args[I].Flags; - bool R; - - if (ArgFlags.isByVal()) { - handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); - continue; - } - - if (IsVarArg && !Args[I].IsFixed) - R = VarFn(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); - else { - MVT RegVT = getRegVT(ArgVT, FuncArgs[Args[I].OrigArgIndex].Ty, CallNode, - IsSoftFloat); - R = FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo); - } - - if (R) { -#ifndef NDEBUG - dbgs() << "Call operand #" << I << " has unhandled type " - << EVT(ArgVT).getEVTString(); -#endif - llvm_unreachable(nullptr); - } - } -} - -void MipsTargetLowering::MipsCC:: -analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Args, - bool IsSoftFloat, Function::const_arg_iterator FuncArg) { - unsigned NumArgs = Args.size(); - llvm::CCAssignFn *FixedFn = fixedArgFn(); - unsigned CurArgIdx = 0; - - for (unsigned I = 0; I != NumArgs; ++I) { - MVT ArgVT = Args[I].VT; - ISD::ArgFlagsTy ArgFlags = Args[I].Flags; - std::advance(FuncArg, Args[I].OrigArgIndex - CurArgIdx); - CurArgIdx = Args[I].OrigArgIndex; - - if (ArgFlags.isByVal()) { - handleByValArg(I, ArgVT, ArgVT, CCValAssign::Full, ArgFlags); - continue; - } - - MVT RegVT = getRegVT(ArgVT, FuncArg->getType(), nullptr, IsSoftFloat); - - if (!FixedFn(I, ArgVT, RegVT, CCValAssign::Full, ArgFlags, CCInfo)) - continue; - -#ifndef NDEBUG - dbgs() << "Formal Arg #" << I << " has unhandled type " - << EVT(ArgVT).getEVTString(); -#endif - llvm_unreachable(nullptr); - } -} - -template<typename Ty> -void MipsTargetLowering::MipsCC:: -analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, - const SDNode *CallNode, const Type *RetTy) const { - CCAssignFn *Fn; - - if (IsSoftFloat && originalTypeIsF128(RetTy, CallNode)) - Fn = RetCC_F128Soft; - else - Fn = RetCC_Mips; - - for (unsigned I = 0, E = RetVals.size(); I < E; ++I) { - MVT VT = RetVals[I].VT; - ISD::ArgFlagsTy Flags = RetVals[I].Flags; - MVT RegVT = this->getRegVT(VT, RetTy, CallNode, IsSoftFloat); - - if (Fn(I, VT, RegVT, CCValAssign::Full, Flags, this->CCInfo)) { -#ifndef NDEBUG - dbgs() << "Call result #" << I << " has unhandled type " - << EVT(VT).getEVTString() << '\n'; -#endif - llvm_unreachable(nullptr); - } - } -} - -void MipsTargetLowering::MipsCC:: -analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, bool IsSoftFloat, - const SDNode *CallNode, const Type *RetTy) const { - analyzeReturn(Ins, IsSoftFloat, CallNode, RetTy); -} - -void MipsTargetLowering::MipsCC:: -analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, bool IsSoftFloat, - const Type *RetTy) const { - analyzeReturn(Outs, IsSoftFloat, nullptr, RetTy); -} - -void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT, - MVT LocVT, - CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags) { - assert(ArgFlags.getByValSize() && "Byval argument's size shouldn't be 0."); - - struct ByValArgInfo ByVal; - unsigned RegSize = regSize(); - unsigned ByValSize = RoundUpToAlignment(ArgFlags.getByValSize(), RegSize); - unsigned Align = std::min(std::max(ArgFlags.getByValAlign(), RegSize), - RegSize * 2); - - if (useRegsForByval()) - allocateRegs(ByVal, ByValSize, Align); - - // Allocate space on caller's stack. - ByVal.Address = CCInfo.AllocateStack(ByValSize - RegSize * ByVal.NumRegs, - Align); - CCInfo.addLoc(CCValAssign::getMem(ValNo, ValVT, ByVal.Address, LocVT, - LocInfo)); - ByValArgs.push_back(ByVal); -} - -unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const { - return IsO32 ? array_lengthof(O32IntRegs) : array_lengthof(Mips64IntRegs); -} - -unsigned MipsTargetLowering::MipsCC::reservedArgArea() const { - return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0; -} - -const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const { - return IsO32 ? O32IntRegs : Mips64IntRegs; -} - -llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const { - if (CallConv == CallingConv::Fast) - return CC_Mips_FastCC; - - if (SpecialCallingConv == Mips16RetHelperConv) - return CC_Mips16RetHelper; - return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN; -} - -llvm::CCAssignFn *MipsTargetLowering::MipsCC::varArgFn() const { - return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg; -} - -const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const { - return IsO32 ? O32IntRegs : Mips64DPRegs; -} - -void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal, - unsigned ByValSize, - unsigned Align) { - unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs(); - const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs(); - assert(!(ByValSize % RegSize) && !(Align % RegSize) && - "Byval argument's size and alignment should be a multiple of" - "RegSize."); - - ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs); - - // If Align > RegSize, the first arg register must be even. - if ((Align > RegSize) && (ByVal.FirstIdx % 2)) { - CCInfo.AllocateReg(IntArgRegs[ByVal.FirstIdx], ShadowRegs[ByVal.FirstIdx]); - ++ByVal.FirstIdx; - } - - // Mark the registers allocated. - for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs); - ByValSize -= RegSize, ++I, ++ByVal.NumRegs) - CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]); -} - -MVT MipsTargetLowering::MipsCC::getRegVT(MVT VT, const Type *OrigTy, - const SDNode *CallNode, - bool IsSoftFloat) const { - if (IsSoftFloat || IsO32) - return VT; - - // Check if the original type was fp128. - if (originalTypeIsF128(OrigTy, CallNode)) { - assert(VT == MVT::i64); - return MVT::f64; - } - - return VT; -} - -void MipsTargetLowering:: -copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, - SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, - SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg, - const MipsCC &CC, const ByValArgInfo &ByVal) const { +void MipsTargetLowering::copyByValRegs( + SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG, + const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, + const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, + const CCValAssign &VA, MipsCCState &State) const { MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - unsigned RegAreaSize = ByVal.NumRegs * CC.regSize(); + unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); + unsigned NumRegs = LastReg - FirstReg; + unsigned RegAreaSize = NumRegs * GPRSizeInBytes; unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize); int FrameObjOffset; + const MipsABIInfo &ABI = Subtarget.getABI(); + ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs(); if (RegAreaSize) - FrameObjOffset = (int)CC.reservedArgArea() - - (int)((CC.numIntArgRegs() - ByVal.FirstIdx) * CC.regSize()); + FrameObjOffset = + (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - + (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes); else - FrameObjOffset = ByVal.Address; + FrameObjOffset = VA.getLocMemOffset(); // Create frame object. EVT PtrTy = getPointerTy(); @@ -3552,17 +3511,17 @@ copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SDValue FIN = DAG.getFrameIndex(FI, PtrTy); InVals.push_back(FIN); - if (!ByVal.NumRegs) + if (!NumRegs) return; // Copy arg registers. - MVT RegTy = MVT::getIntegerVT(CC.regSize() * 8); + MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8); const TargetRegisterClass *RC = getRegClassFor(RegTy); - for (unsigned I = 0; I < ByVal.NumRegs; ++I) { - unsigned ArgReg = CC.intArgRegs()[ByVal.FirstIdx + I]; + for (unsigned I = 0; I < NumRegs; ++I) { + unsigned ArgReg = ByValArgRegs[FirstReg + I]; unsigned VReg = addLiveIn(MF, ArgReg, RC); - unsigned Offset = I * CC.regSize(); + unsigned Offset = I * GPRSizeInBytes; SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN, DAG.getConstant(Offset, PtrTy)); SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy), @@ -3573,34 +3532,34 @@ copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, } // Copy byVal arg to registers and stack. -void MipsTargetLowering:: -passByValArg(SDValue Chain, SDLoc DL, - std::deque< std::pair<unsigned, SDValue> > &RegsToPass, - SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, - MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, - const MipsCC &CC, const ByValArgInfo &ByVal, - const ISD::ArgFlagsTy &Flags, bool isLittle) const { +void MipsTargetLowering::passByValArg( + SDValue Chain, SDLoc DL, + std::deque<std::pair<unsigned, SDValue>> &RegsToPass, + SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, + MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, + unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, + const CCValAssign &VA) const { unsigned ByValSizeInBytes = Flags.getByValSize(); unsigned OffsetInBytes = 0; // From beginning of struct - unsigned RegSizeInBytes = CC.regSize(); + unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes); EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); + unsigned NumRegs = LastReg - FirstReg; - if (ByVal.NumRegs) { - const MCPhysReg *ArgRegs = CC.intArgRegs(); - bool LeftoverBytes = (ByVal.NumRegs * RegSizeInBytes > ByValSizeInBytes); + if (NumRegs) { + const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetByValArgRegs(); + bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes); unsigned I = 0; // Copy words to registers. - for (; I < ByVal.NumRegs - LeftoverBytes; - ++I, OffsetInBytes += RegSizeInBytes) { + for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) { SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, DAG.getConstant(OffsetInBytes, PtrTy)); SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr, MachinePointerInfo(), false, false, false, Alignment); MemOpChains.push_back(LoadVal.getValue(1)); - unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; + unsigned ArgReg = ArgRegs[FirstReg + I]; RegsToPass.push_back(std::make_pair(ArgReg, LoadVal)); } @@ -3610,9 +3569,6 @@ passByValArg(SDValue Chain, SDLoc DL, // Copy the remainder of the byval argument with sub-word loads and shifts. if (LeftoverBytes) { - assert((ByValSizeInBytes > OffsetInBytes) && - (ByValSizeInBytes < OffsetInBytes + RegSizeInBytes) && - "Size of the remainder should be smaller than RegSizeInBytes."); SDValue Val; for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0; @@ -3627,7 +3583,8 @@ passByValArg(SDValue Chain, SDLoc DL, DAG.getConstant(OffsetInBytes, PtrTy)); SDValue LoadVal = DAG.getExtLoad( ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(), - MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, Alignment); + MVT::getIntegerVT(LoadSizeInBytes * 8), false, false, false, + Alignment); MemOpChains.push_back(LoadVal.getValue(1)); // Shift the loaded value. @@ -3651,7 +3608,7 @@ passByValArg(SDValue Chain, SDLoc DL, Alignment = std::min(Alignment, LoadSizeInBytes); } - unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; + unsigned ArgReg = ArgRegs[FirstReg + I]; RegsToPass.push_back(std::make_pair(ArgReg, Val)); return; } @@ -3662,7 +3619,7 @@ passByValArg(SDValue Chain, SDLoc DL, SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg, DAG.getConstant(OffsetInBytes, PtrTy)); SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr, - DAG.getIntPtrConstant(ByVal.Address)); + DAG.getIntPtrConstant(VA.getLocMemOffset())); Chain = DAG.getMemcpy(Chain, DL, Dst, Src, DAG.getConstant(MemCpySize, PtrTy), Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false, MachinePointerInfo(), MachinePointerInfo()); @@ -3670,14 +3627,13 @@ passByValArg(SDValue Chain, SDLoc DL, } void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, - const MipsCC &CC, SDValue Chain, - SDLoc DL, SelectionDAG &DAG) const { - unsigned NumRegs = CC.numIntArgRegs(); - const MCPhysReg *ArgRegs = CC.intArgRegs(); - const CCState &CCInfo = CC.getCCInfo(); - unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); - unsigned RegSize = CC.regSize(); - MVT RegTy = MVT::getIntegerVT(RegSize * 8); + SDValue Chain, SDLoc DL, + SelectionDAG &DAG, + CCState &State) const { + const ArrayRef<MCPhysReg> ArgRegs = Subtarget.getABI().GetVarArgRegs(); + unsigned Idx = State.getFirstUnallocated(ArgRegs.data(), ArgRegs.size()); + unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); + MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); const TargetRegisterClass *RC = getRegClassFor(RegTy); MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -3686,28 +3642,81 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, // Offset of the first variable argument from stack pointer. int VaArgOffset; - if (NumRegs == Idx) - VaArgOffset = RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSize); - else - VaArgOffset = (int)CC.reservedArgArea() - (int)(RegSize * (NumRegs - Idx)); + if (ArgRegs.size() == Idx) + VaArgOffset = + RoundUpToAlignment(State.getNextStackOffset(), RegSizeInBytes); + else { + const MipsABIInfo &ABI = Subtarget.getABI(); + VaArgOffset = + (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) - + (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); + } // Record the frame index of the first variable argument // which is a value necessary to VASTART. - int FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); + int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); MipsFI->setVarArgsFrameIndex(FI); // Copy the integer registers that have not been used for argument passing // to the argument register save area. For O32, the save area is allocated // in the caller's stack frame, while for N32/64, it is allocated in the // callee's stack frame. - for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSize) { + for (unsigned I = Idx; I < ArgRegs.size(); + ++I, VaArgOffset += RegSizeInBytes) { unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); - FI = MFI->CreateFixedObject(RegSize, VaArgOffset, true); + FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy()); SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo(), false, false, 0); - cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue((Value*)nullptr); + cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue( + (Value *)nullptr); OutChains.push_back(Store); } } + +void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size, + unsigned Align) const { + MachineFunction &MF = State->getMachineFunction(); + const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering(); + + assert(Size && "Byval argument's size shouldn't be 0."); + + Align = std::min(Align, TFL->getStackAlignment()); + + unsigned FirstReg = 0; + unsigned NumRegs = 0; + + if (State->getCallingConv() != CallingConv::Fast) { + unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes(); + const ArrayRef<MCPhysReg> IntArgRegs = Subtarget.getABI().GetByValArgRegs(); + // FIXME: The O32 case actually describes no shadow registers. + const MCPhysReg *ShadowRegs = + Subtarget.isABI_O32() ? IntArgRegs.data() : Mips64DPRegs; + + // We used to check the size as well but we can't do that anymore since + // CCState::HandleByVal() rounds up the size after calling this function. + assert(!(Align % RegSizeInBytes) && + "Byval argument's alignment should be a multiple of" + "RegSizeInBytes."); + + FirstReg = State->getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size()); + + // If Align > RegSizeInBytes, the first arg register must be even. + // FIXME: This condition happens to do the right thing but it's not the + // right way to test it. We want to check that the stack frame offset + // of the register is aligned. + if ((Align > RegSizeInBytes) && (FirstReg % 2)) { + State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]); + ++FirstReg; + } + + // Mark the registers allocated. + Size = RoundUpToAlignment(Size, RegSizeInBytes); + for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size()); + Size -= RegSizeInBytes, ++I, ++NumRegs) + State->AllocateReg(IntArgRegs[I], ShadowRegs[I]); + } + + State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs); +} diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 4701bc4..60e53da 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MipsISELLOWERING_H -#define MipsISELLOWERING_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H #include "MCTargetDesc/MipsBaseInfo.h" #include "Mips.h" @@ -210,13 +210,16 @@ namespace llvm { //===--------------------------------------------------------------------===// class MipsFunctionInfo; class MipsSubtarget; + class MipsCCState; class MipsTargetLowering : public TargetLowering { bool isMicroMips; public: - explicit MipsTargetLowering(MipsTargetMachine &TM); + explicit MipsTargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); - static const MipsTargetLowering *create(MipsTargetMachine &TM); + static const MipsTargetLowering *create(const MipsTargetMachine &TM, + const MipsSubtarget &STI); /// createFastISel - This method returns a target specific FastISel object, /// or null if the target does not support "fast" ISel. @@ -257,6 +260,8 @@ namespace llvm { } }; + void HandleByVal(CCState *, unsigned &, unsigned) const override; + protected: SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; @@ -327,6 +332,21 @@ namespace llvm { DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); } + // This method creates the following nodes, which are necessary for + // computing a symbol's address using gp-relative addressing: + // + // (add $gp, %gp_rel(sym)) + template<class NodeTy> + SDValue getAddrGPRel(NodeTy *N, EVT Ty, SelectionDAG &DAG) const { + SDLoc DL(N); + assert(Ty == MVT::i32); + SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL); + return DAG.getNode(ISD::ADD, DL, Ty, + DAG.getRegister(Mips::GP, Ty), + DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), + GPRel)); + } + /// This function fills Ops, which is the list of operands that will later /// be used when a function call node is created. It also generates /// copyToReg nodes to set up argument registers. @@ -334,109 +354,15 @@ namespace llvm { getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const; - - /// ByValArgInfo - Byval argument information. - struct ByValArgInfo { - unsigned FirstIdx; // Index of the first register used. - unsigned NumRegs; // Number of registers used for this argument. - unsigned Address; // Offset of the stack area used to pass this argument. - - ByValArgInfo() : FirstIdx(0), NumRegs(0), Address(0) {} - }; - - /// MipsCC - This class provides methods used to analyze formal and call - /// arguments and inquire about calling convention information. - class MipsCC { - public: - enum SpecialCallingConvType { - Mips16RetHelperConv, NoSpecialCallingConv - }; - - MipsCC(CallingConv::ID CallConv, bool IsO32, bool IsFP64, CCState &Info, - SpecialCallingConvType SpecialCallingConv = NoSpecialCallingConv); - - - void analyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, - bool IsVarArg, bool IsSoftFloat, - const SDNode *CallNode, - std::vector<ArgListEntry> &FuncArgs); - void analyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, - bool IsSoftFloat, - Function::const_arg_iterator FuncArg); - - void analyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, - bool IsSoftFloat, const SDNode *CallNode, - const Type *RetTy) const; - - void analyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, - bool IsSoftFloat, const Type *RetTy) const; + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const; - const CCState &getCCInfo() const { return CCInfo; } - - /// hasByValArg - Returns true if function has byval arguments. - bool hasByValArg() const { return !ByValArgs.empty(); } - - /// regSize - Size (in number of bits) of integer registers. - unsigned regSize() const { return IsO32 ? 4 : 8; } - - /// numIntArgRegs - Number of integer registers available for calls. - unsigned numIntArgRegs() const; - - /// reservedArgArea - The size of the area the caller reserves for - /// register arguments. This is 16-byte if ABI is O32. - unsigned reservedArgArea() const; - - /// Return pointer to array of integer argument registers. - const MCPhysReg *intArgRegs() const; - - typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator; - byval_iterator byval_begin() const { return ByValArgs.begin(); } - byval_iterator byval_end() const { return ByValArgs.end(); } - - private: - void handleByValArg(unsigned ValNo, MVT ValVT, MVT LocVT, - CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags); - - /// useRegsForByval - Returns true if the calling convention allows the - /// use of registers to pass byval arguments. - bool useRegsForByval() const { return CallConv != CallingConv::Fast; } - - /// Return the function that analyzes fixed argument list functions. - llvm::CCAssignFn *fixedArgFn() const; - - /// Return the function that analyzes variable argument list functions. - llvm::CCAssignFn *varArgFn() const; - - const MCPhysReg *shadowRegs() const; - - void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize, - unsigned Align); - - /// Return the type of the register which is used to pass an argument or - /// return a value. This function returns f64 if the argument is an i64 - /// value which has been generated as a result of softening an f128 value. - /// Otherwise, it just returns VT. - MVT getRegVT(MVT VT, const Type *OrigTy, const SDNode *CallNode, - bool IsSoftFloat) const; - - template<typename Ty> - void analyzeReturn(const SmallVectorImpl<Ty> &RetVals, bool IsSoftFloat, - const SDNode *CallNode, const Type *RetTy) const; - - CCState &CCInfo; - CallingConv::ID CallConv; - bool IsO32, IsFP64; - SpecialCallingConvType SpecialCallingConv; - SmallVector<ByValArgInfo, 2> ByValArgs; - }; protected: SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; // Subtarget Info - const MipsSubtarget *Subtarget; + const MipsSubtarget &Subtarget; private: // Create a TargetGlobalAddress node. @@ -459,14 +385,12 @@ namespace llvm { SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG, unsigned Flag) const; - MipsCC::SpecialCallingConvType getSpecialCallingConv(SDValue Callee) const; // Lower Operand helpers SDValue LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, - const SmallVectorImpl<ISD::InputArg> &Ins, - SDLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals, - const SDNode *CallNode, const Type *RetTy) const; + const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, + SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, + TargetLowering::CallLoweringInfo &CLI) const; // Lower Operand specifics SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; @@ -480,6 +404,7 @@ namespace llvm { SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const; SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const; + SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; @@ -495,33 +420,34 @@ namespace llvm { /// isEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. virtual bool - isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, + isEligibleForTailCallOptimization(const CCState &CCInfo, unsigned NextStackOffset, - const MipsFunctionInfo& FI) const = 0; + const MipsFunctionInfo &FI) const = 0; /// copyByValArg - Copy argument registers which were used to pass a byval /// argument to the stack. Create a stack frame object for the byval /// argument. - void copyByValRegs(SDValue Chain, SDLoc DL, - std::vector<SDValue> &OutChains, SelectionDAG &DAG, - const ISD::ArgFlagsTy &Flags, + void copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, + SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals, - const Argument *FuncArg, - const MipsCC &CC, const ByValArgInfo &ByVal) const; + const Argument *FuncArg, unsigned FirstReg, + unsigned LastReg, const CCValAssign &VA, + MipsCCState &State) const; /// passByValArg - Pass a byval argument in registers or on stack. void passByValArg(SDValue Chain, SDLoc DL, - std::deque< std::pair<unsigned, SDValue> > &RegsToPass, + std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, - const MipsCC &CC, const ByValArgInfo &ByVal, - const ISD::ArgFlagsTy &Flags, bool isLittle) const; + unsigned FirstReg, unsigned LastReg, + const ISD::ArgFlagsTy &Flags, bool isLittle, + const CCValAssign &VA) const; /// writeVarArgRegs - Write variable function arguments passed in registers /// to the stack. Also create a stack frame object for the first variable /// argument. - void writeVarArgRegs(std::vector<SDValue> &OutChains, const MipsCC &CC, - SDValue Chain, SDLoc DL, SelectionDAG &DAG) const; + void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain, + SDLoc DL, SelectionDAG &DAG, CCState &State) const; SDValue LowerFormalArguments(SDValue Chain, @@ -560,7 +486,7 @@ namespace llvm { /// This function parses registers that appear in inline-asm constraints. /// It returns pair (0, 0) on failure. std::pair<unsigned, const TargetRegisterClass *> - parseRegForInlineAsmConstraint(const StringRef &C, MVT VT) const; + parseRegForInlineAsmConstraint(StringRef C, MVT VT) const; std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, @@ -611,8 +537,12 @@ namespace llvm { }; /// Create MipsTargetLowering objects. - const MipsTargetLowering *createMips16TargetLowering(MipsTargetMachine &TM); - const MipsTargetLowering *createMipsSETargetLowering(MipsTargetMachine &TM); + const MipsTargetLowering * + createMips16TargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); + const MipsTargetLowering * + createMipsSETargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); namespace Mips { FastISel *createFastISel(FunctionLoweringInfo &funcInfo, @@ -620,4 +550,4 @@ namespace llvm { } } -#endif // MipsISELLOWERING_H +#endif diff --git a/lib/Target/Mips/MipsInstrFPU.td b/lib/Target/Mips/MipsInstrFPU.td index 2260d53..2aa8328 100644 --- a/lib/Target/Mips/MipsInstrFPU.td +++ b/lib/Target/Mips/MipsInstrFPU.td @@ -211,14 +211,14 @@ class SWXC1_FT<string opstr, RegisterOperand DRC, } class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, - SDPatternOperator Op = null_frag> : + SDPatternOperator Op = null_frag, bit DelaySlot = 1> : InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), !strconcat(opstr, "\t$fcc, $offset"), [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, FrmFI, opstr> { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = 1; + let hasDelaySlot = DelaySlot; let Defs = [AT]; } @@ -362,11 +362,15 @@ def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM<0>; def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, MFC1_FM<4>; -def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>, - MFC1_FM<3>, ISA_MIPS32R2; -def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, +def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, + MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; +def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, + MFC1_FM<3>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { + let DecoderNamespace = "Mips64"; +} +def MTHC1_D32 : MMRel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[NotFP64bit]>; -def MTHC1_D64 : MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>, +def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>, MFC1_FM<7>, ISA_MIPS32R2, AdditionalRequires<[IsFP64bit]> { let DecoderNamespace = "Mips64"; } @@ -400,30 +404,6 @@ def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, ISA_MIPS2, FGR_32; -// Cop2 Memory Instructions -// FIXME: These aren't really FPU instructions and as such don't belong in this -// file -def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, - ISA_MIPS1_NOT_32R6_64R6; -def SWC2 : SW_FT<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, - ISA_MIPS1_NOT_32R6_64R6; -def LDC2 : LW_FT<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, - ISA_MIPS2_NOT_32R6_64R6; -def SDC2 : SW_FT<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, - ISA_MIPS2_NOT_32R6_64R6; - -// Cop3 Memory Instructions -// FIXME: These aren't really FPU instructions and as such don't belong in this -// file -let DecoderNamespace = "COP3_" in { - def LWC3 : LW_FT<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; - def SWC3 : SW_FT<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; - def LDC3 : LW_FT<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, - ISA_MIPS2; - def SDC3 : SW_FT<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, - ISA_MIPS2; -} - // Indexed loads and stores. // Base register + offset register addressing mode (indicated by "x" in the // instruction mnemonic) is disallowed under NaCl. @@ -526,8 +506,12 @@ def MIPS_BRANCH_T : PatLeaf<(i32 1)>; def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, IIBranch, MIPS_BRANCH_F>, BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6; +def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, IIBranch, MIPS_BRANCH_F, 0>, + BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6; def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, IIBranch, MIPS_BRANCH_T>, BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6; +def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, IIBranch, MIPS_BRANCH_T, 0>, + BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; //===----------------------------------------------------------------------===// // Floating Point Flag Conditions @@ -593,8 +577,12 @@ def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, //===----------------------------------------------------------------------===// def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, + ISA_MIPS2_NOT_32R6_64R6; def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, + ISA_MIPS2_NOT_32R6_64R6; //===----------------------------------------------------------------------===// // Floating Point Patterns diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td index 6a01ae5..5c91fbc 100644 --- a/lib/Target/Mips/MipsInstrFormats.td +++ b/lib/Target/Mips/MipsInstrFormats.td @@ -440,7 +440,7 @@ class EXT_FM<bits<6> funct> : StdArch { let Inst{5-0} = funct; } -class RDHWR_FM { +class RDHWR_FM : StdArch { bits<5> rt; bits<5> rd; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index d6da6c6..dcc0e24 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -30,15 +30,15 @@ using namespace llvm; // Pin the vtable to this file. void MipsInstrInfo::anchor() {} -MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr) - : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), - TM(tm), UncondBrOpc(UncondBr) {} +MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr) + : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), + Subtarget(STI), UncondBrOpc(UncondBr) {} -const MipsInstrInfo *MipsInstrInfo::create(MipsTargetMachine &TM) { - if (TM.getSubtargetImpl()->inMips16Mode()) - return llvm::createMips16InstrInfo(TM); +const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) { + if (STI.inMips16Mode()) + return llvm::createMips16InstrInfo(STI); - return llvm::createMipsSEInstrInfo(TM); + return llvm::createMipsSEInstrInfo(STI); } bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const { @@ -94,10 +94,10 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, return (BT == BT_None) || (BT == BT_Indirect); } -void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, - MachineBasicBlock *TBB, DebugLoc DL, - const SmallVectorImpl<MachineOperand>& Cond) - const { +void +MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + DebugLoc DL, + const SmallVectorImpl<MachineOperand> &Cond) const { unsigned Opc = Cond[0].getImm(); const MCInstrDesc &MCID = get(Opc); MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); @@ -113,11 +113,9 @@ void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MIB.addMBB(TBB); } -unsigned MipsInstrInfo:: -InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, - MachineBasicBlock *FBB, - const SmallVectorImpl<MachineOperand> &Cond, - DebugLoc DL) const { +unsigned MipsInstrInfo::InsertBranch( + MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, + const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const { // Shouldn't be a fall through. assert(TBB && "InsertBranch must not be told to insert a fallthrough"); @@ -145,9 +143,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, return 1; } -unsigned MipsInstrInfo:: -RemoveBranch(MachineBasicBlock &MBB) const -{ +unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); MachineBasicBlock::reverse_iterator FirstBr; unsigned removed; @@ -160,7 +156,7 @@ RemoveBranch(MachineBasicBlock &MBB) const // Up to 2 branches are removed. // Note that indirect branches are not removed. - for(removed = 0; I != REnd && removed < 2; ++I, ++removed) + for (removed = 0; I != REnd && removed < 2; ++I, ++removed) if (!getAnalyzableBrOpc(I->getOpcode())) break; @@ -171,20 +167,18 @@ RemoveBranch(MachineBasicBlock &MBB) const /// ReverseBranchCondition - Return the inverse opcode of the /// specified Branch instruction. -bool MipsInstrInfo:: -ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const -{ +bool MipsInstrInfo::ReverseBranchCondition( + SmallVectorImpl<MachineOperand> &Cond) const { assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm())); return false; } -MipsInstrInfo::BranchType MipsInstrInfo:: -AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, SmallVectorImpl<MachineOperand> &Cond, - bool AllowModify, - SmallVectorImpl<MachineInstr*> &BranchInstrs) const { +MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch( + MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, + SmallVectorImpl<MachineOperand> &Cond, bool AllowModify, + SmallVectorImpl<MachineInstr *> &BranchInstrs) const { MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index 742193f..db149d4 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -15,8 +15,8 @@ // size in bytes; MipsLongBranch only expects it to be the correct upper bound. //===----------------------------------------------------------------------===// -#ifndef MIPSINSTRUCTIONINFO_H -#define MIPSINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H #include "Mips.h" #include "MipsAnalyzeImmediate.h" @@ -33,7 +33,7 @@ namespace llvm { class MipsInstrInfo : public MipsGenInstrInfo { virtual void anchor(); protected: - MipsTargetMachine &TM; + const MipsSubtarget &Subtarget; unsigned UncondBrOpc; public: @@ -46,9 +46,9 @@ public: BT_Indirect // One indirct branch. }; - explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc); + explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc); - static const MipsInstrInfo *create(MipsTargetMachine &TM); + static const MipsInstrInfo *create(MipsSubtarget &STI); /// Branch Analysis bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, @@ -140,8 +140,8 @@ private: }; /// Create MipsInstrInfo objects. -const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM); -const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM); +const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI); +const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI); } diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 8e9472c..aebac34 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -331,7 +331,7 @@ include "MipsInstrFormats.td" def MipsJumpTargetAsmOperand : AsmOperandClass { let Name = "JumpTarget"; - let ParserMethod = "ParseJumpTarget"; + let ParserMethod = "parseJumpTarget"; let PredicateMethod = "isImm"; let RenderMethod = "addImmOperands"; } @@ -672,28 +672,62 @@ class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO, let DecoderMethod = "DecodeMem"; } +// COP2 Load/Store +class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, + SDPatternOperator OpNode= null_frag> : + InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { + let DecoderMethod = "DecodeFMem2"; + let mayLoad = 1; +} + +class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin, + SDPatternOperator OpNode= null_frag> : + InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { + let DecoderMethod = "DecodeFMem2"; + let mayStore = 1; +} + +// COP3 Load/Store +class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, + SDPatternOperator OpNode= null_frag> : + InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> { + let DecoderMethod = "DecodeFMem3"; + let mayLoad = 1; +} + +class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin, + SDPatternOperator OpNode= null_frag> : + InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> { + let DecoderMethod = "DecodeFMem3"; + let mayStore = 1; +} + // Conditional Branch class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op, - RegisterOperand RO> : + RegisterOperand RO, bit DelaySlot = 1> : InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset), !strconcat(opstr, "\t$rs, $rt, $offset"), [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch, FrmI, opstr> { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = 1; + let hasDelaySlot = DelaySlot; let Defs = [AT]; } class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op, - RegisterOperand RO> : + RegisterOperand RO, bit DelaySlot = 1> : InstSE<(outs), (ins RO:$rs, opnd:$offset), !strconcat(opstr, "\t$rs, $offset"), [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI, opstr> { let isBranch = 1; let isTerminator = 1; - let hasDelaySlot = 1; + let hasDelaySlot = DelaySlot; let Defs = [AT]; } @@ -765,9 +799,12 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), [], IIBranch, FrmR>; - class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> : + class BGEZAL_FT<string opstr, DAGOperand opnd, + RegisterOperand RO, bit DelaySlot = 1> : InstSE<(outs), (ins RO:$rs, opnd:$offset), - !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; + !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> { + let hasDelaySlot = DelaySlot; + } } @@ -933,7 +970,7 @@ class SubwordSwap<string opstr, RegisterOperand RO>: // Read Hardware class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> : InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], - II_RDHWR, FrmR>; + II_RDHWR, FrmR, "rdhwr">; // Ext and Ins class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd, @@ -1059,18 +1096,20 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst), //===----------------------------------------------------------------------===// /// Arithmetic Instructions (ALU Immediate) +let AdditionalPredicates = [NotInMicroMips] in { def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, - add>, - ADDI_FM<0x9>, IsAsCheapAsAMove; + add>, ADDI_FM<0x9>, IsAsCheapAsAMove; +} def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xa>; def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM<0xb>; +let AdditionalPredicates = [NotInMicroMips] in { def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, - and>, - ADDI_FM<0xc>; + and>, ADDI_FM<0xc>; +} def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, ADDI_FM<0xd>; @@ -1100,10 +1139,12 @@ def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; /// Shift Instructions +let AdditionalPredicates = [NotInMicroMips] in { def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl, immZExt5>, SRA_FM<0, 0>; def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl, immZExt5>, SRA_FM<2, 0>; +} def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra, immZExt5>, SRA_FM<3, 0>; def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>, @@ -1147,13 +1188,34 @@ def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>, ISA_MIPS1_NOT_32R6_64R6; } +// COP2 Memory Instructions +def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>, + ISA_MIPS1_NOT_32R6_64R6; +def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>, + ISA_MIPS1_NOT_32R6_64R6; +def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>, + ISA_MIPS2_NOT_32R6_64R6; +def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>, + ISA_MIPS2_NOT_32R6_64R6; + +// COP3 Memory Instructions +let DecoderNamespace = "COP3_" in { + def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>; + def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>; + def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>, + ISA_MIPS2; + def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>, + ISA_MIPS2; +} + def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32; -def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>; -def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>; -def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>; -def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>; -def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>; -def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>; + +def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2; +def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2; +def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2; +def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2; +def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2; +def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2; def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2_NOT_32R6_64R6; @@ -1171,7 +1233,7 @@ def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>; def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>; def TRAP : TrapBase<BREAK>; -def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; +def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6; def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32; def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32; @@ -1193,15 +1255,27 @@ def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>, AdditionalRequires<[RelocStatic]>, IsBranch; def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>; def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>; +def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>, + BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6; def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>; +def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>, + BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6; def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>, BGEZ_FM<1, 1>; +def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>, + BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6; def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>, BGEZ_FM<7, 0>; +def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>, + BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>, BGEZ_FM<6, 0>; +def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>, + BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6; def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>, BGEZ_FM<1, 0>; +def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>, + BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6; def B : UncondBranch<BEQ>; def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>; @@ -1214,8 +1288,12 @@ let AdditionalPredicates = [NotInMicroMips] in { def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6; def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>, ISA_MIPS1_NOT_32R6_64R6; +def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>, + BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6; def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, ISA_MIPS1_NOT_32R6_64R6; +def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>, + BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; def BAL_BR : BAL_BR_Pseudo<BGEZAL>; def TAILCALL : TailCall<J>; def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; @@ -1350,7 +1428,7 @@ def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV, def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6; -def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; +def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM; def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>; def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>; @@ -1408,19 +1486,21 @@ def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6; def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32; class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary, - FrmOther>; -def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>; -def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>; -def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>; -def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>; + FrmOther, asmstr>; +def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>; +def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>; +def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>; +def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>; -class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> : +class CacheOp<string instr_asm, Operand MemOpnd> : InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint), - !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>; + !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> { + let DecoderMethod = "DecodeCacheOp"; +} -def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>, +def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>, INSN_MIPS3_32_NOT_32R6_64R6; -def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>, +def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>, INSN_MIPS3_32_NOT_32R6_64R6; //===----------------------------------------------------------------------===// @@ -1435,8 +1515,14 @@ def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>, ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"addu $rs, $rt, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; +def : MipsInstAlias<"addu $rs, $imm", + (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>; def : MipsInstAlias<"add $rs, $rt, $imm", - (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; + (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>, + ISA_MIPS1_NOT_32R6_64R6; +def : MipsInstAlias<"add $rs, $imm", + (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>, + ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>; def : MipsInstAlias<"and $rs, $imm", @@ -1480,25 +1566,30 @@ def : MipsInstAlias<"syscall", (SYSCALL 0), 1>; def : MipsInstAlias<"break", (BREAK 0, 0), 1>; def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>; -def : MipsInstAlias<"ei", (EI ZERO), 1>; -def : MipsInstAlias<"di", (DI ZERO), 1>; - -def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), - 1>; -def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; -def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), - 1>; -def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; +def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2; +def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2; + +def : MipsInstAlias<"teq $rs, $rt", + (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; +def : MipsInstAlias<"tge $rs, $rt", + (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; +def : MipsInstAlias<"tgeu $rs, $rt", + (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; +def : MipsInstAlias<"tlt $rs, $rt", + (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; +def : MipsInstAlias<"tltu $rs, $rt", + (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; +def : MipsInstAlias<"tne $rs, $rt", + (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2; + def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sub, $rd, $rs, $imm", (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, - InvertedImOperand:$imm), 0>; + InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"sub $rs, $imm", (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm), - 0>; + 0>, ISA_MIPS1_NOT_32R6_64R6; def : MipsInstAlias<"subu, $rd, $rs, $imm", (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm), 0>; @@ -1563,6 +1654,12 @@ let AdditionalPredicates = [NotDSP] in { (ADDiu GPR32:$src, imm:$imm)>; } +// Support multiplication for pre-Mips32 targets that don't have +// the MUL instruction. +def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs), + (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>, + ISA_MIPS1_NOT_32R6_64R6; + // SYNC def : MipsPat<(MipsSync (i32 immz)), (SYNC 0)>, ISA_MIPS2; diff --git a/lib/Target/Mips/MipsJITInfo.cpp b/lib/Target/Mips/MipsJITInfo.cpp deleted file mode 100644 index 2072488..0000000 --- a/lib/Target/Mips/MipsJITInfo.cpp +++ /dev/null @@ -1,286 +0,0 @@ -//===-- MipsJITInfo.cpp - Implement the Mips JIT Interface ----------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the JIT interfaces for the Mips target. -// -//===----------------------------------------------------------------------===// - -#include "MipsJITInfo.h" -#include "MipsInstrInfo.h" -#include "MipsRelocations.h" -#include "MipsSubtarget.h" -#include "llvm/CodeGen/JITCodeEmitter.h" -#include "llvm/IR/Function.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/Memory.h" -#include "llvm/Support/raw_ostream.h" -#include <cstdlib> -using namespace llvm; - -#define DEBUG_TYPE "jit" - - -void MipsJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { - unsigned NewAddr = (intptr_t)New; - unsigned OldAddr = (intptr_t)Old; - const unsigned NopInstr = 0x0; - - // If the functions are in the same memory segment, insert PC-region branch. - if ((NewAddr & 0xF0000000) == ((OldAddr + 4) & 0xF0000000)) { - unsigned *OldInstruction = (unsigned *)Old; - *OldInstruction = 0x08000000; - unsigned JTargetAddr = NewAddr & 0x0FFFFFFC; - - JTargetAddr >>= 2; - *OldInstruction |= JTargetAddr; - - // Insert a NOP. - OldInstruction++; - *OldInstruction = NopInstr; - - sys::Memory::InvalidateInstructionCache(Old, 2 * 4); - } else { - // We need to clear hint bits from the instruction, in case it is 'jr ra'. - const unsigned HintMask = 0xFFFFF83F, ReturnSequence = 0x03e00008; - unsigned* CurrentInstr = (unsigned*)Old; - unsigned CurrInstrHintClear = (*CurrentInstr) & HintMask; - unsigned* NextInstr = CurrentInstr + 1; - unsigned NextInstrHintClear = (*NextInstr) & HintMask; - - // Do absolute jump if there are 2 or more instructions before return from - // the old function. - if ((CurrInstrHintClear != ReturnSequence) && - (NextInstrHintClear != ReturnSequence)) { - const unsigned LuiT0Instr = 0x3c080000, AddiuT0Instr = 0x25080000; - const unsigned JrT0Instr = 0x01000008; - // lui t0, high 16 bit of the NewAddr - (*(CurrentInstr++)) = LuiT0Instr | ((NewAddr & 0xffff0000) >> 16); - // addiu t0, t0, low 16 bit of the NewAddr - (*(CurrentInstr++)) = AddiuT0Instr | (NewAddr & 0x0000ffff); - // jr t0 - (*(CurrentInstr++)) = JrT0Instr; - (*CurrentInstr) = NopInstr; - - sys::Memory::InvalidateInstructionCache(Old, 4 * 4); - } else { - // Unsupported case - report_fatal_error("MipsJITInfo::replaceMachineCodeForFunction"); - } - } -} - -/// JITCompilerFunction - This contains the address of the JIT function used to -/// compile a function lazily. -static TargetJITInfo::JITCompilerFn JITCompilerFunction; - -// Get the ASMPREFIX for the current host. This is often '_'. -#ifndef __USER_LABEL_PREFIX__ -#define __USER_LABEL_PREFIX__ -#endif -#define GETASMPREFIX2(X) #X -#define GETASMPREFIX(X) GETASMPREFIX2(X) -#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__) - -// CompilationCallback stub - We can't use a C function with inline assembly in -// it, because the prolog/epilog inserted by GCC won't work for us. Instead, -// write our own wrapper, which does things our way, so we have complete control -// over register saving and restoring. This code saves registers, calls -// MipsCompilationCallbackC and restores registers. -extern "C" { -#if defined (__mips__) -void MipsCompilationCallback(); - - asm( - ".text\n" - ".align 2\n" - ".globl " ASMPREFIX "MipsCompilationCallback\n" - ASMPREFIX "MipsCompilationCallback:\n" - ".ent " ASMPREFIX "MipsCompilationCallback\n" - ".frame $sp, 32, $ra\n" - ".set noreorder\n" - ".cpload $t9\n" - - "addiu $sp, $sp, -64\n" - ".cprestore 16\n" - - // Save argument registers a0, a1, a2, a3, f12, f14 since they may contain - // stuff for the real target function right now. We have to act as if this - // whole compilation callback doesn't exist as far as the caller is - // concerned. We also need to save the ra register since it contains the - // original return address, and t8 register since it contains the address - // of the end of function stub. - "sw $a0, 20($sp)\n" - "sw $a1, 24($sp)\n" - "sw $a2, 28($sp)\n" - "sw $a3, 32($sp)\n" - "sw $ra, 36($sp)\n" - "sw $t8, 40($sp)\n" - "sdc1 $f12, 48($sp)\n" - "sdc1 $f14, 56($sp)\n" - - // t8 points at the end of function stub. Pass the beginning of the stub - // to the MipsCompilationCallbackC. - "addiu $a0, $t8, -16\n" - "jal " ASMPREFIX "MipsCompilationCallbackC\n" - "nop\n" - - // Restore registers. - "lw $a0, 20($sp)\n" - "lw $a1, 24($sp)\n" - "lw $a2, 28($sp)\n" - "lw $a3, 32($sp)\n" - "lw $ra, 36($sp)\n" - "lw $t8, 40($sp)\n" - "ldc1 $f12, 48($sp)\n" - "ldc1 $f14, 56($sp)\n" - "addiu $sp, $sp, 64\n" - - // Jump to the (newly modified) stub to invoke the real function. - "addiu $t8, $t8, -16\n" - "jr $t8\n" - "nop\n" - - ".set reorder\n" - ".end " ASMPREFIX "MipsCompilationCallback\n" - ); -#else // host != Mips - void MipsCompilationCallback() { - llvm_unreachable( - "Cannot call MipsCompilationCallback() on a non-Mips arch!"); - } -#endif -} - -/// MipsCompilationCallbackC - This is the target-specific function invoked -/// by the function stub when we did not know the real target of a call. -/// This function must locate the start of the stub or call site and pass -/// it into the JIT compiler function. -extern "C" void MipsCompilationCallbackC(intptr_t StubAddr) { - // Get the address of the compiled code for this function. - intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr); - - // Rewrite the function stub so that we don't end up here every time we - // execute the call. We're replacing the first four instructions of the - // stub with code that jumps to the compiled function: - // lui $t9, %hi(NewVal) - // addiu $t9, $t9, %lo(NewVal) - // jr $t9 - // nop - - int Hi = ((unsigned)NewVal & 0xffff0000) >> 16; - if ((NewVal & 0x8000) != 0) - Hi++; - int Lo = (int)(NewVal & 0xffff); - - *(intptr_t *)(StubAddr) = 0xf << 26 | 25 << 16 | Hi; - *(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo; - *(intptr_t *)(StubAddr + 8) = 25 << 21 | 8; - *(intptr_t *)(StubAddr + 12) = 0; - - sys::Memory::InvalidateInstructionCache((void*) StubAddr, 16); -} - -TargetJITInfo::LazyResolverFn MipsJITInfo::getLazyResolverFunction( - JITCompilerFn F) { - JITCompilerFunction = F; - return MipsCompilationCallback; -} - -TargetJITInfo::StubLayout MipsJITInfo::getStubLayout() { - // The stub contains 4 4-byte instructions, aligned at 4 bytes. See - // emitFunctionStub for details. - StubLayout Result = { 4*4, 4 }; - return Result; -} - -void *MipsJITInfo::emitFunctionStub(const Function *F, void *Fn, - JITCodeEmitter &JCE) { - JCE.emitAlignment(4); - void *Addr = (void*) (JCE.getCurrentPCValue()); - if (!sys::Memory::setRangeWritable(Addr, 16)) - llvm_unreachable("ERROR: Unable to mark stub writable."); - - intptr_t EmittedAddr; - if (Fn != (void*)(intptr_t)MipsCompilationCallback) - EmittedAddr = (intptr_t)Fn; - else - EmittedAddr = (intptr_t)MipsCompilationCallback; - - - int Hi = ((unsigned)EmittedAddr & 0xffff0000) >> 16; - if ((EmittedAddr & 0x8000) != 0) - Hi++; - int Lo = (int)(EmittedAddr & 0xffff); - - // lui $t9, %hi(EmittedAddr) - // addiu $t9, $t9, %lo(EmittedAddr) - // jalr $t8, $t9 - // nop - if (IsLittleEndian) { - JCE.emitWordLE(0xf << 26 | 25 << 16 | Hi); - JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo); - JCE.emitWordLE(25 << 21 | 24 << 11 | 9); - JCE.emitWordLE(0); - } else { - JCE.emitWordBE(0xf << 26 | 25 << 16 | Hi); - JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo); - JCE.emitWordBE(25 << 21 | 24 << 11 | 9); - JCE.emitWordBE(0); - } - - sys::Memory::InvalidateInstructionCache(Addr, 16); - if (!sys::Memory::setRangeExecutable(Addr, 16)) - llvm_unreachable("ERROR: Unable to mark stub executable."); - - return Addr; -} - -/// relocate - Before the JIT can run a block of code that has been emitted, -/// it must rewrite the code to contain the actual addresses of any -/// referenced global symbols. -void MipsJITInfo::relocate(void *Function, MachineRelocation *MR, - unsigned NumRelocs, unsigned char *GOTBase) { - for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { - - void *RelocPos = (char*) Function + MR->getMachineCodeOffset(); - intptr_t ResultPtr = (intptr_t) MR->getResultPointer(); - - switch ((Mips::RelocationType) MR->getRelocationType()) { - case Mips::reloc_mips_pc16: - ResultPtr = (((ResultPtr - (intptr_t) RelocPos) - 4) >> 2) & 0xffff; - *((unsigned*) RelocPos) |= (unsigned) ResultPtr; - break; - - case Mips::reloc_mips_26: - ResultPtr = (ResultPtr & 0x0fffffff) >> 2; - *((unsigned*) RelocPos) |= (unsigned) ResultPtr; - break; - - case Mips::reloc_mips_hi: - ResultPtr = ResultPtr >> 16; - if ((((intptr_t) (MR->getResultPointer()) & 0xffff) >> 15) == 1) { - ResultPtr += 1; - } - *((unsigned*) RelocPos) |= (unsigned) ResultPtr; - break; - - case Mips::reloc_mips_lo: { - // Addend is needed for unaligned load/store instructions, where offset - // for the second load/store in the expanded instruction sequence must - // be modified by +1 or +3. Otherwise, Addend is 0. - int Addend = *((unsigned*) RelocPos) & 0xffff; - ResultPtr = (ResultPtr + Addend) & 0xffff; - *((unsigned*) RelocPos) &= 0xffff0000; - *((unsigned*) RelocPos) |= (unsigned) ResultPtr; - break; - } - } - } -} diff --git a/lib/Target/Mips/MipsJITInfo.h b/lib/Target/Mips/MipsJITInfo.h deleted file mode 100644 index c9dfd83..0000000 --- a/lib/Target/Mips/MipsJITInfo.h +++ /dev/null @@ -1,71 +0,0 @@ -//===- MipsJITInfo.h - Mips Implementation of the JIT Interface -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the MipsJITInfo class. -// -//===----------------------------------------------------------------------===// - -#ifndef MIPSJITINFO_H -#define MIPSJITINFO_H - -#include "MipsMachineFunction.h" -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineJumpTableInfo.h" -#include "llvm/Target/TargetJITInfo.h" - -namespace llvm { -class MipsTargetMachine; - -class MipsJITInfo : public TargetJITInfo { - - bool IsPIC; - bool IsLittleEndian; - - public: - explicit MipsJITInfo() : - IsPIC(false), IsLittleEndian(true) {} - - /// replaceMachineCodeForFunction - Make it so that calling the function - /// whose machine code is at OLD turns into a call to NEW, perhaps by - /// overwriting OLD with a branch to NEW. This is used for self-modifying - /// code. - /// - void replaceMachineCodeForFunction(void *Old, void *New) override; - - // getStubLayout - Returns the size and alignment of the largest call stub - // on Mips. - StubLayout getStubLayout() override; - - /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a - /// small native function that simply calls the function at the specified - /// address. - void *emitFunctionStub(const Function *F, void *Fn, - JITCodeEmitter &JCE) override; - - /// getLazyResolverFunction - Expose the lazy resolver to the JIT. - LazyResolverFn getLazyResolverFunction(JITCompilerFn) override; - - /// relocate - Before the JIT can run a block of code that has been emitted, - /// it must rewrite the code to contain the actual addresses of any - /// referenced global symbols. - void relocate(void *Function, MachineRelocation *MR, - unsigned NumRelocs, unsigned char *GOTBase) override; - - /// Initialize - Initialize internal stage for the function being JITted. - void Initialize(const MachineFunction &MF, bool isPIC, - bool isLittleEndian) { - IsPIC = isPIC; - IsLittleEndian = isLittleEndian; - } - -}; -} - -#endif diff --git a/lib/Target/Mips/MipsLongBranch.cpp b/lib/Target/Mips/MipsLongBranch.cpp index c6838a3..e44d6ee 100644 --- a/lib/Target/Mips/MipsLongBranch.cpp +++ b/lib/Target/Mips/MipsLongBranch.cpp @@ -16,6 +16,7 @@ #include "Mips.h" #include "MCTargetDesc/MipsBaseInfo.h" #include "MCTargetDesc/MipsMCNaCl.h" +#include "MipsMachineFunction.h" #include "MipsTargetMachine.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/MachineFunctionPass.h" @@ -64,8 +65,8 @@ namespace { MipsLongBranch(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm), IsPIC(TM.getRelocationModel() == Reloc::PIC_), - ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()), - LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 10 : + ABI(TM.getSubtarget<MipsSubtarget>().getABI()), + LongBranchSeqSize(!IsPIC ? 2 : (ABI.IsN64() ? 10 : (!TM.getSubtarget<MipsSubtarget>().isTargetNaCl() ? 9 : 10))) {} const char *getPassName() const override { @@ -86,7 +87,7 @@ namespace { MachineFunction *MF; SmallVector<MBBInfo, 16> MBBInfos; bool IsPIC; - unsigned ABI; + MipsABIInfo ABI; unsigned LongBranchSeqSize; }; @@ -170,7 +171,7 @@ void MipsLongBranch::initMBBInfo() { MBBInfos.resize(MF->size()); const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo()); for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) { MachineBasicBlock *MBB = MF->getBlockNumbered(I); @@ -217,7 +218,7 @@ int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) { void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL, MachineBasicBlock *MBBOpnd) { const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo()); unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode()); const MCInstrDesc &NewDesc = TII->get(NewOpc); @@ -254,7 +255,7 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) { MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB); const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo()); MF->insert(FallThroughMBB, LongBrMBB); MBB->removeSuccessor(TgtMBB); @@ -273,7 +274,7 @@ void MipsLongBranch::expandToLongBranch(MBBInfo &I) { const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; - if (ABI != MipsSubtarget::N64) { + if (!ABI.IsN64()) { // $longbr: // addiu $sp, $sp, -8 // sw $ra, 0($sp) @@ -447,9 +448,10 @@ static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) { bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { const MipsInstrInfo *TII = - static_cast<const MipsInstrInfo*>(TM.getInstrInfo()); + static_cast<const MipsInstrInfo *>(TM.getSubtargetImpl()->getInstrInfo()); - if (TM.getSubtarget<MipsSubtarget>().inMips16Mode()) + const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); + if (STI.inMips16Mode() || !STI.enableLongBranchPass()) return false; if ((TM.getRelocationModel() == Reloc::PIC_) && TM.getSubtarget<MipsSubtarget>().isABI_O32() && diff --git a/lib/Target/Mips/MipsMCInstLower.h b/lib/Target/Mips/MipsMCInstLower.h index 269190f..1ce27e4 100644 --- a/lib/Target/Mips/MipsMCInstLower.h +++ b/lib/Target/Mips/MipsMCInstLower.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSMCINSTLOWER_H -#define MIPSMCINSTLOWER_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H +#define LLVM_LIB_TARGET_MIPS_MIPSMCINSTLOWER_H #include "MCTargetDesc/MipsMCExpr.h" #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineOperand.h" diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index 285bb14..68230e6 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -69,7 +69,7 @@ def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", // as the encoded value should be subtracted by one. def uimm2LSAAsmOperand : AsmOperandClass { let Name = "LSAImm"; - let ParserMethod = "ParseLSAImm"; + let ParserMethod = "parseLSAImm"; let RenderMethod = "addImmOperands"; } diff --git a/lib/Target/Mips/MipsMachineFunction.cpp b/lib/Target/Mips/MipsMachineFunction.cpp index e30302e..a89718a 100644 --- a/lib/Target/Mips/MipsMachineFunction.cpp +++ b/lib/Target/Mips/MipsMachineFunction.cpp @@ -24,7 +24,7 @@ FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true), cl::desc("Always use $gp as the global base register.")); // class MipsCallEntry. -MipsCallEntry::MipsCallEntry(const StringRef &N) { +MipsCallEntry::MipsCallEntry(StringRef N) { #ifndef NDEBUG Name = N; Val = nullptr; @@ -119,7 +119,7 @@ bool MipsFunctionInfo::isEhDataRegFI(int FI) const { || FI == EhDataRegFI[2] || FI == EhDataRegFI[3]); } -MachinePointerInfo MipsFunctionInfo::callPtrInfo(const StringRef &Name) { +MachinePointerInfo MipsFunctionInfo::callPtrInfo(StringRef Name) { const MipsCallEntry *&E = ExternalCallEntries[Name]; if (!E) @@ -137,4 +137,12 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *Val) { return MachinePointerInfo(E); } +int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { + if (MoveF64ViaSpillFI == -1) { + MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject( + RC->getSize(), RC->getAlignment(), false); + } + return MoveF64ViaSpillFI; +} + void MipsFunctionInfo::anchor() { } diff --git a/lib/Target/Mips/MipsMachineFunction.h b/lib/Target/Mips/MipsMachineFunction.h index 8c16f82..217f307 100644 --- a/lib/Target/Mips/MipsMachineFunction.h +++ b/lib/Target/Mips/MipsMachineFunction.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPS_MACHINE_FUNCTION_INFO_H -#define MIPS_MACHINE_FUNCTION_INFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSMACHINEFUNCTION_H +#define LLVM_LIB_TARGET_MIPS_MIPSMACHINEFUNCTION_H #include "Mips16HardFloatInfo.h" #include "llvm/ADT/StringMap.h" @@ -34,7 +34,7 @@ namespace llvm { /// resolved by lazy-binding. class MipsCallEntry : public PseudoSourceValue { public: - explicit MipsCallEntry(const StringRef &N); + explicit MipsCallEntry(StringRef N); explicit MipsCallEntry(const GlobalValue *V); bool isConstant(const MachineFrameInfo *) const override; bool isAliased(const MachineFrameInfo *) const override; @@ -54,7 +54,8 @@ class MipsFunctionInfo : public MachineFunctionInfo { public: MipsFunctionInfo(MachineFunction &MF) : MF(MF), SRetReturnReg(0), GlobalBaseReg(0), Mips16SPAliasReg(0), - VarArgsFrameIndex(0), CallsEhReturn(false), SaveS2(false) {} + VarArgsFrameIndex(0), CallsEhReturn(false), SaveS2(false), + MoveF64ViaSpillFI(-1) {} ~MipsFunctionInfo(); @@ -87,7 +88,7 @@ public: /// \brief Create a MachinePointerInfo that has a MipsCallEntr object /// representing a GOT entry for an external function. - MachinePointerInfo callPtrInfo(const StringRef &Name); + MachinePointerInfo callPtrInfo(StringRef Name); /// \brief Create a MachinePointerInfo that has a MipsCallEntr object /// representing a GOT entry for a global function. @@ -96,6 +97,8 @@ public: void setSaveS2() { SaveS2 = true; } bool hasSaveS2() const { return SaveS2; } + int getMoveF64ViaSpillFI(const TargetRegisterClass *RC); + std::map<const char *, const llvm::Mips16HardFloatInfo::FuncSignature *> StubsNeeded; @@ -136,6 +139,10 @@ private: // saveS2 bool SaveS2; + /// FrameIndex for expanding BuildPairF64 nodes to spill and reload when the + /// O32 FPXX ABI is enabled. -1 is used to denote invalid index. + int MoveF64ViaSpillFI; + /// MipsCallEntry maps. StringMap<const MipsCallEntry *> ExternalCallEntries; ValueMap<const GlobalValue *, const MipsCallEntry *> GlobalCallEntries; @@ -143,4 +150,4 @@ private: } // end of namespace llvm -#endif // MIPS_MACHINE_FUNCTION_INFO_H +#endif diff --git a/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp b/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp index 03c76ea..b011e8f 100644 --- a/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp @@ -20,7 +20,7 @@ namespace llvm { bool MipsModuleDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { DEBUG(errs() << "In MipsModuleDAGToDAGISel::runMachineFunction\n"); - const_cast<MipsSubtarget&>(Subtarget).resetSubtarget(&MF); + TM.resetSubtarget(&MF); return false; } diff --git a/lib/Target/Mips/MipsModuleISelDAGToDAG.h b/lib/Target/Mips/MipsModuleISelDAGToDAG.h index a96862a..85bae47 100644 --- a/lib/Target/Mips/MipsModuleISelDAGToDAG.h +++ b/lib/Target/Mips/MipsModuleISelDAGToDAG.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSMODULEISELDAGTODAG_H -#define MIPSMODULEISELDAGTODAG_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSMODULEISELDAGTODAG_H +#define LLVM_LIB_TARGET_MIPS_MIPSMODULEISELDAGTODAG_H #include "Mips.h" #include "MipsSubtarget.h" @@ -37,8 +37,7 @@ public: static char ID; explicit MipsModuleDAGToDAGISel(MipsTargetMachine &TM_) - : MachineFunctionPass(ID), - TM(TM_), Subtarget(TM.getSubtarget<MipsSubtarget>()) {} + : MachineFunctionPass(ID), TM(TM_) {} // Pass Name const char *getPassName() const override { @@ -48,10 +47,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override; protected: - /// Keep a pointer to the MipsSubtarget around so that we can make the right - /// decision when generating code for different targets. - const TargetMachine &TM; - const MipsSubtarget &Subtarget; + MipsTargetMachine &TM; }; /// createMipsISelDag - This pass converts a legalized DAG into a diff --git a/lib/Target/Mips/MipsOptimizePICCall.cpp b/lib/Target/Mips/MipsOptimizePICCall.cpp index c234049..22c524e 100644 --- a/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -130,7 +130,7 @@ static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) { static void setCallTargetReg(MachineBasicBlock *MBB, MachineBasicBlock::iterator I) { MachineFunction &MF = *MBB->getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned SrcReg = I->getOperand(0).getReg(); unsigned DstReg = getRegTy(SrcReg, MF) == MVT::i32 ? Mips::T9 : Mips::T9_64; BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg) diff --git a/lib/Target/Mips/MipsOptionRecord.h b/lib/Target/Mips/MipsOptionRecord.h new file mode 100644 index 0000000..f82544a --- /dev/null +++ b/lib/Target/Mips/MipsOptionRecord.h @@ -0,0 +1,78 @@ +//===-- MipsOptionRecord.h - Abstraction for storing information ----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// MipsOptionRecord - Abstraction for storing arbitrary information in +// ELF files. Arbitrary information (e.g. register usage) can be stored in Mips +// specific ELF sections like .Mips.options. Specific records should subclass +// MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which +// basically just dumps the information into an ELF section. More information +// about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object +// specification. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H +#define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H + +#include "MCTargetDesc/MipsMCTargetDesc.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCRegisterInfo.h" + +namespace llvm { +class MipsELFStreamer; +class MCSubtargetInfo; + +class MipsOptionRecord { +public: + virtual ~MipsOptionRecord(){}; + virtual void EmitMipsOptionRecord() = 0; +}; + +class MipsRegInfoRecord : public MipsOptionRecord { +public: + MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context, + const MCSubtargetInfo &STI) + : Streamer(S), Context(Context), STI(STI) { + ri_gprmask = 0; + ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0; + ri_gp_value = 0; + + const MCRegisterInfo *TRI = Context.getRegisterInfo(); + GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID)); + GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID)); + FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID)); + FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID)); + AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID)); + MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID)); + COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID)); + COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID)); + } + ~MipsRegInfoRecord() {} + + void EmitMipsOptionRecord() override; + void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo); + +private: + MipsELFStreamer *Streamer; + MCContext &Context; + const MCSubtargetInfo &STI; + const MCRegisterClass *GPR32RegClass; + const MCRegisterClass *GPR64RegClass; + const MCRegisterClass *FGR32RegClass; + const MCRegisterClass *FGR64RegClass; + const MCRegisterClass *AFGR64RegClass; + const MCRegisterClass *MSA128BRegClass; + const MCRegisterClass *COP2RegClass; + const MCRegisterClass *COP3RegClass; + uint32_t ri_gprmask; + uint32_t ri_cprmask[4]; + int64_t ri_gp_value; +}; +} // namespace llvm +#endif diff --git a/lib/Target/Mips/MipsOs16.h b/lib/Target/Mips/MipsOs16.h index 55e5a81..77183ec 100644 --- a/lib/Target/Mips/MipsOs16.h +++ b/lib/Target/Mips/MipsOs16.h @@ -11,16 +11,14 @@ // //===----------------------------------------------------------------------===// +#ifndef LLVM_LIB_TARGET_MIPS_MIPSOS16_H +#define LLVM_LIB_TARGET_MIPS_MIPSOS16_H + #include "MCTargetDesc/MipsMCTargetDesc.h" #include "MipsTargetMachine.h" #include "llvm/Pass.h" #include "llvm/Target/TargetMachine.h" - - -#ifndef MIPSOS16_H -#define MIPSOS16_H - using namespace llvm; namespace llvm { diff --git a/lib/Target/Mips/MipsRegisterInfo.cpp b/lib/Target/Mips/MipsRegisterInfo.cpp index 084449b..20ef3f3 100644 --- a/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/lib/Target/Mips/MipsRegisterInfo.cpp @@ -62,7 +62,7 @@ MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, case Mips::GPR32RegClassID: case Mips::GPR64RegClassID: case Mips::DSPRRegClassID: { - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return 28 - TFI->hasFP(MF); } case Mips::FGR32RegClassID: @@ -149,6 +149,12 @@ getReservedRegs(const MachineFunction &MF) const { for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) Reserved.set(ReservedGPR64[I]); + // For mno-abicalls, GP is a program invariant! + if (!Subtarget.isABICalls()) { + Reserved.set(Mips::GP); + Reserved.set(Mips::GP_64); + } + if (Subtarget.isFP64bit()) { // Reserve all registers in AFGR64. for (RegIter Reg = Mips::AFGR64RegClass.begin(), @@ -161,7 +167,7 @@ getReservedRegs(const MachineFunction &MF) const { Reserved.set(*Reg); } // Reserve FP if this function should have a dedicated frame pointer register. - if (MF.getTarget().getFrameLowering()->hasFP(MF)) { + if (MF.getSubtarget().getFrameLowering()->hasFP(MF)) { if (Subtarget.inMips16Mode()) Reserved.set(Mips::S0); else { @@ -250,7 +256,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned MipsRegisterInfo:: getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); bool IsN64 = Subtarget.isABI_N64(); if (Subtarget.inMips16Mode()) diff --git a/lib/Target/Mips/MipsRegisterInfo.h b/lib/Target/Mips/MipsRegisterInfo.h index b34496f..9ec4a38 100644 --- a/lib/Target/Mips/MipsRegisterInfo.h +++ b/lib/Target/Mips/MipsRegisterInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSREGISTERINFO_H -#define MIPSREGISTERINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H #include "Mips.h" #include "llvm/Target/TargetRegisterInfo.h" diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 6323da3..42fe76b 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -212,8 +212,13 @@ let Namespace = "Mips" in { // PC register def PC : Register<"pc">; - // Hardware register $29 - foreach I = 0-31 in + // Hardware registers + def HWR0 : MipsReg<0, "hwr_cpunum">; + def HWR1 : MipsReg<1, "hwr_synci_step">; + def HWR2 : MipsReg<2, "hwr_cc">; + def HWR3 : MipsReg<3, "hwr_ccres">; + + foreach I = 4-31 in def HWR#I : MipsReg<#I, ""#I>; // Accum registers @@ -283,6 +288,12 @@ class GPR32Class<list<ValueType> regTypes> : def GPR32 : GPR32Class<[i32]>; def DSPR : GPR32Class<[v4i8, v2i16]>; +def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add + // Return Values and Arguments + V0, V1, A0, A1, A2, A3, + // Callee save + S0, S1)>; + def GPR64 : RegisterClass<"Mips", [i64], 64, (add // Reserved ZERO_64, AT_64, @@ -341,9 +352,12 @@ def AFGR64 : RegisterClass<"Mips", [f64], 64, (add def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; // Used to reserve odd registers when given -mattr=+nooddspreg +// FIXME: Remove double precision registers from this set. def OddSP : RegisterClass<"Mips", [f32], 32, (add (decimate (sequence "F%u", 1, 31), 2), - (decimate (sequence "F_HI%u", 1, 31), 2))>, + (decimate (sequence "F_HI%u", 1, 31), 2), + (decimate (sequence "D%u", 1, 15), 2), + (decimate (sequence "D%u_64", 1, 31), 2))>, Unallocatable; // FP control registers. @@ -414,7 +428,7 @@ def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>, // Register Operands. class MipsAsmRegOperand : AsmOperandClass { - let ParserMethod = "ParseAnyRegister"; + let ParserMethod = "parseAnyRegister"; } def GPR64AsmOperand : MipsAsmRegOperand { @@ -427,6 +441,11 @@ def GPR32AsmOperand : MipsAsmRegOperand { let PredicateMethod = "isGPRAsmReg"; } +def GPRMM16AsmOperand : MipsAsmRegOperand { + let Name = "GPRMM16AsmReg"; + let PredicateMethod = "isMM16AsmReg"; +} + def ACC64DSPAsmOperand : MipsAsmRegOperand { let Name = "ACC64DSPAsmReg"; let PredicateMethod = "isACCAsmReg"; @@ -482,6 +501,10 @@ def GPR32Opnd : RegisterOperand<GPR32> { let ParserMatchClass = GPR32AsmOperand; } +def GPRMM16Opnd : RegisterOperand<GPRMM16> { + let ParserMatchClass = GPRMM16AsmOperand; +} + def GPR64Opnd : RegisterOperand<GPR64> { let ParserMatchClass = GPR64AsmOperand; } @@ -575,4 +598,3 @@ def MSA128DOpnd : RegisterOperand<MSA128D> { def MSA128CROpnd : RegisterOperand<MSACtrl> { let ParserMatchClass = MSACtrlAsmOperand; } - diff --git a/lib/Target/Mips/MipsRelocations.h b/lib/Target/Mips/MipsRelocations.h deleted file mode 100644 index 0787ed3..0000000 --- a/lib/Target/Mips/MipsRelocations.h +++ /dev/null @@ -1,41 +0,0 @@ -//===-- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the Mips target-specific relocation types -// (for relocation-model=static). -// -//===----------------------------------------------------------------------===// - -#ifndef MIPSRELOCATIONS_H_ -#define MIPSRELOCATIONS_H_ - -#include "llvm/CodeGen/MachineRelocation.h" - -namespace llvm { - namespace Mips{ - enum RelocationType { - // reloc_mips_pc16 - pc relative relocation for branches. The lower 18 - // bits of the difference between the branch target and the branch - // instruction, shifted right by 2. - reloc_mips_pc16 = 1, - - // reloc_mips_hi - upper 16 bits of the address (modified by +1 if the - // lower 16 bits of the address is negative). - reloc_mips_hi = 2, - - // reloc_mips_lo - lower 16 bits of the address. - reloc_mips_lo = 3, - - // reloc_mips_26 - lower 28 bits of the address, shifted right by 2. - reloc_mips_26 = 4 - }; - } -} - -#endif /* MIPSRELOCATIONS_H_ */ diff --git a/lib/Target/Mips/MipsSEFrameLowering.cpp b/lib/Target/Mips/MipsSEFrameLowering.cpp index 6573070..97d9edf 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -64,6 +64,10 @@ private: bool expandCopy(MachineBasicBlock &MBB, Iter I); bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc, unsigned MFLoOpc); + bool expandBuildPairF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, bool FP64) const; + bool expandExtractElementF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, bool FP64) const; MachineFunction &MF; MachineRegisterInfo &MRI; @@ -108,6 +112,22 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) { case Mips::STORE_ACC128: expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8); break; + case Mips::BuildPairF64: + if (expandBuildPairF64(MBB, I, false)) + MBB.erase(I); + return false; + case Mips::BuildPairF64_64: + if (expandBuildPairF64(MBB, I, true)) + MBB.erase(I); + return false; + case Mips::ExtractElementF64: + if (expandExtractElementF64(MBB, I, false)) + MBB.erase(I); + return false; + case Mips::ExtractElementF64_64: + if (expandExtractElementF64(MBB, I, true)) + MBB.erase(I); + return false; case TargetOpcode::COPY: if (!expandCopy(MBB, I)) return false; @@ -127,9 +147,9 @@ void ExpandPseudo::expandLoadCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -147,9 +167,9 @@ void ExpandPseudo::expandStoreCCond(MachineBasicBlock &MBB, Iter I) { assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(4); unsigned VR = MRI.createVirtualRegister(RC); @@ -170,9 +190,9 @@ void ExpandPseudo::expandLoadACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -200,9 +220,9 @@ void ExpandPseudo::expandStoreACC(MachineBasicBlock &MBB, Iter I, assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); unsigned VR0 = MRI.createVirtualRegister(RC); @@ -235,9 +255,9 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, // copy dst_hi, $vr1 const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg(); unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2; @@ -258,6 +278,123 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I, return true; } +/// This method expands the same instruction that MipsSEInstrInfo:: +/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not +/// available and the case where the ABI is FP64A. It is implemented here +/// because frame indexes are eliminated before MipsSEInstrInfo:: +/// expandBuildPairF64 is called. +bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + bool FP64) const { + // For fpxx and when mthc1 is not available, use: + // spill + reload via ldc1 + // + // The case where dmtc1 is available doesn't need to be handled here + // because it never creates a BuildPairF64 node. + // + // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence + // for odd-numbered double precision values (because the lower 32-bits is + // transferred with mtc1 which is redirected to the upper half of the even + // register). Unfortunately, we have to make this decision before register + // allocation so for now we use a spill/reload sequence for all + // double-precision values in regardless of being an odd/even register. + + const TargetMachine &TM = MF.getTarget(); + const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); + if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || + (FP64 && !Subtarget.useOddSPReg())) { + const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( + TM.getSubtargetImpl()->getInstrInfo()); + const MipsRegisterInfo &TRI = *static_cast<const MipsRegisterInfo *>( + TM.getSubtargetImpl()->getRegisterInfo()); + + unsigned DstReg = I->getOperand(0).getReg(); + unsigned LoReg = I->getOperand(1).getReg(); + unsigned HiReg = I->getOperand(2).getReg(); + + // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are + // the cases where mthc1 is not available). 64-bit architectures and + // MIPS32r2 or later can use FGR64 though. + assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || + !Subtarget.isFP64bit()); + + const TargetRegisterClass *RC = &Mips::GPR32RegClass; + const TargetRegisterClass *RC2 = + FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; + + // We re-use the same spill slot each time so that the stack frame doesn't + // grow too much in functions with a large number of moves. + int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC2); + if (!Subtarget.isLittle()) + std::swap(LoReg, HiReg); + TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI, + 0); + TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI, + 4); + TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, 0); + return true; + } + + return false; +} + +/// This method expands the same instruction that MipsSEInstrInfo:: +/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not +/// available and the case where the ABI is FP64A. It is implemented here +/// because frame indexes are eliminated before MipsSEInstrInfo:: +/// expandExtractElementF64 is called. +bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I, + bool FP64) const { + // For fpxx and when mfhc1 is not available, use: + // spill + reload via ldc1 + // + // The case where dmfc1 is available doesn't need to be handled here + // because it never creates a ExtractElementF64 node. + // + // The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence + // for odd-numbered double precision values (because the lower 32-bits is + // transferred with mfc1 which is redirected to the upper half of the even + // register). Unfortunately, we have to make this decision before register + // allocation so for now we use a spill/reload sequence for all + // double-precision values in regardless of being an odd/even register. + + const TargetMachine &TM = MF.getTarget(); + const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); + if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) || + (FP64 && !Subtarget.useOddSPReg())) { + const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( + TM.getSubtargetImpl()->getInstrInfo()); + const MipsRegisterInfo &TRI = *static_cast<const MipsRegisterInfo *>( + TM.getSubtargetImpl()->getRegisterInfo()); + + unsigned DstReg = I->getOperand(0).getReg(); + unsigned SrcReg = I->getOperand(1).getReg(); + unsigned N = I->getOperand(2).getImm(); + int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N)); + + // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are + // the cases where mfhc1 is not available). 64-bit architectures and + // MIPS32r2 or later can use FGR64 though. + assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() || + !Subtarget.isFP64bit()); + + const TargetRegisterClass *RC = + FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; + const TargetRegisterClass *RC2 = &Mips::GPR32RegClass; + + // We re-use the same spill slot each time so that the stack frame doesn't + // grow too much in functions with a large number of moves. + int FI = MF.getInfo<MipsFunctionInfo>()->getMoveF64ViaSpillFI(RC); + TII.storeRegToStack(MBB, I, SrcReg, I->getOperand(1).isKill(), FI, RC, &TRI, + 0); + TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, Offset); + return true; + } + + return false; +} + MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) : MipsFrameLowering(STI, STI.stackAlignment()) {} @@ -278,9 +415,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -343,6 +480,22 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF) const { MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); + } else if (Mips::FGR64RegClass.contains(Reg)) { + unsigned Reg0 = MRI->getDwarfRegNum(Reg, true); + unsigned Reg1 = MRI->getDwarfRegNum(Reg, true) + 1; + + if (!STI.isLittle()) + std::swap(Reg0, Reg1); + + unsigned CFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); + + CFIIndex = MMI.addFrameInst( + MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); } else { // Reg is either in GPR32 or FGR32. unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( @@ -397,9 +550,9 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); - const MipsRegisterInfo &RegInfo = - *static_cast<const MipsRegisterInfo*>(MF.getTarget().getRegisterInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); + const MipsRegisterInfo &RegInfo = *static_cast<const MipsRegisterInfo *>( + MF.getSubtarget().getRegisterInfo()); DebugLoc dl = MBBI->getDebugLoc(); unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; @@ -452,7 +605,7 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, const TargetRegisterInfo *TRI) const { MachineFunction *MF = MBB.getParent(); MachineBasicBlock *EntryBlock = MF->begin(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is @@ -493,7 +646,7 @@ void MipsSEFrameLowering:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { const MipsSEInstrInfo &TII = - *static_cast<const MipsSEInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const MipsSEInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (!hasReservedCallFrame(MF)) { int64_t Amount = I->getOperand(0).getImm(); diff --git a/lib/Target/Mips/MipsSEFrameLowering.h b/lib/Target/Mips/MipsSEFrameLowering.h index e832848..0eca1df 100644 --- a/lib/Target/Mips/MipsSEFrameLowering.h +++ b/lib/Target/Mips/MipsSEFrameLowering.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSE_FRAMEINFO_H -#define MIPSSE_FRAMEINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPSSEFRAMELOWERING_H #include "MipsFrameLowering.h" diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 6f35947..f759905 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -37,6 +37,7 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &TM.getSubtarget<MipsSubtarget>(); if (Subtarget->inMips16Mode()) return false; return MipsDAGToDAGISel::runOnMachineFunction(MF); @@ -129,7 +130,7 @@ void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator I = MBB.begin(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); const TargetRegisterClass *RC; diff --git a/lib/Target/Mips/MipsSEISelDAGToDAG.h b/lib/Target/Mips/MipsSEISelDAGToDAG.h index 57328d2..2e11fa7 100644 --- a/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSEISELDAGTODAG_H -#define MIPSSEISELDAGTODAG_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H +#define LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H #include "MipsISelDAGToDAG.h" diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index be4ca86..4a0ce09 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -11,6 +11,7 @@ // //===----------------------------------------------------------------------===// #include "MipsSEISelLowering.h" +#include "MipsMachineFunction.h" #include "MipsRegisterInfo.h" #include "MipsTargetMachine.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -34,15 +35,16 @@ static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), "stores to their single precision " "counterparts")); -MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) - : MipsTargetLowering(TM) { +MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI) + : MipsTargetLowering(TM, STI) { // Set up the register classes addRegisterClass(MVT::i32, &Mips::GPR32RegClass); - if (Subtarget->isGP64bit()) + if (Subtarget.isGP64bit()) addRegisterClass(MVT::i64, &Mips::GPR64RegClass); - if (Subtarget->hasDSP() || Subtarget->hasMSA()) { + if (Subtarget.hasDSP() || Subtarget.hasMSA()) { // Expand all truncating stores and extending loads. unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; @@ -58,7 +60,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) } } - if (Subtarget->hasDSP()) { + if (Subtarget.hasDSP()) { MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { @@ -82,10 +84,10 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setTargetDAGCombine(ISD::VSELECT); } - if (Subtarget->hasDSPR2()) + if (Subtarget.hasDSPR2()) setOperationAction(ISD::MUL, MVT::v2i16, Legal); - if (Subtarget->hasMSA()) { + if (Subtarget.hasMSA()) { addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); @@ -101,12 +103,12 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setTargetDAGCombine(ISD::XOR); } - if (!Subtarget->mipsSEUsesSoftFloat()) { + if (!Subtarget.abiUsesSoftFloat()) { addRegisterClass(MVT::f32, &Mips::FGR32RegClass); // When dealing with single precision only, use libcalls - if (!Subtarget->isSingleFloat()) { - if (Subtarget->isFP64bit()) + if (!Subtarget.isSingleFloat()) { + if (Subtarget.isFP64bit()) addRegisterClass(MVT::f64, &Mips::FGR64RegClass); else addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); @@ -118,14 +120,16 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::MULHS, MVT::i32, Custom); setOperationAction(ISD::MULHU, MVT::i32, Custom); - if (Subtarget->hasCnMips()) + if (Subtarget.hasCnMips()) setOperationAction(ISD::MUL, MVT::i64, Legal); - else if (Subtarget->isGP64bit()) + else if (Subtarget.isGP64bit()) setOperationAction(ISD::MUL, MVT::i64, Custom); - if (Subtarget->isGP64bit()) { + if (Subtarget.isGP64bit()) { setOperationAction(ISD::MULHS, MVT::i64, Custom); setOperationAction(ISD::MULHU, MVT::i64, Custom); + setOperationAction(ISD::SDIVREM, MVT::i64, Custom); + setOperationAction(ISD::UDIVREM, MVT::i64, Custom); } setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); @@ -133,8 +137,6 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::SDIVREM, MVT::i32, Custom); setOperationAction(ISD::UDIVREM, MVT::i32, Custom); - setOperationAction(ISD::SDIVREM, MVT::i64, Custom); - setOperationAction(ISD::UDIVREM, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); setOperationAction(ISD::LOAD, MVT::i32, Custom); setOperationAction(ISD::STORE, MVT::i32, Custom); @@ -152,7 +154,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::STORE, MVT::f64, Custom); } - if (Subtarget->hasMips32r6()) { + if (Subtarget.hasMips32r6()) { // MIPS32r6 replaces the accumulator-based multiplies with a three register // instruction setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); @@ -180,7 +182,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setOperationAction(ISD::SELECT, MVT::f32, Legal); setOperationAction(ISD::SELECT_CC, MVT::f32, Expand); - assert(Subtarget->isFP64bit() && "FR=1 is required for MIPS32r6"); + assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6"); setOperationAction(ISD::SETCC, MVT::f64, Legal); setOperationAction(ISD::SELECT, MVT::f64, Legal); setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); @@ -199,7 +201,7 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); } - if (Subtarget->hasMips64r6()) { + if (Subtarget.hasMips64r6()) { // MIPS64r6 replaces the accumulator-based multiplies with a three register // instruction setOperationAction(ISD::MUL, MVT::i64, Legal); @@ -226,14 +228,15 @@ MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) } const MipsTargetLowering * -llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { - return new MipsSETargetLowering(TM); +llvm::createMipsSETargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI) { + return new MipsSETargetLowering(TM, STI); } const TargetRegisterClass * MipsSETargetLowering::getRepRegClassFor(MVT VT) const { if (VT == MVT::Untyped) - return Subtarget->hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; + return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass; return TargetLowering::getRepRegClassFor(VT); } @@ -327,12 +330,13 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { } bool -MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, - unsigned, - bool *Fast) const { +MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT, + unsigned, + unsigned, + bool *Fast) const { MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; - if (Subtarget->systemSupportsUnalignedAccess()) { + if (Subtarget.systemSupportsUnalignedAccess()) { // MIPS32r6/MIPS64r6 is required to support unaligned access. It's // implementation defined whether this is handled by hardware, software, or // a hybrid of the two but it's expected that most implementations will @@ -523,11 +527,11 @@ static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { if (DCI.isBeforeLegalize()) return SDValue(); - if (Subtarget->hasMips32() && !Subtarget->hasMips32r6() && + if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() && N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG)) return SDValue(N, 0); @@ -543,8 +547,8 @@ static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, // - Removes redundant zero extensions performed by an ISD::AND. static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { - if (!Subtarget->hasMSA()) + const MipsSubtarget &Subtarget) { + if (!Subtarget.hasMSA()) return SDValue(); SDValue Op0 = N->getOperand(0); @@ -575,10 +579,9 @@ static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || Log2 == ExtendTySize) { SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; - DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, - Op0->getVTList(), - makeArrayRef(Ops, Op0->getNumOperands())); - return Op0; + return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0), + Op0->getVTList(), + makeArrayRef(Ops, Op0->getNumOperands())); } } @@ -659,8 +662,8 @@ static bool isBitwiseInverse(SDValue N, SDValue OfNode) { // vector type. static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { - if (!Subtarget->hasMSA()) + const MipsSubtarget &Subtarget) { + if (!Subtarget.hasMSA()) return SDValue(); EVT Ty = N->getValueType(0); @@ -676,7 +679,7 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, SDValue Op0Op1 = Op0->getOperand(1); SDValue Op1Op0 = Op1->getOperand(0); SDValue Op1Op1 = Op1->getOperand(1); - bool IsLittleEndian = !Subtarget->isLittle(); + bool IsLittleEndian = !Subtarget.isLittle(); SDValue IfSet, IfClr, Cond; bool IsConstantMask = false; @@ -779,11 +782,11 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { if (DCI.isBeforeLegalize()) return SDValue(); - if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && + if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 && selectMSUB(N, &DAG)) return SDValue(N, 0); @@ -843,7 +846,7 @@ static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { // See if this is a vector splat immediate node. APInt SplatValue, SplatUndef; unsigned SplatBitSize; @@ -851,12 +854,12 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); - if (!Subtarget->hasDSP()) + if (!Subtarget.hasDSP()) return SDValue(); if (!BV || !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, - EltSize, !Subtarget->isLittle()) || + EltSize, !Subtarget.isLittle()) || (SplatBitSize != EltSize) || (SplatValue.getZExtValue() >= EltSize)) return SDValue(); @@ -867,7 +870,7 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { EVT Ty = N->getValueType(0); if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) @@ -890,10 +893,10 @@ static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, // used for DSPr2. static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { EVT Ty = N->getValueType(0); - if (Subtarget->hasMSA()) { + if (Subtarget.hasMSA()) { SDValue Op0 = N->getOperand(0); SDValue Op1 = N->getOperand(1); @@ -920,15 +923,14 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, TotalBits <= 32)) { SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), Op0Op0->getOperand(2) }; - DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, - Op0Op0->getVTList(), - makeArrayRef(Ops, Op0Op0->getNumOperands())); - return Op0Op0; + return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0), + Op0Op0->getVTList(), + makeArrayRef(Ops, Op0Op0->getNumOperands())); } } } - if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) + if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2())) return SDValue(); return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); @@ -937,10 +939,10 @@ static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { EVT Ty = N->getValueType(0); - if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) + if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8)) return SDValue(); return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); @@ -1034,10 +1036,10 @@ static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { } static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, - const MipsSubtarget *Subtarget) { + const MipsSubtarget &Subtarget) { EVT Ty = N->getValueType(0); - if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { + if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { // Try the following combines: // (xor (or $a, $b), (build_vector allones)) // (xor (or $a, $b), (bitcast (build_vector allones))) @@ -1165,15 +1167,14 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, } } -bool MipsSETargetLowering:: -isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const { +bool MipsSETargetLowering::isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const { if (!EnableMipsTailCalls) return false; // Return false if either the callee or caller has a byval argument. - if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) + if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg()) return false; // Return true if the callee's argument area is no larger than the @@ -1185,10 +1186,12 @@ void MipsSETargetLowering:: getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, + SDValue Chain) const { Ops.push_back(Callee); MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, - InternalLinkage, CLI, Callee, Chain); + InternalLinkage, IsCallReloc, CLI, Callee, + Chain); } SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { @@ -1215,7 +1218,7 @@ SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { Nd.isNonTemporal(), Nd.isInvariant(), std::min(Nd.getAlignment(), 4U)); - if (!Subtarget->isLittle()) + if (!Subtarget.isLittle()) std::swap(Lo, Hi); SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); @@ -1238,26 +1241,26 @@ SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Val, DAG.getConstant(1, MVT::i32)); - if (!Subtarget->isLittle()) + if (!Subtarget.isLittle()) std::swap(Lo, Hi); // i32 store to lower address. Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), - Nd.getTBAAInfo()); + Nd.getAAInfo()); // i32 store to higher address. Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), Nd.isVolatile(), Nd.isNonTemporal(), - std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); + std::min(Nd.getAlignment(), 4U), Nd.getAAInfo()); } SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, SelectionDAG &DAG) const { // MIPS32r6/MIPS64r6 removed accumulator based multiplies. - assert(!Subtarget->hasMips32r6()); + assert(!Subtarget.hasMips32r6()); EVT Ty = Op.getOperand(0).getValueType(); SDLoc DL(Op); @@ -1621,7 +1624,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_bnegi_w: case Intrinsic::mips_bnegi_d: return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), - !Subtarget->isLittle()); + !Subtarget.isLittle()); case Intrinsic::mips_bnz_b: case Intrinsic::mips_bnz_h: case Intrinsic::mips_bnz_w: @@ -1657,7 +1660,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_bseti_w: case Intrinsic::mips_bseti_d: return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), - !Subtarget->isLittle()); + !Subtarget.isLittle()); case Intrinsic::mips_bz_b: case Intrinsic::mips_bz_h: case Intrinsic::mips_bz_w: @@ -1732,7 +1735,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_copy_s_w: return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); case Intrinsic::mips_copy_s_d: - if (Subtarget->hasMips64()) + if (Subtarget.hasMips64()) // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64. return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); else { @@ -1747,7 +1750,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_copy_u_w: return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); case Intrinsic::mips_copy_u_d: - if (Subtarget->hasMips64()) + if (Subtarget.hasMips64()) // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64. return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); else { @@ -2324,12 +2327,12 @@ SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, unsigned SplatBitSize; bool HasAnyUndefs; - if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) + if (!Subtarget.hasMSA() || !ResTy.is128BitVector()) return SDValue(); if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 8, - !Subtarget->isLittle()) && SplatBitSize <= 64) { + !Subtarget.isLittle()) && SplatBitSize <= 64) { // We can only cope with 8, 16, 32, or 64-bit elements if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && SplatBitSize != 64) @@ -2744,7 +2747,8 @@ emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ // $vr0 = phi($vr2, $fbb, $vr1, $tbb) MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); const TargetRegisterClass *RC = &Mips::GPR32RegClass; DebugLoc DL = MI->getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -2809,7 +2813,8 @@ emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, // $rd = phi($rd1, $fbb, $rd2, $tbb) MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); const TargetRegisterClass *RC = &Mips::GPR32RegClass; DebugLoc DL = MI->getDebugLoc(); const BasicBlock *LLVM_BB = BB->getBasicBlock(); @@ -2870,7 +2875,8 @@ emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, // for lane 1 because it would require FR=0 mode which isn't supported by MSA. MachineBasicBlock * MipsSETargetLowering:: emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Fd = MI->getOperand(0).getReg(); @@ -2902,9 +2908,10 @@ emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ // valid because FR=1 mode which is the only supported mode in MSA. MachineBasicBlock * MipsSETargetLowering:: emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ - assert(Subtarget->isFP64bit()); + assert(Subtarget.isFP64bit()); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); unsigned Fd = MI->getOperand(0).getReg(); unsigned Ws = MI->getOperand(1).getReg(); @@ -2933,7 +2940,8 @@ emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ MachineBasicBlock * MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Wd = MI->getOperand(0).getReg(); @@ -2965,9 +2973,10 @@ MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, MachineBasicBlock * MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, MachineBasicBlock *BB) const { - assert(Subtarget->isFP64bit()); + assert(Subtarget.isFP64bit()); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Wd = MI->getOperand(0).getReg(); @@ -3015,7 +3024,8 @@ MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI, MachineBasicBlock *BB, unsigned EltSizeInBytes, bool IsFP) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Wd = MI->getOperand(0).getReg(); @@ -3025,7 +3035,7 @@ MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI, const TargetRegisterClass *VecRC = nullptr; const TargetRegisterClass *GPRRC = - Subtarget->isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + Subtarget.isGP64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; unsigned EltLog2Size; unsigned InsertOp = 0; unsigned InsveOp = 0; @@ -3125,7 +3135,8 @@ MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI, MachineBasicBlock * MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Wd = MI->getOperand(0).getReg(); @@ -3154,9 +3165,10 @@ MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, MachineBasicBlock * MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, MachineBasicBlock *BB) const { - assert(Subtarget->isFP64bit()); + assert(Subtarget.isFP64bit()); - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); unsigned Wd = MI->getOperand(0).getReg(); @@ -3184,7 +3196,8 @@ MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, MachineBasicBlock * MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetRegisterClass *RC = &Mips::MSA128WRegClass; unsigned Ws1 = RegInfo.createVirtualRegister(RC); @@ -3213,7 +3226,8 @@ MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, MachineBasicBlock * MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, MachineBasicBlock *BB) const { - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + const TargetInstrInfo *TII = + getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); const TargetRegisterClass *RC = &Mips::MSA128DRegClass; unsigned Ws1 = RegInfo.createVirtualRegister(RC); diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index 13ef6fc..d44f8d8 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSEISELLOWERING_H -#define MIPSSEISELLOWERING_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H +#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H #include "MipsISelLowering.h" #include "MipsRegisterInfo.h" @@ -20,7 +20,8 @@ namespace llvm { class MipsSETargetLowering : public MipsTargetLowering { public: - explicit MipsSETargetLowering(MipsTargetMachine &TM); + explicit MipsSETargetLowering(const MipsTargetMachine &TM, + const MipsSubtarget &STI); /// \brief Enable MSA support for the given integer type and Register /// class. @@ -30,8 +31,9 @@ namespace llvm { void addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); - bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS = 0, - bool *Fast = nullptr) const override; + bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0, + unsigned Align = 1, + bool *Fast = nullptr) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; @@ -49,15 +51,15 @@ namespace llvm { const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; private: - bool isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, - unsigned NextStackOffset, - const MipsFunctionInfo& FI) const override; + bool isEligibleForTailCallOptimization( + const CCState &CCInfo, unsigned NextStackOffset, + const MipsFunctionInfo &FI) const override; void getOpndList(SmallVectorImpl<SDValue> &Ops, std::deque< std::pair<unsigned, SDValue> > &RegsToPass, bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, - CallLoweringInfo &CLI, SDValue Callee, + bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const override; SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; @@ -112,4 +114,4 @@ namespace llvm { }; } -#endif // MipsSEISELLOWERING_H +#endif diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index 32da749..16bea8b 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -24,11 +24,10 @@ using namespace llvm; -MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm) - : MipsInstrInfo(tm, - tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), - RI(*tm.getSubtargetImpl()), - IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {} +MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) + : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B + : Mips::J), + RI(STI), IsN64(STI.isABI_N64()) {} const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { return RI; @@ -84,7 +83,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { unsigned Opc = 0, ZeroReg = 0; - bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode(); + bool isMicroMips = Subtarget.inMicroMipsMode(); if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. if (Mips::GPR32RegClass.contains(SrcReg)) { @@ -265,7 +264,7 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { MachineBasicBlock &MBB = *MI->getParent(); - bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode(); + bool isMicroMips = Subtarget.inMicroMipsMode(); unsigned Opc; switch(MI->getDesc().getOpcode()) { @@ -360,7 +359,7 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); + const MipsSubtarget &STI = Subtarget; DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu; @@ -380,7 +379,7 @@ MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, MachineBasicBlock::iterator II, DebugLoc DL, unsigned *NewImm) const { MipsAnalyzeImmediate AnalyzeImm; - const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); + const MipsSubtarget &STI = Subtarget; MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); unsigned Size = STI.isABI_N64() ? 64 : 32; unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; @@ -429,8 +428,6 @@ unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const auto &Subtarget = TM.getSubtarget<MipsSubtarget>(); - if (Subtarget.isGP64bit()) BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) .addReg(Mips::RA_64); @@ -521,8 +518,17 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); - if (SubIdx == Mips::sub_hi && FP64) { - // FIXME: The .addReg(SrcReg, RegState::Implicit) is a white lie used to + // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload + // in MipsSEFrameLowering.cpp. + assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); + + // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload + // in MipsSEFrameLowering.cpp. + assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); + + if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { + // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we + // claim to read the whole 64-bits as part of a white lie used to // temporarily work around a widespread bug in the -mfp64 support. // The problem is that none of the 32-bit fpu ops mention the fact // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that @@ -533,8 +539,8 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, // We therefore pretend that it reads the bottom 32-bits to // artificially create a dependency and prevent the scheduler // changing the behaviour of the code. - BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg).addReg( - SrcReg, RegState::Implicit); + BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) + .addReg(SrcReg); } else BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); } @@ -547,29 +553,34 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); DebugLoc dl = I->getDebugLoc(); const TargetRegisterInfo &TRI = getRegisterInfo(); - bool HasMTHC1 = TM.getSubtarget<MipsSubtarget>().hasMips32r2() || - TM.getSubtarget<MipsSubtarget>().hasMips32r6(); // When mthc1 is available, use: // mtc1 Lo, $fp // mthc1 Hi, $fp // - // Otherwise, for FP64: + // Otherwise, for O32 FPXX ABI: // spill + reload via ldc1 - // This has not been implemented since FP64 on MIPS32 and earlier is not - // supported. + // This case is handled by the frame lowering code. // // Otherwise, for FP32: // mtc1 Lo, $fp // mtc1 Hi, $fp + 1 + // + // The case where dmtc1 is available doesn't need to be handled here + // because it never creates a BuildPairF64 node. + + // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload + // in MipsSEFrameLowering.cpp. + assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); + + // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload + // in MipsSEFrameLowering.cpp. + assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) .addReg(LoReg); - if (HasMTHC1 || FP64) { - assert(TM.getSubtarget<MipsSubtarget>().hasMips32r2() && - "MTHC1 requires MIPS32r2"); - + if (Subtarget.hasMTHC1()) { // FIXME: The .addReg(DstReg) is a white lie used to temporarily work // around a widespread bug in the -mfp64 support. // The problem is that none of the 32-bit fpu ops mention the fact @@ -584,7 +595,9 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) .addReg(DstReg) .addReg(HiReg); - } else + } else if (Subtarget.isABI_FPXX()) + llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); + else BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) .addReg(HiReg); } @@ -594,28 +607,34 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, // This pseudo instruction is generated as part of the lowering of // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and // indirect jump to TargetReg - const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>(); - unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; - unsigned SP = STI.isGP64bit() ? Mips::SP_64 : Mips::SP; - unsigned RA = STI.isGP64bit() ? Mips::RA_64 : Mips::RA; - unsigned T9 = STI.isGP64bit() ? Mips::T9_64 : Mips::T9; - unsigned ZERO = STI.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; + unsigned ADDU = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; + unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; + unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; + unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; + unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; unsigned OffsetReg = I->getOperand(0).getReg(); unsigned TargetReg = I->getOperand(1).getReg(); // addu $ra, $v0, $zero // addu $sp, $sp, $v1 // jr $ra (via RetRA) + const TargetMachine &TM = MBB.getParent()->getTarget(); if (TM.getRelocationModel() == Reloc::PIC_) - BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9) - .addReg(TargetReg).addReg(ZERO); - BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA) - .addReg(TargetReg).addReg(ZERO); - BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP) - .addReg(SP).addReg(OffsetReg); + BuildMI(MBB, I, I->getDebugLoc(), + TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), T9) + .addReg(TargetReg) + .addReg(ZERO); + BuildMI(MBB, I, I->getDebugLoc(), + TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), RA) + .addReg(TargetReg) + .addReg(ZERO); + BuildMI(MBB, I, I->getDebugLoc(), + TM.getSubtargetImpl()->getInstrInfo()->get(ADDU), SP) + .addReg(SP) + .addReg(OffsetReg); expandRetRA(MBB, I); } -const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) { - return new MipsSEInstrInfo(TM); +const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { + return new MipsSEInstrInfo(STI); } diff --git a/lib/Target/Mips/MipsSEInstrInfo.h b/lib/Target/Mips/MipsSEInstrInfo.h index 9ac94ce..b2d2301 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.h +++ b/lib/Target/Mips/MipsSEInstrInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSEINSTRUCTIONINFO_H -#define MIPSSEINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H #include "MipsInstrInfo.h" #include "MipsSERegisterInfo.h" @@ -24,7 +24,7 @@ class MipsSEInstrInfo : public MipsInstrInfo { bool IsN64; public: - explicit MipsSEInstrInfo(MipsTargetMachine &TM); + explicit MipsSEInstrInfo(const MipsSubtarget &STI); const MipsRegisterInfo &getRegisterInfo() const override; diff --git a/lib/Target/Mips/MipsSERegisterInfo.cpp b/lib/Target/Mips/MipsSERegisterInfo.cpp index 0af1a6b..55c6638 100644 --- a/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -172,7 +172,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned Reg = RegInfo.createVirtualRegister(RC); const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( - MBB.getParent()->getTarget().getInstrInfo()); + MBB.getParent()->getSubtarget().getInstrInfo()); BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset); FrameReg = Reg; @@ -187,7 +187,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, unsigned NewImm = 0; const MipsSEInstrInfo &TII = *static_cast<const MipsSEInstrInfo *>( - MBB.getParent()->getTarget().getInstrInfo()); + MBB.getParent()->getSubtarget().getInstrInfo()); unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, OffsetBitSize == 16 ? &NewImm : nullptr); BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg) diff --git a/lib/Target/Mips/MipsSERegisterInfo.h b/lib/Target/Mips/MipsSERegisterInfo.h index f2f3a7e..6b70d07 100644 --- a/lib/Target/Mips/MipsSERegisterInfo.h +++ b/lib/Target/Mips/MipsSERegisterInfo.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSEREGISTERINFO_H -#define MIPSSEREGISTERINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEREGISTERINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPSSEREGISTERINFO_H #include "MipsRegisterInfo.h" diff --git a/lib/Target/Mips/MipsSelectionDAGInfo.h b/lib/Target/Mips/MipsSelectionDAGInfo.h index 2b3d527..061423f 100644 --- a/lib/Target/Mips/MipsSelectionDAGInfo.h +++ b/lib/Target/Mips/MipsSelectionDAGInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSELECTIONDAGINFO_H -#define MIPSSELECTIONDAGINFO_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_MIPS_MIPSSELECTIONDAGINFO_H #include "llvm/Target/TargetSelectionDAGInfo.h" diff --git a/lib/Target/Mips/MipsSubtarget.cpp b/lib/Target/Mips/MipsSubtarget.cpp index 693daa3..8768b12 100644 --- a/lib/Target/Mips/MipsSubtarget.cpp +++ b/lib/Target/Mips/MipsSubtarget.cpp @@ -58,6 +58,10 @@ Mips16ConstantIslands( cl::desc("MIPS: mips16 constant islands enable."), cl::init(true)); +static cl::opt<bool> +GPOpt("mgpopt", cl::Hidden, + cl::desc("MIPS: Enable gp-relative addressing of small data items")); + /// Select the Mips CPU for the given triple and cpu name. /// FIXME: Merge with the copy in MipsMCTargetDesc.cpp static StringRef selectMipsCPU(Triple TT, StringRef CPU) { @@ -104,31 +108,32 @@ static std::string computeDataLayout(const MipsSubtarget &ST) { MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little, - Reloc::Model _RM, MipsTargetMachine *_TM) - : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), - MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), - IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), - IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), - HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), - HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), - InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), - HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), - HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM), - TargetTriple(TT), + const MipsTargetMachine *_TM) + : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault), + ABI(MipsABIInfo::Unknown()), IsLittle(little), IsSingleFloat(false), + IsFPXX(false), NoABICalls(false), IsFP64bit(false), UseOddSPReg(true), + IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false), + IsLinux(true), HasMips3_32(false), HasMips3_32r2(false), + HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), + InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), + InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), + AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), + HasMSA(false), TM(_TM), TargetTriple(TT), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), - TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*TM)), - FrameLowering(MipsFrameLowering::create(*TM, *this)), - TLInfo(MipsTargetLowering::create(*TM)) { + TSInfo(DL), InstrInfo(MipsInstrInfo::create(*this)), + FrameLowering(MipsFrameLowering::create(*this)), + TLInfo(MipsTargetLowering::create(*TM, *this)) { PreviousInMips16Mode = InMips16Mode; - // Don't even attempt to generate code for MIPS-I, MIPS-II, MIPS-III, and - // MIPS-V. They have not been tested and currently exist for the integrated + if (MipsArchVersion == MipsDefault) + MipsArchVersion = Mips32; + + // Don't even attempt to generate code for MIPS-I, MIPS-III and MIPS-V. + // They have not been tested and currently exist for the integrated // assembler only. if (MipsArchVersion == Mips1) report_fatal_error("Code generation for MIPS-I is not implemented", false); - if (MipsArchVersion == Mips2) - report_fatal_error("Code generation for MIPS-II is not implemented", false); if (MipsArchVersion == Mips3) report_fatal_error("Code generation for MIPS-III is not implemented", false); @@ -136,7 +141,7 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, report_fatal_error("Code generation for MIPS-V is not implemented", false); // Assert exactly one ABI was chosen. - assert(MipsABI != UnknownABI); + assert(ABI.IsKnown()); assert((((getFeatureBits() & Mips::FeatureO32) != 0) + ((getFeatureBits() & Mips::FeatureEABI) != 0) + ((getFeatureBits() & Mips::FeatureN32) != 0) + @@ -153,9 +158,10 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, false); if (!isABI_O32() && !useOddSPReg()) - report_fatal_error("-mattr=+nooddspreg is not currently permitted for a " - "the O32 ABI.", - false); + report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false); + + if (IsFPXX && (isABI_N32() || isABI_N64())) + report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false); if (hasMips32r6()) { StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6"; @@ -170,21 +176,29 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, if (TT.find("linux") == std::string::npos) IsLinux = false; + if (NoABICalls && TM->getRelocationModel() == Reloc::PIC_) + report_fatal_error("position-independent code requires '-mabicalls'"); + // Set UseSmallSection. - // TODO: Investigate the IsLinux check. I suspect it's really checking for - // bare-metal. - UseSmallSection = !IsLinux && (RM == Reloc::Static); + UseSmallSection = GPOpt; + if (!NoABICalls && GPOpt) { + errs() << "warning: cannot use small-data accesses for '-mabicalls'" + << "\n"; + UseSmallSection = false; + } } -bool -MipsSubtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, - TargetSubtargetInfo::AntiDepBreakMode &Mode, - RegClassVector &CriticalPathRCs) const { - Mode = TargetSubtargetInfo::ANTIDEP_NONE; +/// This overrides the PostRAScheduler bit in the SchedModel for any CPU. +bool MipsSubtarget::enablePostMachineScheduler() const { return true; } + +void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const { CriticalPathRCs.clear(); - CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass - : &Mips::GPR32RegClass); - return OptLevel >= CodeGenOpt::Aggressive; + CriticalPathRCs.push_back(isGP64bit() ? + &Mips::GPR64RegClass : &Mips::GPR32RegClass); +} + +CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const { + return CodeGenOpt::Aggressive; } MipsSubtarget & @@ -197,100 +211,13 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, // Initialize scheduling itinerary for the specified CPU. InstrItins = getInstrItineraryForCPU(CPUName); - if (InMips16Mode && !TM->Options.UseSoftFloat) { - // Hard float for mips16 means essentially to compile as soft float - // but to use a runtime library for soft float that is written with - // native mips32 floating point instructions (those runtime routines - // run in mips32 hard float mode). - TM->Options.UseSoftFloat = true; - TM->Options.FloatABIType = FloatABI::Soft; + if (InMips16Mode && !TM->Options.UseSoftFloat) InMips16HardFloat = true; - } return *this; } -//FIXME: This logic for reseting the subtarget along with -// the helper classes can probably be simplified but there are a lot of -// cases so we will defer rewriting this to later. -// -void MipsSubtarget::resetSubtarget(MachineFunction *MF) { - bool ChangeToMips16 = false, ChangeToNoMips16 = false; - DEBUG(dbgs() << "resetSubtargetFeatures" << "\n"); - AttributeSet FnAttrs = MF->getFunction()->getAttributes(); - ChangeToMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, - "mips16"); - ChangeToNoMips16 = FnAttrs.hasAttribute(AttributeSet::FunctionIndex, - "nomips16"); - assert (!(ChangeToMips16 & ChangeToNoMips16) && - "mips16 and nomips16 specified on the same function"); - if (ChangeToMips16) { - if (PreviousInMips16Mode) - return; - OverrideMode = Mips16Override; - PreviousInMips16Mode = true; - setHelperClassesMips16(); - return; - } else if (ChangeToNoMips16) { - if (!PreviousInMips16Mode) - return; - OverrideMode = NoMips16Override; - PreviousInMips16Mode = false; - setHelperClassesMipsSE(); - return; - } else { - if (OverrideMode == NoOverride) - return; - OverrideMode = NoOverride; - DEBUG(dbgs() << "back to default" << "\n"); - if (inMips16Mode() && !PreviousInMips16Mode) { - setHelperClassesMips16(); - PreviousInMips16Mode = true; - } else if (!inMips16Mode() && PreviousInMips16Mode) { - setHelperClassesMipsSE(); - PreviousInMips16Mode = false; - } - return; - } -} - -void MipsSubtarget::setHelperClassesMips16() { - InstrInfoSE.swap(InstrInfo); - FrameLoweringSE.swap(FrameLowering); - TLInfoSE.swap(TLInfo); - if (!InstrInfo16) { - InstrInfo.reset(MipsInstrInfo::create(*TM)); - FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); - TLInfo.reset(MipsTargetLowering::create(*TM)); - } else { - InstrInfo16.swap(InstrInfo); - FrameLowering16.swap(FrameLowering); - TLInfo16.swap(TLInfo); - } - assert(TLInfo && "null target lowering 16"); - assert(InstrInfo && "null instr info 16"); - assert(FrameLowering && "null frame lowering 16"); -} - -void MipsSubtarget::setHelperClassesMipsSE() { - InstrInfo16.swap(InstrInfo); - FrameLowering16.swap(FrameLowering); - TLInfo16.swap(TLInfo); - if (!InstrInfoSE) { - InstrInfo.reset(MipsInstrInfo::create(*TM)); - FrameLowering.reset(MipsFrameLowering::create(*TM, *this)); - TLInfo.reset(MipsTargetLowering::create(*TM)); - } else { - InstrInfoSE.swap(InstrInfo); - FrameLoweringSE.swap(FrameLowering); - TLInfoSE.swap(TLInfo); - } - assert(TLInfo && "null target lowering in SE"); - assert(InstrInfo && "null instr info SE"); - assert(FrameLowering && "null frame lowering SE"); -} - -bool MipsSubtarget::mipsSEUsesSoftFloat() const { +bool MipsSubtarget::abiUsesSoftFloat() const { return TM->Options.UseSoftFloat && !InMips16HardFloat; } @@ -298,3 +225,7 @@ bool MipsSubtarget::useConstantIslands() { DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n"); return Mips16ConstantIslands; } + +Reloc::Model MipsSubtarget::getRelocationModel() const { + return TM->getRelocationModel(); +} diff --git a/lib/Target/Mips/MipsSubtarget.h b/lib/Target/Mips/MipsSubtarget.h index a3dcf03..bff9013 100644 --- a/lib/Target/Mips/MipsSubtarget.h +++ b/lib/Target/Mips/MipsSubtarget.h @@ -11,18 +11,18 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSSUBTARGET_H -#define MIPSSUBTARGET_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H +#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H #include "MipsFrameLowering.h" #include "MipsISelLowering.h" #include "MipsInstrInfo.h" -#include "MipsJITInfo.h" #include "MipsSelectionDAGInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Target/TargetSubtargetInfo.h" +#include "MipsABIInfo.h" #include <string> #define GET_SUBTARGETINFO_HEADER @@ -36,14 +36,8 @@ class MipsTargetMachine; class MipsSubtarget : public MipsGenSubtargetInfo { virtual void anchor(); -public: - // NOTE: O64 will not be supported. - enum MipsABIEnum { - UnknownABI, O32, N32, N64, EABI - }; - -protected: enum MipsArchEnum { + MipsDefault, Mips1, Mips2, Mips32, Mips32r2, Mips32r6, Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r6 }; @@ -51,8 +45,8 @@ protected: // Mips architecture version MipsArchEnum MipsArchVersion; - // Mips supported ABIs - MipsABIEnum MipsABI; + // Selected ABI + MipsABIInfo ABI; // IsLittle - The target is Little Endian bool IsLittle; @@ -65,6 +59,9 @@ protected: // IsFPXX - MIPS O32 modeless ABI. bool IsFPXX; + // NoABICalls - Disable SVR4-style position-independent code. + bool NoABICalls; + // IsFP64bit - The target processor has 64-bit floating point registers. bool IsFP64bit; @@ -135,48 +132,39 @@ protected: InstrItineraryData InstrItins; - // Relocation Model - Reloc::Model RM; - // We can override the determination of whether we are in mips16 mode // as from the command line enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode; - MipsTargetMachine *TM; + const MipsTargetMachine *TM; Triple TargetTriple; const DataLayout DL; // Calculates type size & alignment const MipsSelectionDAGInfo TSInfo; - MipsJITInfo JITInfo; std::unique_ptr<const MipsInstrInfo> InstrInfo; std::unique_ptr<const MipsFrameLowering> FrameLowering; std::unique_ptr<const MipsTargetLowering> TLInfo; - std::unique_ptr<const MipsInstrInfo> InstrInfo16; - std::unique_ptr<const MipsFrameLowering> FrameLowering16; - std::unique_ptr<const MipsTargetLowering> TLInfo16; - std::unique_ptr<const MipsInstrInfo> InstrInfoSE; - std::unique_ptr<const MipsFrameLowering> FrameLoweringSE; - std::unique_ptr<const MipsTargetLowering> TLInfoSE; public: - bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, - AntiDepBreakMode& Mode, - RegClassVector& CriticalPathRCs) const override; + /// This overrides the PostRAScheduler bit in the SchedModel for each CPU. + bool enablePostMachineScheduler() const override; + void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; + CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; /// Only O32 and EABI supported right now. - bool isABI_EABI() const { return MipsABI == EABI; } - bool isABI_N64() const { return MipsABI == N64; } - bool isABI_N32() const { return MipsABI == N32; } - bool isABI_O32() const { return MipsABI == O32; } - bool isABI_FPXX() const { return false; } // TODO: add check for FPXX - unsigned getTargetABI() const { return MipsABI; } + bool isABI_EABI() const { return ABI.IsEABI(); } + bool isABI_N64() const { return ABI.IsN64(); } + bool isABI_N32() const { return ABI.IsN32(); } + bool isABI_O32() const { return ABI.IsO32(); } + bool isABI_FPXX() const { return isABI_O32() && IsFPXX; } + const MipsABIInfo &getABI() const { return ABI; } /// This constructor initializes the data members to match that /// of the specified triple. MipsSubtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, bool little, Reloc::Model RM, - MipsTargetMachine *TM); + const std::string &FS, bool little, + const MipsTargetMachine *TM); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. @@ -209,30 +197,25 @@ public: bool hasCnMips() const { return HasCnMips; } bool isLittle() const { return IsLittle; } + bool isABICalls() const { return !NoABICalls; } bool isFPXX() const { return IsFPXX; } bool isFP64bit() const { return IsFP64bit; } bool useOddSPReg() const { return UseOddSPReg; } + bool noOddSPReg() const { return !UseOddSPReg; } bool isNaN2008() const { return IsNaN2008bit; } - bool isNotFP64bit() const { return !IsFP64bit; } bool isGP64bit() const { return IsGP64bit; } bool isGP32bit() const { return !IsGP64bit; } + unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; } bool isSingleFloat() const { return IsSingleFloat; } - bool isNotSingleFloat() const { return !IsSingleFloat; } bool hasVFPU() const { return HasVFPU; } - bool inMips16Mode() const { - switch (OverrideMode) { - case NoOverride: - return InMips16Mode; - case Mips16Override: - return true; - case NoMips16Override: - return false; - } - llvm_unreachable("Unexpected mode"); - } + bool inMips16Mode() const { return InMips16Mode; } bool inMips16ModeDefault() const { return InMips16Mode; } + // Hard float for mips16 means essentially to compile as soft float + // but to use a runtime library for soft float that is written with + // native mips32 floating point instructions (those runtime routines + // run in mips32 hard float mode). bool inMips16HardFloat() const { return inMips16Mode() && InMips16HardFloat; } @@ -245,7 +228,7 @@ public: bool hasStandardEncoding() const { return !inMips16Mode(); } - bool mipsSEUsesSoftFloat() const; + bool abiUsesSoftFloat() const; bool enableLongBranchPass() const { return hasStandardEncoding() || allowMixed16_32(); @@ -253,15 +236,14 @@ public: /// Features related to the presence of specific instructions. bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); } + bool hasMTHC1() const { return hasMips32r2(); } - const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } bool allowMixed16_32() const { return inMips16ModeDefault() | AllowMixed16_32;} bool os16() const { return Os16;}; bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } - bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); } // for now constant islands are on for the whole compilation unit but we only // really use them if in addition we are in mips16 mode @@ -270,10 +252,7 @@ public: unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } // Grab relocation model - Reloc::Model getRelocationModel() const {return RM;} - - /// \brief Reset the subtarget for the Mips target. - void resetSubtarget(MachineFunction *MF); + Reloc::Model getRelocationModel() const; MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS, const TargetMachine *TM); @@ -289,17 +268,23 @@ public: void setHelperClassesMips16(); void setHelperClassesMipsSE(); - MipsJITInfo *getJITInfo() { return &JITInfo; } - const MipsSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - const DataLayout *getDataLayout() const { return &DL; } - const MipsInstrInfo *getInstrInfo() const { return InstrInfo.get(); } - const TargetFrameLowering *getFrameLowering() const { + const MipsSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const DataLayout *getDataLayout() const override { return &DL; } + const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } + const TargetFrameLowering *getFrameLowering() const override { return FrameLowering.get(); } - const MipsRegisterInfo *getRegisterInfo() const { + const MipsRegisterInfo *getRegisterInfo() const override { return &InstrInfo->getRegisterInfo(); } - const MipsTargetLowering *getTargetLowering() const { return TLInfo.get(); } + const MipsTargetLowering *getTargetLowering() const override { + return TLInfo.get(); + } + const InstrItineraryData *getInstrItineraryData() const override { + return &InstrItins; + } }; } // End llvm namespace diff --git a/lib/Target/Mips/MipsTargetMachine.cpp b/lib/Target/Mips/MipsTargetMachine.cpp index 425dbf1..33280e3 100644 --- a/lib/Target/Mips/MipsTargetMachine.cpp +++ b/lib/Target/Mips/MipsTargetMachine.cpp @@ -26,6 +26,7 @@ #include "MipsSEISelDAGToDAG.h" #include "MipsSEISelLowering.h" #include "MipsSEInstrInfo.h" +#include "MipsTargetObjectFile.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/CodeGen/Passes.h" #include "llvm/PassManager.h" @@ -56,10 +57,20 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - Subtarget(TT, CPU, FS, isLittle, RM, this) { + isLittle(isLittle), + TLOF(make_unique<MipsTargetObjectFile>()), + Subtarget(nullptr), + DefaultSubtarget(TT, CPU, FS, isLittle, this), + NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", + isLittle, this), + Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", + isLittle, this) { + Subtarget = &DefaultSubtarget; initAsmInfo(); } +MipsTargetMachine::~MipsTargetMachine() {} + void MipsebTargetMachine::anchor() { } MipsebTargetMachine:: @@ -78,6 +89,63 @@ MipselTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL) : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} +const MipsSubtarget * +MipsTargetMachine::getSubtargetImpl(const Function &F) const { + AttributeSet FnAttrs = F.getAttributes(); + Attribute CPUAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu"); + Attribute FSAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features"); + + std::string CPU = !CPUAttr.hasAttribute(Attribute::None) + ? CPUAttr.getValueAsString().str() + : TargetCPU; + std::string FS = !FSAttr.hasAttribute(Attribute::None) + ? FSAttr.getValueAsString().str() + : TargetFS; + bool hasMips16Attr = + !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "mips16") + .hasAttribute(Attribute::None); + bool hasNoMips16Attr = + !FnAttrs.getAttribute(AttributeSet::FunctionIndex, "nomips16") + .hasAttribute(Attribute::None); + + // FIXME: This is related to the code below to reset the target options, + // we need to know whether or not the soft float flag is set on the + // function before we can generate a subtarget. We also need to use + // it as a key for the subtarget since that can be the only difference + // between two functions. + Attribute SFAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "use-soft-float"); + bool softFloat = !SFAttr.hasAttribute(Attribute::None) + ? SFAttr.getValueAsString() == "true" + : Options.UseSoftFloat; + + if (hasMips16Attr) + FS += FS.empty() ? "+mips16" : ",+mips16"; + else if (hasNoMips16Attr) + FS += FS.empty() ? "-mips16" : ",-mips16"; + + auto &I = SubtargetMap[CPU + FS + (softFloat ? "use-soft-float=true" + : "use-soft-float=false")]; + if (!I) { + // This needs to be done before we create a new subtarget since any + // creation will depend on the TM and the code generation flags on the + // function that reside in TargetOptions. + resetTargetOptions(F); + I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, this); + } + return I.get(); +} + +void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { + DEBUG(dbgs() << "resetSubtarget\n"); + + Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction())); + MF->setSubtarget(Subtarget); + return; +} + namespace { /// Mips Code Generator Pass Configuration Options. class MipsPassConfig : public TargetPassConfig { @@ -115,22 +183,18 @@ TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { void MipsPassConfig::addIRPasses() { TargetPassConfig::addIRPasses(); + addPass(createAtomicExpandPass(&getMipsTargetMachine())); if (getMipsSubtarget().os16()) addPass(createMipsOs16(getMipsTargetMachine())); if (getMipsSubtarget().inMips16HardFloat()) addPass(createMips16HardFloat(getMipsTargetMachine())); - addPass(createPartiallyInlineLibCallsPass()); } // Install an instruction selector pass using // the ISelDag to gen Mips code. bool MipsPassConfig::addInstSelector() { - if (getMipsSubtarget().allowMixed16_32()) { - addPass(createMipsModuleISelDag(getMipsTargetMachine())); - addPass(createMips16ISelDag(getMipsTargetMachine())); - addPass(createMipsSEISelDag(getMipsTargetMachine())); - } else { - addPass(createMipsISelDag(getMipsTargetMachine())); - } + addPass(createMipsModuleISelDag(getMipsTargetMachine())); + addPass(createMips16ISelDag(getMipsTargetMachine())); + addPass(createMipsSEISelDag(getMipsTargetMachine())); return false; } @@ -149,7 +213,7 @@ bool MipsPassConfig::addPreRegAlloc() { } void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) { - if (Subtarget.allowMixed16_32()) { + if (Subtarget->allowMixed16_32()) { DEBUG(errs() << "No "); //FIXME: The Basic Target Transform Info // pass needs to become a function pass instead of @@ -166,21 +230,8 @@ void MipsTargetMachine::addAnalysisPasses(PassManagerBase &PM) { // print out the code after the passes. bool MipsPassConfig::addPreEmitPass() { MipsTargetMachine &TM = getMipsTargetMachine(); - const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); addPass(createMipsDelaySlotFillerPass(TM)); - - if (Subtarget.enableLongBranchPass()) - addPass(createMipsLongBranchPass(TM)); - if (Subtarget.inMips16Mode() || - Subtarget.allowMixed16_32()) - addPass(createMipsConstantIslandPass(TM)); - + addPass(createMipsLongBranchPass(TM)); + addPass(createMipsConstantIslandPass(TM)); return true; } - -bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, - JITCodeEmitter &JCE) { - // Machine code emitter pass for Mips. - PM.add(createMipsJITCodeEmitterPass(*this, JCE)); - return false; -} diff --git a/lib/Target/Mips/MipsTargetMachine.h b/lib/Target/Mips/MipsTargetMachine.h index a0e7d43..1349f82 100644 --- a/lib/Target/Mips/MipsTargetMachine.h +++ b/lib/Target/Mips/MipsTargetMachine.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSTARGETMACHINE_H -#define MIPSTARGETMACHINE_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H +#define LLVM_LIB_TARGET_MIPS_MIPSTARGETMACHINE_H #include "MipsSubtarget.h" #include "llvm/CodeGen/Passes.h" @@ -25,48 +25,40 @@ class formatted_raw_ostream; class MipsRegisterInfo; class MipsTargetMachine : public LLVMTargetMachine { - MipsSubtarget Subtarget; + bool isLittle; + std::unique_ptr<TargetLoweringObjectFile> TLOF; + MipsSubtarget *Subtarget; + MipsSubtarget DefaultSubtarget; + MipsSubtarget NoMips16Subtarget; + MipsSubtarget Mips16Subtarget; + + mutable StringMap<std::unique_ptr<MipsSubtarget>> SubtargetMap; public: MipsTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle); - - virtual ~MipsTargetMachine() {} + ~MipsTargetMachine() override; void addAnalysisPasses(PassManagerBase &PM) override; - const MipsInstrInfo *getInstrInfo() const override { - return getSubtargetImpl()->getInstrInfo(); - } - const TargetFrameLowering *getFrameLowering() const override { - return getSubtargetImpl()->getFrameLowering(); - } - const MipsSubtarget *getSubtargetImpl() const override { return &Subtarget; } - const InstrItineraryData *getInstrItineraryData() const override { - return Subtarget.inMips16Mode() - ? nullptr - : &getSubtargetImpl()->getInstrItineraryData(); - } - MipsJITInfo *getJITInfo() override { - return Subtarget.getJITInfo(); - } - const MipsRegisterInfo *getRegisterInfo() const override { - return getSubtargetImpl()->getRegisterInfo(); - } - const MipsTargetLowering *getTargetLowering() const override { - return getSubtargetImpl()->getTargetLowering(); - } - const DataLayout *getDataLayout() const override { - return getSubtargetImpl()->getDataLayout(); - } - const MipsSelectionDAGInfo* getSelectionDAGInfo() const override { - return getSubtargetImpl()->getSelectionDAGInfo(); + const MipsSubtarget *getSubtargetImpl() const override { + if (Subtarget) + return Subtarget; + return &DefaultSubtarget; } + const MipsSubtarget *getSubtargetImpl(const Function &F) const override; + + /// \brief Reset the subtarget for the Mips target. + void resetSubtarget(MachineFunction *MF); + // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// MipsebTargetMachine - Mips32/64 big endian target machine. diff --git a/lib/Target/Mips/MipsTargetObjectFile.cpp b/lib/Target/Mips/MipsTargetObjectFile.cpp index 13f9408..b56c39b 100644 --- a/lib/Target/Mips/MipsTargetObjectFile.cpp +++ b/lib/Target/Mips/MipsTargetObjectFile.cpp @@ -24,6 +24,17 @@ SSThreshold("mips-ssection-threshold", cl::Hidden, cl::desc("Small data and bss section threshold size (default=8)"), cl::init(8)); +static cl::opt<bool> +LocalSData("mlocal-sdata", cl::Hidden, + cl::desc("MIPS: Use gp_rel for object-local data."), + cl::init(true)); + +static cl::opt<bool> +ExternSData("mextern-sdata", cl::Hidden, + cl::desc("MIPS: Use gp_rel for data that is not defined by the " + "current object."), + cl::init(true)); + void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ TargetLoweringObjectFileELF::Initialize(Ctx, TM); InitializeELF(TM.Options.UseInitArray); @@ -37,29 +48,46 @@ void MipsTargetObjectFile::Initialize(MCContext &Ctx, const TargetMachine &TM){ getContext().getELFSection(".sbss", ELF::SHT_NOBITS, ELF::SHF_WRITE |ELF::SHF_ALLOC, SectionKind::getBSS()); + this->TM = &TM; } // A address must be loaded from a small section if its size is less than the // small section size threshold. Data in this section must be addressed using // gp_rel operator. static bool IsInSmallSection(uint64_t Size) { + // gcc has traditionally not treated zero-sized objects as small data, so this + // is effectively part of the ABI. return Size > 0 && Size <= SSThreshold; } -bool MipsTargetObjectFile::IsGlobalInSmallSection(const GlobalValue *GV, - const TargetMachine &TM) const { +/// Return true if this global address should be placed into small data/bss +/// section. +bool MipsTargetObjectFile:: +IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM) const { + // We first check the case where global is a declaration, because finding + // section kind using getKindForGlobal() is only allowed for global + // definitions. if (GV->isDeclaration() || GV->hasAvailableExternallyLinkage()) - return false; + return IsGlobalInSmallSectionImpl(GV, TM); return IsGlobalInSmallSection(GV, TM, getKindForGlobal(GV, TM)); } -/// IsGlobalInSmallSection - Return true if this global address should be -/// placed into small data/bss section. +/// Return true if this global address should be placed into small data/bss +/// section. bool MipsTargetObjectFile:: IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, SectionKind Kind) const { + return (IsGlobalInSmallSectionImpl(GV, TM) && + (Kind.isDataRel() || Kind.isBSS() || Kind.isCommon())); +} +/// Return true if this global address should be placed into small data/bss +/// section. This method does all the work, except for checking the section +/// kind. +bool MipsTargetObjectFile:: +IsGlobalInSmallSectionImpl(const GlobalValue *GV, + const TargetMachine &TM) const { const MipsSubtarget &Subtarget = TM.getSubtarget<MipsSubtarget>(); // Return if small section is not available. @@ -71,21 +99,20 @@ IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, if (!GVA) return false; - // We can only do this for datarel or BSS objects for now. - if (!Kind.isBSS() && !Kind.isDataRel()) + // Enforce -mlocal-sdata. + if (!LocalSData && GV->hasLocalLinkage()) return false; - // If this is a internal constant string, there is a special - // section for it, but not in small data/bss. - if (Kind.isMergeable1ByteCString()) + // Enforce -mextern-sdata. + if (!ExternSData && ((GV->hasExternalLinkage() && GV->isDeclaration()) || + GV->hasCommonLinkage())) return false; Type *Ty = GV->getType()->getElementType(); - return IsInSmallSection(TM.getDataLayout()->getTypeAllocSize(Ty)); + return IsInSmallSection( + TM.getSubtargetImpl()->getDataLayout()->getTypeAllocSize(Ty)); } - - const MCSection *MipsTargetObjectFile:: SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler &Mang, const TargetMachine &TM) const { @@ -95,9 +122,27 @@ SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, // Handle Small Section classification here. if (Kind.isBSS() && IsGlobalInSmallSection(GV, TM, Kind)) return SmallBSSSection; - if (Kind.isDataNoRel() && IsGlobalInSmallSection(GV, TM, Kind)) + if (Kind.isDataRel() && IsGlobalInSmallSection(GV, TM, Kind)) return SmallDataSection; // Otherwise, we work the same as ELF. return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,TM); } + +/// Return true if this constant should be placed into small data section. +bool MipsTargetObjectFile:: +IsConstantInSmallSection(const Constant *CN, const TargetMachine &TM) const { + return (TM.getSubtarget<MipsSubtarget>().useSmallSection() && + LocalSData && + IsInSmallSection(TM.getSubtargetImpl()->getDataLayout() + ->getTypeAllocSize(CN->getType()))); +} + +const MCSection *MipsTargetObjectFile:: +getSectionForConstant(SectionKind Kind, const Constant *C) const { + if (IsConstantInSmallSection(C, *TM)) + return SmallDataSection; + + // Otherwise, we work the same as ELF. + return TargetLoweringObjectFileELF::getSectionForConstant(Kind, C); +} diff --git a/lib/Target/Mips/MipsTargetObjectFile.h b/lib/Target/Mips/MipsTargetObjectFile.h index 2bf5a75..3a2b298 100644 --- a/lib/Target/Mips/MipsTargetObjectFile.h +++ b/lib/Target/Mips/MipsTargetObjectFile.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_MIPS_TARGETOBJECTFILE_H -#define LLVM_TARGET_MIPS_TARGETOBJECTFILE_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_MIPS_MIPSTARGETOBJECTFILE_H #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" @@ -17,21 +17,30 @@ namespace llvm { class MipsTargetObjectFile : public TargetLoweringObjectFileELF { const MCSection *SmallDataSection; const MCSection *SmallBSSSection; + const TargetMachine *TM; public: void Initialize(MCContext &Ctx, const TargetMachine &TM) override; - - /// IsGlobalInSmallSection - Return true if this global address should be - /// placed into small data/bss section. - bool IsGlobalInSmallSection(const GlobalValue *GV, - const TargetMachine &TM, SectionKind Kind)const; + /// Return true if this global address should be placed into small data/bss + /// section. + bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, + SectionKind Kind) const; bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM) const; + bool IsGlobalInSmallSectionImpl(const GlobalValue *GV, + const TargetMachine &TM) const; const MCSection *SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, Mangler &Mang, const TargetMachine &TM) const override; + + /// Return true if this constant should be placed into small data section. + bool IsConstantInSmallSection(const Constant *CN, + const TargetMachine &TM) const; + + const MCSection *getSectionForConstant(SectionKind Kind, + const Constant *C) const override; }; } // end namespace llvm diff --git a/lib/Target/Mips/MipsTargetStreamer.h b/lib/Target/Mips/MipsTargetStreamer.h index 99f7d4c..c1f17933 100644 --- a/lib/Target/Mips/MipsTargetStreamer.h +++ b/lib/Target/Mips/MipsTargetStreamer.h @@ -7,10 +7,11 @@ // //===----------------------------------------------------------------------===// -#ifndef MIPSTARGETSTREAMER_H -#define MIPSTARGETSTREAMER_H +#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETSTREAMER_H +#define LLVM_LIB_TARGET_MIPS_MIPSTARGETSTREAMER_H #include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "MCTargetDesc/MipsABIFlagsSection.h" @@ -30,6 +31,8 @@ public: virtual void emitDirectiveSetNoReorder(); virtual void emitDirectiveSetMacro(); virtual void emitDirectiveSetNoMacro(); + virtual void emitDirectiveSetMsa(); + virtual void emitDirectiveSetNoMsa(); virtual void emitDirectiveSetAt(); virtual void emitDirectiveSetNoAt(); virtual void emitDirectiveEnd(StringRef Name); @@ -45,13 +48,26 @@ public: virtual void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff); virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff); + virtual void emitDirectiveSetArch(StringRef Arch); + virtual void emitDirectiveSetMips0(); + virtual void emitDirectiveSetMips1(); + virtual void emitDirectiveSetMips2(); + virtual void emitDirectiveSetMips3(); + virtual void emitDirectiveSetMips4(); + virtual void emitDirectiveSetMips5(); + virtual void emitDirectiveSetMips32(); virtual void emitDirectiveSetMips32R2(); + virtual void emitDirectiveSetMips32R6(); virtual void emitDirectiveSetMips64(); virtual void emitDirectiveSetMips64R2(); + virtual void emitDirectiveSetMips64R6(); virtual void emitDirectiveSetDsp(); + virtual void emitDirectiveSetNoDsp(); + virtual void emitDirectiveSetPop(); + virtual void emitDirectiveSetPush(); // PIC support - virtual void emitDirectiveCpload(unsigned RegNo); + virtual void emitDirectiveCpLoad(unsigned RegNo); virtual void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg); @@ -72,8 +88,8 @@ public: virtual void emitDirectiveModuleOddSPReg(bool Enabled, bool IsO32ABI); virtual void emitDirectiveSetFp(MipsABIFlagsSection::FpABIKind Value){}; virtual void emitMipsAbiFlags(){}; - void setCanHaveModuleDir(bool Can) { canHaveModuleDirective = Can; } - bool getCanHaveModuleDir() { return canHaveModuleDirective; } + void forbidModuleDirective() { ModuleDirectiveAllowed = false; } + bool isModuleDirectiveAllowed() { return ModuleDirectiveAllowed; } // This method enables template classes to set internal abi flags // structure values. @@ -87,8 +103,21 @@ public: protected: MipsABIFlagsSection ABIFlagsSection; + bool GPRInfoSet; + unsigned GPRBitMask; + int GPROffset; + + bool FPRInfoSet; + unsigned FPRBitMask; + int FPROffset; + + bool FrameInfoSet; + int FrameOffset; + unsigned FrameReg; + unsigned ReturnReg; + private: - bool canHaveModuleDirective; + bool ModuleDirectiveAllowed; }; // This part is for ascii assembly output @@ -106,6 +135,8 @@ public: void emitDirectiveSetNoReorder() override; void emitDirectiveSetMacro() override; void emitDirectiveSetNoMacro() override; + void emitDirectiveSetMsa() override; + void emitDirectiveSetNoMsa() override; void emitDirectiveSetAt() override; void emitDirectiveSetNoAt() override; void emitDirectiveEnd(StringRef Name) override; @@ -121,13 +152,26 @@ public: void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override; void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override; + void emitDirectiveSetArch(StringRef Arch) override; + void emitDirectiveSetMips0() override; + void emitDirectiveSetMips1() override; + void emitDirectiveSetMips2() override; + void emitDirectiveSetMips3() override; + void emitDirectiveSetMips4() override; + void emitDirectiveSetMips5() override; + void emitDirectiveSetMips32() override; void emitDirectiveSetMips32R2() override; + void emitDirectiveSetMips32R6() override; void emitDirectiveSetMips64() override; void emitDirectiveSetMips64R2() override; + void emitDirectiveSetMips64R6() override; void emitDirectiveSetDsp() override; + void emitDirectiveSetNoDsp() override; + void emitDirectiveSetPop() override; + void emitDirectiveSetPush() override; // PIC support - virtual void emitDirectiveCpload(unsigned RegNo); + void emitDirectiveCpLoad(unsigned RegNo) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; @@ -157,14 +201,8 @@ public: void emitDirectiveSetMicroMips() override; void emitDirectiveSetNoMicroMips() override; void emitDirectiveSetMips16() override; - void emitDirectiveSetNoMips16() override; - void emitDirectiveSetReorder() override; void emitDirectiveSetNoReorder() override; - void emitDirectiveSetMacro() override; - void emitDirectiveSetNoMacro() override; - void emitDirectiveSetAt() override; - void emitDirectiveSetNoAt() override; void emitDirectiveEnd(StringRef Name) override; void emitDirectiveEnt(const MCSymbol &Symbol) override; @@ -178,13 +216,8 @@ public: void emitMask(unsigned CPUBitmask, int CPUTopSavedRegOff) override; void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override; - void emitDirectiveSetMips32R2() override; - void emitDirectiveSetMips64() override; - void emitDirectiveSetMips64R2() override; - void emitDirectiveSetDsp() override; - // PIC support - virtual void emitDirectiveCpload(unsigned RegNo); + void emitDirectiveCpLoad(unsigned RegNo) override; void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset, const MCSymbol &Sym, bool IsReg) override; |