diff options
Diffstat (limited to 'lib/Target/PowerPC')
47 files changed, 357 insertions, 189 deletions
diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt index 1b85495..bcd8bd2 100644 --- a/lib/Target/PowerPC/CMakeLists.txt +++ b/lib/Target/PowerPC/CMakeLists.txt @@ -21,6 +21,7 @@ add_llvm_target(PowerPCCodeGen PPCFrameLowering.cpp PPCJITInfo.cpp PPCMCInstLower.cpp + PPCMachineFunctionInfo.cpp PPCRegisterInfo.cpp PPCSubtarget.cpp PPCTargetMachine.cpp diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp index b6a0835..000d6d4 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp @@ -94,7 +94,6 @@ void PPCInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo, unsigned Code = MI->getOperand(OpNo).getImm(); if (StringRef(Modifier) == "cc") { switch ((PPC::Predicate)Code) { - default: assert(0 && "Invalid predicate"); case PPC::PRED_ALWAYS: return; // Don't print anything for always. case PPC::PRED_LT: O << "lt"; return; case PPC::PRED_LE: O << "le"; return; @@ -175,7 +174,7 @@ void PPCInstPrinter::printcrbitm(const MCInst *MI, unsigned OpNo, unsigned CCReg = MI->getOperand(OpNo).getReg(); unsigned RegNo; switch (CCReg) { - default: assert(0 && "Unknown CR register"); + default: llvm_unreachable("Unknown CR register"); case PPC::CR0: RegNo = 0; break; case PPC::CR1: RegNo = 1; break; case PPC::CR2: RegNo = 2; break; diff --git a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h index 4ed4b76..21fc733 100644 --- a/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h +++ b/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h @@ -1,4 +1,4 @@ -//===-- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax ----------===// +//===- PPCInstPrinter.h - Convert PPC MCInst to assembly syntax -*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -24,8 +24,9 @@ class PPCInstPrinter : public MCInstPrinter { // 0 -> AIX, 1 -> Darwin. unsigned SyntaxVariant; public: - PPCInstPrinter(const MCAsmInfo &MAI, unsigned syntaxVariant) - : MCInstPrinter(MAI), SyntaxVariant(syntaxVariant) {} + PPCInstPrinter(const MCAsmInfo &MAI, const MCRegisterInfo &MRI, + unsigned syntaxVariant) + : MCInstPrinter(MAI, MRI), SyntaxVariant(syntaxVariant) {} bool isDarwinSyntax() const { return SyntaxVariant == 1; diff --git a/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt b/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt index febf438..b674883 100644 --- a/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt +++ b/lib/Target/PowerPC/MCTargetDesc/CMakeLists.txt @@ -4,6 +4,7 @@ add_llvm_library(LLVMPowerPCDesc PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp PPCPredicates.cpp + PPCELFObjectWriter.cpp ) add_dependencies(LLVMPowerPCDesc PowerPCCommonTableGen) diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp index 34a5774..02dad45 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp @@ -57,13 +57,6 @@ public: MCValue Target, uint64_t &FixedValue) {} }; -class PPCELFObjectWriter : public MCELFObjectTargetWriter { -public: - PPCELFObjectWriter(bool Is64Bit, Triple::OSType OSType, uint16_t EMachine, - bool HasRelocationAddend, bool isLittleEndian) - : MCELFObjectTargetWriter(Is64Bit, OSType, EMachine, HasRelocationAddend) {} -}; - class PPCAsmBackend : public MCAsmBackend { const Target &TheTarget; public: @@ -80,16 +73,16 @@ public: { "fixup_ppc_ha16", 16, 16, 0 }, { "fixup_ppc_lo14", 16, 14, 0 } }; - + if (Kind < FirstTargetFixupKind) return MCAsmBackend::getFixupKindInfo(Kind); - + assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && "Invalid kind!"); return Infos[Kind - FirstTargetFixupKind]; } - - bool MayNeedRelaxation(const MCInst &Inst) const { + + bool mayNeedRelaxation(const MCInst &Inst) const { // FIXME. return false; } @@ -99,24 +92,23 @@ public: const MCInstFragment *DF, const MCAsmLayout &Layout) const { // FIXME. - assert(0 && "RelaxInstruction() unimplemented"); - return false; + llvm_unreachable("relaxInstruction() unimplemented"); } - - void RelaxInstruction(const MCInst &Inst, MCInst &Res) const { + + void relaxInstruction(const MCInst &Inst, MCInst &Res) const { // FIXME. - assert(0 && "RelaxInstruction() unimplemented"); + llvm_unreachable("relaxInstruction() unimplemented"); } - - bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const { + + bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { // FIXME: Zero fill for now. That's not right, but at least will get the // section size right. for (uint64_t i = 0; i != Count; ++i) OW->Write8(0); return true; - } - + } + unsigned getPointerSize() const { StringRef Name = TheTarget.getName(); if (Name == "ppc64") return 8; @@ -132,12 +124,12 @@ namespace { class DarwinPPCAsmBackend : public PPCAsmBackend { public: DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { } - - void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, + + void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const { - assert(0 && "UNIMP"); + llvm_unreachable("UNIMP"); } - + MCObjectWriter *createObjectWriter(raw_ostream &OS) const { bool is64 = getPointerSize() == 8; return createMachObjectWriter(new PPCMachObjectWriter( @@ -147,19 +139,19 @@ namespace { object::mach::CSPPC_ALL), OS, /*IsLittleEndian=*/false); } - + virtual bool doesSectionRequireSymbols(const MCSection &Section) const { return false; } }; class ELFPPCAsmBackend : public PPCAsmBackend { - Triple::OSType OSType; + uint8_t OSABI; public: - ELFPPCAsmBackend(const Target &T, Triple::OSType OSType) : - PPCAsmBackend(T), OSType(OSType) { } - - void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, + ELFPPCAsmBackend(const Target &T, uint8_t OSABI) : + PPCAsmBackend(T), OSABI(OSABI) { } + + void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, uint64_t Value) const { Value = adjustFixupValue(Fixup.getKind(), Value); if (!Value) return; // Doesn't change encoding. @@ -172,17 +164,12 @@ namespace { for (unsigned i = 0; i != 4; ++i) Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff); } - + MCObjectWriter *createObjectWriter(raw_ostream &OS) const { bool is64 = getPointerSize() == 8; - return createELFObjectWriter(new PPCELFObjectWriter( - /*Is64Bit=*/is64, - OSType, - is64 ? ELF::EM_PPC64 : ELF::EM_PPC, - /*addend*/ true, /*isLittleEndian*/ false), - OS, /*IsLittleEndian=*/false); + return createPPCELFObjectWriter(OS, is64, OSABI); } - + virtual bool doesSectionRequireSymbols(const MCSection &Section) const { return false; } @@ -197,5 +184,6 @@ MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, StringRef TT) { if (Triple(TT).isOSDarwin()) return new DarwinPPCAsmBackend(T); - return new ELFPPCAsmBackend(T, Triple(TT).getOS()); + uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); + return new ELFPPCAsmBackend(T, OSABI); } diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h b/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h index 369bbdc..9c975c0 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h +++ b/lib/Target/PowerPC/MCTargetDesc/PPCBaseInfo.h @@ -1,4 +1,4 @@ -//===-- PPCBaseInfo.h - Top level definitions for PPC -------- --*- C++ -*-===// +//===-- PPCBaseInfo.h - Top level definitions for PPC -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp new file mode 100644 index 0000000..a197981 --- /dev/null +++ b/lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp @@ -0,0 +1,103 @@ +//===-- PPCELFObjectWriter.cpp - PPC ELF Writer ---------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "MCTargetDesc/PPCFixupKinds.h" +#include "MCTargetDesc/PPCMCTargetDesc.h" +#include "llvm/MC/MCELFObjectWriter.h" +#include "llvm/Support/ErrorHandling.h" + +using namespace llvm; + +namespace { + class PPCELFObjectWriter : public MCELFObjectTargetWriter { + public: + PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI); + + virtual ~PPCELFObjectWriter(); + protected: + virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, + bool IsPCRel, bool IsRelocWithSymbol, + int64_t Addend) const; + virtual void adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset); + }; +} + +PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI) + : MCELFObjectTargetWriter(Is64Bit, OSABI, + Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC, + /*HasRelocationAddend*/ true) {} + +PPCELFObjectWriter::~PPCELFObjectWriter() { +} + +unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target, + const MCFixup &Fixup, + bool IsPCRel, + bool IsRelocWithSymbol, + int64_t Addend) const { + // determine the type of the relocation + unsigned Type; + if (IsPCRel) { + switch ((unsigned)Fixup.getKind()) { + default: + llvm_unreachable("Unimplemented"); + case PPC::fixup_ppc_br24: + Type = ELF::R_PPC_REL24; + break; + case FK_PCRel_4: + Type = ELF::R_PPC_REL32; + break; + } + } else { + switch ((unsigned)Fixup.getKind()) { + default: llvm_unreachable("invalid fixup kind!"); + case PPC::fixup_ppc_br24: + Type = ELF::R_PPC_ADDR24; + break; + case PPC::fixup_ppc_brcond14: + Type = ELF::R_PPC_ADDR14_BRTAKEN; // XXX: or BRNTAKEN?_ + break; + case PPC::fixup_ppc_ha16: + Type = ELF::R_PPC_ADDR16_HA; + break; + case PPC::fixup_ppc_lo16: + Type = ELF::R_PPC_ADDR16_LO; + break; + case PPC::fixup_ppc_lo14: + Type = ELF::R_PPC_ADDR14; + break; + case FK_Data_4: + Type = ELF::R_PPC_ADDR32; + break; + case FK_Data_2: + Type = ELF::R_PPC_ADDR16; + break; + } + } + return Type; +} + +void PPCELFObjectWriter:: +adjustFixupOffset(const MCFixup &Fixup, uint64_t &RelocOffset) { + switch ((unsigned)Fixup.getKind()) { + case PPC::fixup_ppc_ha16: + case PPC::fixup_ppc_lo16: + RelocOffset += 2; + break; + default: + break; + } +} + +MCObjectWriter *llvm::createPPCELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI) { + MCELFObjectTargetWriter *MOTW = new PPCELFObjectWriter(Is64Bit, OSABI); + return createELFObjectWriter(MOTW, OS, /*IsLittleEndian=*/false); +} diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp index e9424d8..245b457 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -1,4 +1,4 @@ -//===-- PPCMCAsmInfo.cpp - PPC asm properties -------------------*- C++ -*-===// +//===-- PPCMCAsmInfo.cpp - PPC asm properties -----------------------------===// // // The LLVM Compiler Infrastructure // @@ -14,6 +14,8 @@ #include "PPCMCAsmInfo.h" using namespace llvm; +void PPCMCAsmInfoDarwin::anchor() { } + PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit) { if (is64Bit) PointerSize = 8; @@ -30,6 +32,8 @@ PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit) { SupportsDebugInformation= true; // Debug information. } +void PPCLinuxMCAsmInfo::anchor() { } + PPCLinuxMCAsmInfo::PPCLinuxMCAsmInfo(bool is64Bit) { if (is64Bit) PointerSize = 8; diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h index 96ae6fb..7b4ed9f 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -1,4 +1,4 @@ -//=====-- PPCMCAsmInfo.h - PPC asm properties -----------------*- C++ -*--====// +//===-- PPCMCAsmInfo.h - PPC asm properties --------------------*- C++ -*--===// // // The LLVM Compiler Infrastructure // @@ -18,11 +18,15 @@ namespace llvm { - struct PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { + class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { + virtual void anchor(); + public: explicit PPCMCAsmInfoDarwin(bool is64Bit); }; - struct PPCLinuxMCAsmInfo : public MCAsmInfo { + class PPCLinuxMCAsmInfo : public MCAsmInfo { + virtual void anchor(); + public: explicit PPCLinuxMCAsmInfo(bool is64Bit); }; diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 262f97c..5a6827f 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -57,7 +57,7 @@ public: // getBinaryCodeForInstr - TableGen'erated function for getting the // binary encoding for an instruction. - unsigned getBinaryCodeForInstr(const MCInst &MI, + uint64_t getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups) const; void EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 7c47051..226fbfe 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -1,4 +1,4 @@ -//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -------*- C++ -*-===// +//===-- PPCMCTargetDesc.cpp - PowerPC Target Descriptions -----------------===// // // The LLVM Compiler Infrastructure // @@ -20,6 +20,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #define GET_INSTRINFO_MC_DESC @@ -107,8 +108,9 @@ static MCStreamer *createMCStreamer(const Target &T, StringRef TT, static MCInstPrinter *createPPCMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, + const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) { - return new PPCInstPrinter(MAI, SyntaxVariant); + return new PPCInstPrinter(MAI, MRI, SyntaxVariant); } extern "C" void LLVMInitializePowerPCTargetMC() { diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h index e5bf2a9..b7fa064 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -14,14 +14,18 @@ #ifndef PPCMCTARGETDESC_H #define PPCMCTARGETDESC_H +#include "llvm/Support/DataTypes.h" + namespace llvm { class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; +class MCObjectWriter; class MCSubtargetInfo; class Target; class StringRef; +class raw_ostream; extern Target ThePPC32Target; extern Target ThePPC64Target; @@ -31,7 +35,11 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx); MCAsmBackend *createPPCAsmBackend(const Target &T, StringRef TT); - + +/// createPPCELFObjectWriter - Construct an PPC ELF object writer. +MCObjectWriter *createPPCELFObjectWriter(raw_ostream &OS, + bool Is64Bit, + uint8_t OSABI); } // End llvm namespace // Defines symbolic names for PowerPC registers. This defines a mapping from diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 367f9cc..724374c 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -1,10 +1,10 @@ -//===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===// -// +//===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This is the top level entry point for the PowerPC target. diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp index 5dc2d3d..591ae02 100644 --- a/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -1,4 +1,4 @@ -//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly --------=// +//===-- PPCAsmPrinter.cpp - Print machine instrs to PowerPC assembly ------===// // // The LLVM Compiler Infrastructure // @@ -39,6 +39,7 @@ #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/MCSectionELF.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -49,6 +50,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/Support/ELF.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/SmallString.h" #include "InstPrinter/PPCInstPrinter.h" @@ -391,14 +393,26 @@ void PPCLinuxAsmPrinter::EmitFunctionEntryLabel() { return AsmPrinter::EmitFunctionEntryLabel(); // Emit an official procedure descriptor. - // FIXME 64-bit SVR4: Use MCSection here! - OutStreamer.EmitRawText(StringRef("\t.section\t\".opd\",\"aw\"")); - OutStreamer.EmitRawText(StringRef("\t.align 3")); + const MCSection *Current = OutStreamer.getCurrentSection(); + const MCSectionELF *Section = OutStreamer.getContext().getELFSection(".opd", + ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC, + SectionKind::getReadOnly()); + OutStreamer.SwitchSection(Section); OutStreamer.EmitLabel(CurrentFnSym); - OutStreamer.EmitRawText("\t.quad .L." + Twine(CurrentFnSym->getName()) + - ",.TOC.@tocbase"); - OutStreamer.EmitRawText(StringRef("\t.previous")); - OutStreamer.EmitRawText(".L." + Twine(CurrentFnSym->getName()) + ":"); + OutStreamer.EmitValueToAlignment(8); + MCSymbol *Symbol1 = + OutContext.GetOrCreateSymbol(".L." + Twine(CurrentFnSym->getName())); + MCSymbol *Symbol2 = OutContext.GetOrCreateSymbol(StringRef(".TOC.@tocbase")); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(Symbol1, OutContext), + Subtarget.isPPC64() ? 8 : 4/*size*/, 0/*addrspace*/); + OutStreamer.EmitValue(MCSymbolRefExpr::Create(Symbol2, OutContext), + Subtarget.isPPC64() ? 8 : 4/*size*/, 0/*addrspace*/); + OutStreamer.SwitchSection(Current); + + MCSymbol *RealFnSym = OutContext.GetOrCreateSymbol( + ".L." + Twine(CurrentFnSym->getName())); + OutStreamer.EmitLabel(RealFnSym); + CurrentFnSymForSize = RealFnSym; } @@ -408,8 +422,10 @@ bool PPCLinuxAsmPrinter::doFinalization(Module &M) { bool isPPC64 = TD->getPointerSizeInBits() == 64; if (isPPC64 && !TOC.empty()) { - // FIXME 64-bit SVR4: Use MCSection here? - OutStreamer.EmitRawText(StringRef("\t.section\t\".toc\",\"aw\"")); + const MCSectionELF *Section = OutStreamer.getContext().getELFSection(".toc", + ELF::SHT_PROGBITS, ELF::SHF_WRITE | ELF::SHF_ALLOC, + SectionKind::getReadOnly()); + OutStreamer.SwitchSection(Section); // FIXME: This is nondeterminstic! for (DenseMap<MCSymbol*, MCSymbol*>::iterator I = TOC.begin(), diff --git a/lib/Target/PowerPC/PPCBranchSelector.cpp b/lib/Target/PowerPC/PPCBranchSelector.cpp index 475edf3..5f775e1 100644 --- a/lib/Target/PowerPC/PPCBranchSelector.cpp +++ b/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -1,4 +1,4 @@ -//===-- PPCBranchSelector.cpp - Emit long conditional branches-----*- C++ -*-=// +//===-- PPCBranchSelector.cpp - Emit long conditional branches ------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 441db94..8efc9c1 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -1,10 +1,10 @@ //===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This describes the calling conventions for the PowerPC 32- and 64-bit diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp index 9d2f4d0..252a2d1 100644 --- a/lib/Target/PowerPC/PPCCodeEmitter.cpp +++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp @@ -1,4 +1,4 @@ -//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC32 -------*- C++ -*-=// +//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===// // // The LLVM Compiler Infrastructure // @@ -50,7 +50,7 @@ namespace { /// getBinaryCodeForInstr - This function, generated by the /// CodeEmitterGenerator using TableGen, produces the binary encoding for /// machine instructions. - unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; + uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; MachineRelocation GetRelocation(const MachineOperand &MO, diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp index 5c45018..6d612f7 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1,4 +1,4 @@ -//=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===// +//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// // // The LLVM Compiler Infrastructure // @@ -367,8 +367,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { .addReg(PPC::R0, RegState::Kill) .addImm(NegFrameSize); BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) - .addReg(PPC::R1) - .addReg(PPC::R1) + .addReg(PPC::R1, RegState::Kill) + .addReg(PPC::R1, RegState::Define) .addReg(PPC::R0); } else if (isInt<16>(NegFrameSize)) { BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) @@ -382,8 +382,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { .addReg(PPC::R0, RegState::Kill) .addImm(NegFrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) - .addReg(PPC::R1) - .addReg(PPC::R1) + .addReg(PPC::R1, RegState::Kill) + .addReg(PPC::R1, RegState::Define) .addReg(PPC::R0); } } else { // PPC64. @@ -400,8 +400,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { .addReg(PPC::X0) .addImm(NegFrameSize); BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) - .addReg(PPC::X1) - .addReg(PPC::X1) + .addReg(PPC::X1, RegState::Kill) + .addReg(PPC::X1, RegState::Define) .addReg(PPC::X0); } else if (isInt<16>(NegFrameSize)) { BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) @@ -415,8 +415,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { .addReg(PPC::X0, RegState::Kill) .addImm(NegFrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) - .addReg(PPC::X1) - .addReg(PPC::X1) + .addReg(PPC::X1, RegState::Kill) + .addReg(PPC::X1, RegState::Define) .addReg(PPC::X0); } } diff --git a/lib/Target/PowerPC/PPCFrameLowering.h b/lib/Target/PowerPC/PPCFrameLowering.h index 20faa71..d708541 100644 --- a/lib/Target/PowerPC/PPCFrameLowering.h +++ b/lib/Target/PowerPC/PPCFrameLowering.h @@ -1,4 +1,4 @@ -//==-- PPCFrameLowering.h - Define frame lowering for PowerPC ----*- C++ -*-==// +//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 4a509a3..6651d14 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -602,7 +602,6 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { case ISD::SETULT: return 0; case ISD::SETUGT: return 1; } - return 0; } SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) { diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index f3a3d17..bfed7ba 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -17,7 +17,6 @@ #include "PPCTargetMachine.h" #include "MCTargetDesc/PPCPredicates.h" #include "llvm/ADT/STLExtras.h" -#include "llvm/ADT/VectorExtras.h" #include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -1428,8 +1427,9 @@ SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) std::pair<SDValue, SDValue> CallResult = LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), - false, false, false, false, 0, CallingConv::C, false, - /*isReturnValueUsed=*/true, + false, false, false, false, 0, CallingConv::C, + /*isTailCall=*/false, + /*doesNotRet=*/false, /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__trampoline_setup", PtrVT), Args, DAG, dl); @@ -1699,7 +1699,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4( // Arguments stored in registers. if (VA.isRegLoc()) { - TargetRegisterClass *RC; + const TargetRegisterClass *RC; EVT ValVT = VA.getValVT(); switch (ValVT.getSimpleVT().SimpleTy) { @@ -1915,12 +1915,11 @@ PPCTargetLowering::LowerFormalArguments_Darwin( for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { EVT ObjectVT = Ins[ArgNo].VT; - unsigned ObjSize = ObjectVT.getSizeInBits()/8; ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; if (Flags.isByVal()) { // ObjSize is the true size, ArgSize rounded up to multiple of regs. - ObjSize = Flags.getByValSize(); + unsigned ObjSize = Flags.getByValSize(); unsigned ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; VecArgOffset += ArgSize; @@ -2840,7 +2839,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl, SDValue PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, - bool &isTailCall, + bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -4259,8 +4258,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, // Check to see if this is a shuffle of 4-byte values. If so, we can use our // perfect shuffle table to emit an optimal matching sequence. - SmallVector<int, 16> PermMask; - SVOp->getMask(PermMask); + ArrayRef<int> PermMask = SVOp->getMask(); unsigned PFIndexes[4]; bool isFourElementShuffle = true; @@ -4572,7 +4570,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); } - return SDValue(); } void PPCTargetLowering::ReplaceNodeResults(SDNode *N, @@ -4582,8 +4579,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: - assert(false && "Do not know how to custom type legalize this operation!"); - return; + llvm_unreachable("Do not know how to custom type legalize this operation!"); case ISD::VAARG: { if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI() || TM.getSubtarget<PPCSubtarget>().isPPC64()) diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index 942f5ee..3534e9c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -437,8 +437,8 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; virtual SDValue - LowerCall(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, + LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, + bool isVarArg, bool doesNotRet, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, @@ -472,21 +472,21 @@ namespace llvm { SmallVectorImpl<SDValue> &InVals) const; SDValue - LowerCall_Darwin(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, bool isTailCall, + LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, + bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const; SDValue - LowerCall_SVR4(SDValue Chain, SDValue Callee, - CallingConv::ID CallConv, bool isVarArg, bool isTailCall, - const SmallVectorImpl<ISD::OutputArg> &Outs, - const SmallVectorImpl<SDValue> &OutVals, - const SmallVectorImpl<ISD::InputArg> &Ins, - DebugLoc dl, SelectionDAG &DAG, - SmallVectorImpl<SDValue> &InVals) const; + LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, + bool isVarArg, bool isTailCall, + const SmallVectorImpl<ISD::OutputArg> &Outs, + const SmallVectorImpl<SDValue> &OutVals, + const SmallVectorImpl<ISD::InputArg> &Ins, + DebugLoc dl, SelectionDAG &DAG, + SmallVectorImpl<SDValue> &InVals) const; }; } diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index cdbc264..02bffed 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -1,10 +1,10 @@ -//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// -// +//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the PowerPC 64-bit instructions. These patterns are used @@ -106,7 +106,7 @@ let isCall = 1, PPC970_Unit = 7, (outs), (ins aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; } - let Uses = [CTR8, RM] in { + let Uses = [X11, CTR8, RM] in { def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins variable_ops), "bctrl", BrB, @@ -575,7 +575,8 @@ def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), "", [(set G8RC:$rD, (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; - + +let hasSideEffects = 1 in { let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), "ld 2, 8($reg)", LdStLD, @@ -585,6 +586,7 @@ let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), "ld 2, 40(1)", LdStLD, [(PPCtoc_restore)]>, isPPC64; +} def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 256370f..707fa41 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1,10 +1,10 @@ -//===- PPCInstrAltivec.td - The PowerPC Altivec Extension --*- tablegen -*-===// -// +//===-- PPCInstrAltivec.td - The PowerPC Altivec Extension -*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the Altivec extension to the PowerPC instruction set. diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 84a15b1..d332e2a 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -1,10 +1,10 @@ //===- PowerPCInstrFormats.td - PowerPC Instruction Formats --*- tablegen -*-=// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 6d16f1d..7a8ec40 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1,4 +1,4 @@ -//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===// +//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index e90f8cb..e5f171d 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -1,4 +1,4 @@ -//===- PPCInstrInfo.h - PowerPC Instruction Information ---------*- C++ -*-===// +//===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef POWERPC32_INSTRUCTIONINFO_H -#define POWERPC32_INSTRUCTIONINFO_H +#ifndef POWERPC_INSTRUCTIONINFO_H +#define POWERPC_INSTRUCTIONINFO_H #include "PPC.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index d4c9d10..e234012 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1,10 +1,10 @@ -//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===// -// +//===-- PPCInstrInfo.td - The PowerPC Instruction Set ------*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the subset of the 32-bit PowerPC instruction set, as used diff --git a/lib/Target/PowerPC/PPCJITInfo.h b/lib/Target/PowerPC/PPCJITInfo.h index 47ead59..2f8243a 100644 --- a/lib/Target/PowerPC/PPCJITInfo.h +++ b/lib/Target/PowerPC/PPCJITInfo.h @@ -1,4 +1,4 @@ -//===- PPCJITInfo.h - PowerPC impl. of the JIT interface --------*- C++ -*-===// +//===-- PPCJITInfo.h - PowerPC impl. of the JIT interface -------*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCMCInstLower.cpp b/lib/Target/PowerPC/PPCMCInstLower.cpp index 33af426..276edcb 100644 --- a/lib/Target/PowerPC/PPCMCInstLower.cpp +++ b/lib/Target/PowerPC/PPCMCInstLower.cpp @@ -140,7 +140,7 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, switch (MO.getType()) { default: MI->dump(); - assert(0 && "unknown operand type"); + llvm_unreachable("unknown operand type"); case MachineOperand::MO_Register: assert(!MO.getSubReg() && "Subregs should be eliminated!"); MCOp = MCOperand::CreateReg(MO.getReg()); @@ -166,6 +166,8 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP, isDarwin); break; + case MachineOperand::MO_RegisterMask: + continue; } OutMI.addOperand(MCOp); diff --git a/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp b/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp new file mode 100644 index 0000000..6a0aec8 --- /dev/null +++ b/lib/Target/PowerPC/PPCMachineFunctionInfo.cpp @@ -0,0 +1,15 @@ +//===-- PPCMachineFunctionInfo.cpp - Private data used for PowerPC --------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "PPCMachineFunctionInfo.h" + +using namespace llvm; + +void PPCFunctionInfo::anchor() { } + diff --git a/lib/Target/PowerPC/PPCMachineFunctionInfo.h b/lib/Target/PowerPC/PPCMachineFunctionInfo.h index e2649c8..24caffa 100644 --- a/lib/Target/PowerPC/PPCMachineFunctionInfo.h +++ b/lib/Target/PowerPC/PPCMachineFunctionInfo.h @@ -21,7 +21,8 @@ namespace llvm { /// PPCFunctionInfo - This class is derived from MachineFunction private /// PowerPC target-specific information for each MachineFunction. class PPCFunctionInfo : public MachineFunctionInfo { -private: + virtual void anchor(); + /// FramePointerSaveIndex - Frame index of where the old frame pointer is /// stored. Also used as an anchor for instructions that need to be altered /// when using frame pointers (dyna_add, dyna_sub.) diff --git a/lib/Target/PowerPC/PPCPerfectShuffle.h b/lib/Target/PowerPC/PPCPerfectShuffle.h index 3164e33..17b836d 100644 --- a/lib/Target/PowerPC/PPCPerfectShuffle.h +++ b/lib/Target/PowerPC/PPCPerfectShuffle.h @@ -1,4 +1,4 @@ -//===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table ---------------===// +//===-- PPCPerfectShuffle.h - Altivec Perfect Shuffle Table -----*- C++ -*-===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 27f7f4a..306cc1f 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1,4 +1,4 @@ -//===- PPCRegisterInfo.cpp - PowerPC Register Information -------*- C++ -*-===// +//===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// // // The LLVM Compiler Infrastructure // @@ -98,10 +98,10 @@ PPCRegisterInfo::getPointerRegClass(unsigned Kind) const { return &PPC::GPRCRegClass; } -const unsigned* +const uint16_t* PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // 32-bit Darwin calling convention. - static const unsigned Darwin32_CalleeSavedRegs[] = { + static const uint16_t Darwin32_CalleeSavedRegs[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, @@ -123,7 +123,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { }; // 32-bit SVR4 calling convention. - static const unsigned SVR4_CalleeSavedRegs[] = { + static const uint16_t SVR4_CalleeSavedRegs[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, @@ -147,7 +147,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 0 }; // 64-bit Darwin calling convention. - static const unsigned Darwin64_CalleeSavedRegs[] = { + static const uint16_t Darwin64_CalleeSavedRegs[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, @@ -169,7 +169,7 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { }; // 64-bit SVR4 calling convention. - static const unsigned SVR4_64_CalleeSavedRegs[] = { + static const uint16_t SVR4_64_CalleeSavedRegs[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, @@ -299,8 +299,9 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, DebugLoc dl = MI->getDebugLoc(); if (isInt<16>(CalleeAmt)) { - BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg). - addImm(CalleeAmt); + BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) + .addReg(StackReg, RegState::Kill) + .addImm(CalleeAmt); } else { MachineBasicBlock::iterator MBBI = I; BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) @@ -308,9 +309,8 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) .addReg(TmpReg, RegState::Kill) .addImm(CalleeAmt & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) - .addReg(StackReg) - .addReg(StackReg) + BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) + .addReg(StackReg, RegState::Kill) .addReg(TmpReg); } } @@ -407,12 +407,12 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part. BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(Reg, RegState::Kill) - .addReg(PPC::X1) + .addReg(PPC::X1, RegState::Define) .addReg(MI.getOperand(1).getReg()); else BuildMI(MBB, II, dl, TII.get(PPC::STDUX)) .addReg(PPC::X0, RegState::Kill) - .addReg(PPC::X1) + .addReg(PPC::X1, RegState::Define) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) @@ -428,7 +428,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, } else { BuildMI(MBB, II, dl, TII.get(PPC::STWUX)) .addReg(Reg, RegState::Kill) - .addReg(PPC::R1) + .addReg(PPC::R1, RegState::Define) .addReg(MI.getOperand(1).getReg()); if (!MI.getOperand(1).isKill()) @@ -528,7 +528,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, if (DestReg != PPC::CR0) { unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4; // rlwinm r11, r11, 32-ShiftBits, 0, 31. - BuildMI(MBB, II, dl, TII.get(PPC::RLWINM), Reg) + BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) .addReg(Reg).addImm(32-ShiftBits).addImm(0) .addImm(31); } @@ -681,7 +681,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned StackReg = MI.getOperand(FIOperandNo).getReg(); MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); - MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false); + MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); } unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index faf690f..6ce90bc 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -1,4 +1,4 @@ -//===- PPCRegisterInfo.h - PowerPC Register Information Impl -----*- C++ -*-==// +//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -41,7 +41,7 @@ public: MachineFunction &MF) const; /// Code Generation virtual methods... - const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; + const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const; BitVector getReservedRegs(const MachineFunction &MF) const; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 1acdf4e..0e55313 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -1,10 +1,10 @@ -//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// -// +//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // diff --git a/lib/Target/PowerPC/PPCRelocations.h b/lib/Target/PowerPC/PPCRelocations.h index a33e7e0..0b392f9 100644 --- a/lib/Target/PowerPC/PPCRelocations.h +++ b/lib/Target/PowerPC/PPCRelocations.h @@ -1,4 +1,4 @@ -//===- PPCRelocations.h - PPC32 Code Relocations ----------------*- C++ -*-===// +//===-- PPCRelocations.h - PPC Code Relocations -----------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef PPC32RELOCATIONS_H -#define PPC32RELOCATIONS_H +#ifndef PPCRELOCATIONS_H +#define PPCRELOCATIONS_H #include "llvm/CodeGen/MachineRelocation.h" diff --git a/lib/Target/PowerPC/PPCSchedule.td b/lib/Target/PowerPC/PPCSchedule.td index 69e435b..4e37d0a 100644 --- a/lib/Target/PowerPC/PPCSchedule.td +++ b/lib/Target/PowerPC/PPCSchedule.td @@ -1,10 +1,10 @@ -//===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===// -// +//===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td index 94ee9bd..76f7465 100644 --- a/lib/Target/PowerPC/PPCSchedule440.td +++ b/lib/Target/PowerPC/PPCSchedule440.td @@ -1,10 +1,10 @@ -//===- PPCSchedule440.td - PPC 440 Scheduling Definitions --*- tablegen -*-===// -// +//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // Primary reference: diff --git a/lib/Target/PowerPC/PPCScheduleG3.td b/lib/Target/PowerPC/PPCScheduleG3.td index ad4da1f..e7e5498 100644 --- a/lib/Target/PowerPC/PPCScheduleG3.td +++ b/lib/Target/PowerPC/PPCScheduleG3.td @@ -1,10 +1,10 @@ -//===- PPCScheduleG3.td - PPC G3 Scheduling Definitions ----*- tablegen -*-===// -// +//===-- PPCScheduleG3.td - PPC G3 Scheduling Definitions ---*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the G3 (750) processor. diff --git a/lib/Target/PowerPC/PPCScheduleG4.td b/lib/Target/PowerPC/PPCScheduleG4.td index 03c3b29..87a3151 100644 --- a/lib/Target/PowerPC/PPCScheduleG4.td +++ b/lib/Target/PowerPC/PPCScheduleG4.td @@ -1,10 +1,10 @@ -//===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===// -// +//===-- PPCScheduleG4.td - PPC G4 Scheduling Definitions ---*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the G4 (7400) processor. diff --git a/lib/Target/PowerPC/PPCScheduleG4Plus.td b/lib/Target/PowerPC/PPCScheduleG4Plus.td index 00cac3c..f76557a 100644 --- a/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -1,10 +1,10 @@ -//===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===// -// +//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the G4+ (7450) processor. diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td index 1671f22..bc0820b 100644 --- a/lib/Target/PowerPC/PPCScheduleG5.td +++ b/lib/Target/PowerPC/PPCScheduleG5.td @@ -1,10 +1,10 @@ -//===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===// -// +//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file defines the itinerary class data for the G5 (970) processor. diff --git a/lib/Target/PowerPC/PPCSubtarget.cpp b/lib/Target/PowerPC/PPCSubtarget.cpp index baa0eb5..c89fab3 100644 --- a/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/lib/Target/PowerPC/PPCSubtarget.cpp @@ -1,4 +1,4 @@ -//===- PowerPCSubtarget.cpp - PPC Subtarget Information -------------------===// +//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCSubtarget.h b/lib/Target/PowerPC/PPCSubtarget.h index 62b2424..69fe50b 100644 --- a/lib/Target/PowerPC/PPCSubtarget.h +++ b/lib/Target/PowerPC/PPCSubtarget.h @@ -1,4 +1,4 @@ -//=====-- PPCSubtarget.h - Define Subtarget for the PPC -------*- C++ -*--====// +//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===// // // The LLVM Compiler Infrastructure // diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp index 8e71c46..da20274 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -15,6 +15,7 @@ #include "PPCTargetMachine.h" #include "llvm/PassManager.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/CodeGen/Passes.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -22,7 +23,7 @@ using namespace llvm; extern "C" void LLVMInitializePowerPCTarget() { // Register the targets - RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); + RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target); RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target); } @@ -40,11 +41,9 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, InstrItins(Subtarget.getInstrItineraryData()) { } -/// Override this for PowerPC. Tail merging happily breaks up instruction issue -/// groups, which typically degrades performance. -bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } +void PPC32TargetMachine::anchor() { } -PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, +PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -52,8 +51,9 @@ PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT, : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { } +void PPC64TargetMachine::anchor() { } -PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, +PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -66,13 +66,39 @@ PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT, // Pass Pipeline Configuration //===----------------------------------------------------------------------===// -bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) { +namespace { +/// PPC Code Generator Pass Configuration Options. +class PPCPassConfig : public TargetPassConfig { +public: + PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + PPCTargetMachine &getPPCTargetMachine() const { + return getTM<PPCTargetMachine>(); + } + + virtual bool addInstSelector(); + virtual bool addPreEmitPass(); +}; +} // namespace + +TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) { + TargetPassConfig *PassConfig = new PPCPassConfig(this, PM); + + // Override this for PowerPC. Tail merging happily breaks up instruction issue + // groups, which typically degrades performance. + PassConfig->setEnableTailMerge(false); + + return PassConfig; +} + +bool PPCPassConfig::addInstSelector() { // Install an instruction selector. - PM.add(createPPCISelDag(*this)); + PM.add(createPPCISelDag(getPPCTargetMachine())); return false; } -bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) { +bool PPCPassConfig::addPreEmitPass() { // Must run branch selection immediately preceding the asm printer. PM.add(createPPCBranchSelectionPass()); return false; @@ -84,12 +110,12 @@ bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, if (Subtarget.isPPC64()) // Temporary workaround for the inability of PPC64 JIT to handle jump // tables. - Options.DisableJumpTables = true; - + Options.DisableJumpTables = true; + // Inform the subtarget that we are in JIT mode. FIXME: does this break macho // writing? Subtarget.SetJITMode(); - + // Machine code emitter pass for PowerPC. PM.add(createPPCJITCodeEmitterPass(*this, JCE)); diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h index 0427876..6dd11c9 100644 --- a/lib/Target/PowerPC/PPCTargetMachine.h +++ b/lib/Target/PowerPC/PPCTargetMachine.h @@ -1,4 +1,4 @@ -//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=// +//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -50,7 +50,7 @@ public: return &FrameLowering; } virtual PPCJITInfo *getJITInfo() { return &JITInfo; } - virtual const PPCTargetLowering *getTargetLowering() const { + virtual const PPCTargetLowering *getTargetLowering() const { return &TLInfo; } virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const { @@ -59,24 +59,23 @@ public: virtual const PPCRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } - + virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; } - virtual const InstrItineraryData *getInstrItineraryData() const { + virtual const InstrItineraryData *getInstrItineraryData() const { return &InstrItins; } // Pass Pipeline Configuration - virtual bool addInstSelector(PassManagerBase &PM); - virtual bool addPreEmitPass(PassManagerBase &PM); + virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE); - virtual bool getEnableTailMergeDefault() const; }; /// PPC32TargetMachine - PowerPC 32-bit target machine. /// class PPC32TargetMachine : public PPCTargetMachine { + virtual void anchor(); public: PPC32TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, @@ -87,6 +86,7 @@ public: /// PPC64TargetMachine - PowerPC 64-bit target machine. /// class PPC64TargetMachine : public PPCTargetMachine { + virtual void anchor(); public: PPC64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, |