diff options
Diffstat (limited to 'lib/Target/R600/AMDGPUSubtarget.h')
-rw-r--r-- | lib/Target/R600/AMDGPUSubtarget.h | 80 |
1 files changed, 65 insertions, 15 deletions
diff --git a/lib/Target/R600/AMDGPUSubtarget.h b/lib/Target/R600/AMDGPUSubtarget.h index 0c388b3..f71d80a 100644 --- a/lib/Target/R600/AMDGPUSubtarget.h +++ b/lib/Target/R600/AMDGPUSubtarget.h @@ -12,10 +12,15 @@ // //===----------------------------------------------------------------------===// -#ifndef AMDGPUSUBTARGET_H -#define AMDGPUSUBTARGET_H +#ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H +#define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H #include "AMDGPU.h" +#include "AMDGPUFrameLowering.h" #include "AMDGPUInstrInfo.h" +#include "AMDGPUIntrinsicInfo.h" +#include "AMDGPUSubtarget.h" +#include "R600ISelLowering.h" +#include "llvm/IR/DataLayout.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/Target/TargetSubtargetInfo.h" @@ -23,14 +28,10 @@ #define GET_SUBTARGETINFO_HEADER #include "AMDGPUGenSubtargetInfo.inc" -#define MAX_CB_SIZE (1 << 16) - namespace llvm { class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo { - std::unique_ptr<AMDGPUInstrInfo> InstrInfo; - public: enum Generation { R600 = 0, @@ -50,24 +51,43 @@ private: short TexVTXClauseSize; Generation Gen; bool FP64; + bool FP64Denormals; + bool FP32Denormals; bool CaymanISA; + bool FlatAddressSpace; bool EnableIRStructurizer; + bool EnablePromoteAlloca; bool EnableIfCvt; + bool EnableLoadStoreOpt; unsigned WavefrontSize; bool CFALUBug; int LocalMemorySize; + const DataLayout DL; + AMDGPUFrameLowering FrameLowering; + std::unique_ptr<AMDGPUTargetLowering> TLInfo; + std::unique_ptr<AMDGPUInstrInfo> InstrInfo; InstrItineraryData InstrItins; public: - AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS); + AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM); + AMDGPUSubtarget &initializeSubtargetDependencies(StringRef GPU, StringRef FS); - const AMDGPUInstrInfo *getInstrInfo() const { + const AMDGPUFrameLowering *getFrameLowering() const override { + return &FrameLowering; + } + const AMDGPUInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } - - const InstrItineraryData &getInstrItineraryData() const { - return InstrItins; + const AMDGPURegisterInfo *getRegisterInfo() const override { + return &InstrInfo->getRegisterInfo(); + } + AMDGPUTargetLowering *getTargetLowering() const override { + return TLInfo.get(); + } + const DataLayout *getDataLayout() const override { return &DL; } + const InstrItineraryData *getInstrItineraryData() const override { + return &InstrItins; } void ParseSubtargetFeatures(StringRef CPU, StringRef FS); @@ -81,7 +101,7 @@ public: } short getTexVTXClauseSize() const { - return TexVTXClauseSize; + return TexVTXClauseSize; } Generation getGeneration() const { @@ -96,6 +116,18 @@ public: return CaymanISA; } + bool hasFP32Denormals() const { + return FP32Denormals; + } + + bool hasFP64Denormals() const { + return FP64Denormals; + } + + bool hasFlatAddressSpace() const { + return FlatAddressSpace; + } + bool hasBFE() const { return (getGeneration() >= EVERGREEN); } @@ -112,8 +144,10 @@ public: if (Size == 32) return (getGeneration() >= EVERGREEN); - assert(Size == 64); - return (getGeneration() >= SOUTHERN_ISLANDS); + if (Size == 64) + return (getGeneration() >= SOUTHERN_ISLANDS); + + return false; } bool hasMulU24() const { @@ -125,14 +159,30 @@ public: hasCaymanISA()); } + bool hasFFBL() const { + return (getGeneration() >= EVERGREEN); + } + + bool hasFFBH() const { + return (getGeneration() >= EVERGREEN); + } + bool IsIRStructurizerEnabled() const { return EnableIRStructurizer; } + bool isPromoteAllocaEnabled() const { + return EnablePromoteAlloca; + } + bool isIfCvtEnabled() const { return EnableIfCvt; } + bool loadStoreOptEnabled() const { + return EnableLoadStoreOpt; + } + unsigned getWavefrontSize() const { return WavefrontSize; } @@ -171,4 +221,4 @@ public: } // End namespace llvm -#endif // AMDGPUSUBTARGET_H +#endif |