diff options
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.cpp')
-rw-r--r-- | lib/Target/R600/R600RegisterInfo.cpp | 44 |
1 files changed, 21 insertions, 23 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.cpp b/lib/Target/R600/R600RegisterInfo.cpp index a42043b..f3bb88b 100644 --- a/lib/Target/R600/R600RegisterInfo.cpp +++ b/lib/Target/R600/R600RegisterInfo.cpp @@ -28,6 +28,8 @@ R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm) BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); + const R600InstrInfo *TII = static_cast<const R600InstrInfo*>(TM.getInstrInfo()); + Reserved.set(AMDGPU::ZERO); Reserved.set(AMDGPU::HALF); Reserved.set(AMDGPU::ONE); @@ -41,26 +43,15 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { Reserved.set(AMDGPU::PRED_SEL_OFF); Reserved.set(AMDGPU::PRED_SEL_ZERO); Reserved.set(AMDGPU::PRED_SEL_ONE); + Reserved.set(AMDGPU::INDIRECT_BASE_ADDR); for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { Reserved.set(*I); } - for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(), - E = AMDGPU::TRegMemRegClass.end(); - I != E; ++I) { - Reserved.set(*I); - } + TII->reserveIndirectRegisters(Reserved, MF); - const R600InstrInfo *RII = - static_cast<const R600InstrInfo*>(TM.getInstrInfo()); - std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF); - for (std::vector<unsigned>::iterator I = IndirectRegs.begin(), - E = IndirectRegs.end(); - I != E; ++I) { - Reserved.set(*I); - } return Reserved; } @@ -78,6 +69,10 @@ unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; } +unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const { + return GET_REG_INDEX(getEncodingValue(Reg)); +} + const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( MVT VT) const { switch(VT.SimpleTy) { @@ -86,17 +81,20 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( } } -unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const { - switch (Channel) { - default: assert(!"Invalid channel index"); return 0; - case 0: return AMDGPU::sub0; - case 1: return AMDGPU::sub1; - case 2: return AMDGPU::sub2; - case 3: return AMDGPU::sub3; - } -} - const RegClassWeight &R600RegisterInfo::getRegClassWeight( const TargetRegisterClass *RC) const { return RCW; } + +bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const { + assert(!TargetRegisterInfo::isVirtualRegister(Reg)); + + switch (Reg) { + case AMDGPU::OQAP: + case AMDGPU::OQBP: + case AMDGPU::AR_X: + return false; + default: + return true; + } +} |