diff options
Diffstat (limited to 'lib/Target/R600/R600RegisterInfo.td')
| -rw-r--r-- | lib/Target/R600/R600RegisterInfo.td | 45 |
1 files changed, 11 insertions, 34 deletions
diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td index fa987cf..68bcd20 100644 --- a/lib/Target/R600/R600RegisterInfo.td +++ b/lib/Target/R600/R600RegisterInfo.td @@ -39,8 +39,6 @@ foreach Index = 0-127 in { // Indirect addressing offset registers def Addr#Index#_#Chan : R600RegWithChan <"T("#Index#" + AR.x)."#Chan, Index, Chan>; - def TRegMem#Index#_#Chan : R600RegWithChan <"T"#Index#"."#Chan, Index, - Chan>; } // 128-bit Temporary Registers def T#Index#_XYZW : R600Reg_128 <"T"#Index#"", @@ -95,6 +93,12 @@ foreach Index = 448-480 in { // Special Registers +def OQA : R600Reg<"OQA", 219>; +def OQB : R600Reg<"OQB", 220>; +def OQAP : R600Reg<"OQAP", 221>; +def OQBP : R600Reg<"OQAP", 222>; +def LDS_DIRECT_A : R600Reg<"LDS_DIRECT_A", 223>; +def LDS_DIRECT_B : R600Reg<"LDS_DIRECT_B", 224>; def ZERO : R600Reg<"0.0", 248>; def ONE : R600Reg<"1.0", 249>; def NEG_ONE : R600Reg<"-1.0", 249>; @@ -115,7 +119,6 @@ def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>; def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>; def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>; def AR_X : R600Reg<"AR.x", 0>; -def OQAP : R600Reg<"OQAP", 221>; def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "ArrayBase%u", 448, 480))>; @@ -130,7 +133,8 @@ let isAllocatable = 0 in { // XXX: Only use the X channel, until we support wider stack widths def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X", 0, 127))>; -} // End isAllocatable = 0 +def R600_LDS_SRC_REG : RegisterClass<"AMDGPU", [i32], 32, + (add OQA, OQB, OQAP, OQBP, LDS_DIRECT_A, LDS_DIRECT_B)>; def R600_KC0_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "KC0_%u_X", 128, 159))>; @@ -164,6 +168,8 @@ def R600_KC1 : RegisterClass <"AMDGPU", [f32, i32], 32, (interleave R600_KC1_X, R600_KC1_Y, R600_KC1_Z, R600_KC1_W)>; +} // End isAllocatable = 0 + def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, (add (sequence "T%u_X", 0, 127), AR_X)>; @@ -184,6 +190,7 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add R600_TReg32, R600_ArrayBase, R600_Addr, + R600_KC0, R600_KC1, ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF, ALU_CONST, ALU_PARAM, OQAP )>; @@ -201,33 +208,3 @@ def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, def R600_Reg64 : RegisterClass<"AMDGPU", [v2f32, v2i32], 64, (add (sequence "T%u_XY", 0, 63))>; - -//===----------------------------------------------------------------------===// -// Register classes for indirect addressing -//===----------------------------------------------------------------------===// - -// Super register for all the Indirect Registers. This register class is used -// by the REG_SEQUENCE instruction to specify the registers to use for direct -// reads / writes which may be written / read by an indirect address. -class IndirectSuper<string n, list<Register> subregs> : - RegisterWithSubRegs<n, subregs> { - let Namespace = "AMDGPU"; - let SubRegIndices = - [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, - sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15]; -} - -def IndirectSuperReg : IndirectSuper<"Indirect", - [TRegMem0_X, TRegMem1_X, TRegMem2_X, TRegMem3_X, TRegMem4_X, TRegMem5_X, - TRegMem6_X, TRegMem7_X, TRegMem8_X, TRegMem9_X, TRegMem10_X, TRegMem11_X, - TRegMem12_X, TRegMem13_X, TRegMem14_X, TRegMem15_X] ->; - -def IndirectReg : RegisterClass<"AMDGPU", [f32, i32], 32, (add IndirectSuperReg)>; - -// This register class defines the registers that are the storage units for -// the "Indirect Addressing" pseudo memory space. -// XXX: Only use the X channel, until we support wider stack widths -def TRegMem : RegisterClass<"AMDGPU", [f32, i32], 32, - (add (sequence "TRegMem%u_X", 0, 16)) ->; |