diff options
Diffstat (limited to 'lib/Target/Sparc/SparcInstr64Bit.td')
| -rw-r--r-- | lib/Target/Sparc/SparcInstr64Bit.td | 41 |
1 files changed, 33 insertions, 8 deletions
diff --git a/lib/Target/Sparc/SparcInstr64Bit.td b/lib/Target/Sparc/SparcInstr64Bit.td index 91805f9..47658ee 100644 --- a/lib/Target/Sparc/SparcInstr64Bit.td +++ b/lib/Target/Sparc/SparcInstr64Bit.td @@ -59,10 +59,6 @@ defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>; // preferable to use a constant pool load instead, depending on the // microarchitecture. -// The %g0 register is constant 0. -// This is useful for stx %g0, [...], for example. -def : Pat<(i64 0), (i64 G0)>, Requires<[Is64Bit]>; - // Single-instruction patterns. // The ALU instructions want their simm13 operands as i32 immediates. @@ -164,7 +160,7 @@ def : Pat<(sube i64:$a, i64:$b), (SUBXrr $a, $b)>; def : Pat<(addc i64:$a, i64:$b), (ADDCCrr $a, $b)>; def : Pat<(subc i64:$a, i64:$b), (SUBCCrr $a, $b)>; -def : Pat<(SPcmpicc i64:$a, i64:$b), (SUBCCrr $a, $b)>; +def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>; // Register-immediate instructions. @@ -175,7 +171,7 @@ def : Pat<(xor i64:$a, (i64 simm13:$b)), (XORri $a, (as_i32imm $b))>; def : Pat<(add i64:$a, (i64 simm13:$b)), (ADDri $a, (as_i32imm $b))>; def : Pat<(sub i64:$a, (i64 simm13:$b)), (SUBri $a, (as_i32imm $b))>; -def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (SUBCCri $a, (as_i32imm $b))>; +def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>; } // Predicates = [Is64Bit] @@ -243,6 +239,11 @@ def LDXri : F3_2<3, 0b001011, [(set i64:$dst, (load ADDRri:$addr))]>; // Extending loads to i64. +def : Pat<(i64 (zextloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; +def : Pat<(i64 (zextloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; +def : Pat<(i64 (extloadi1 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; +def : Pat<(i64 (extloadi1 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; + def : Pat<(i64 (zextloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; def : Pat<(i64 (zextloadi8 ADDRri:$addr)), (LDUBri ADDRri:$addr)>; def : Pat<(i64 (extloadi8 ADDRrr:$addr)), (LDUBrr ADDRrr:$addr)>; @@ -290,6 +291,10 @@ def : Pat<(truncstorei16 i64:$src, ADDRri:$addr), (STHri ADDRri:$addr, $src)>; def : Pat<(truncstorei32 i64:$src, ADDRrr:$addr), (STrr ADDRrr:$addr, $src)>; def : Pat<(truncstorei32 i64:$src, ADDRri:$addr), (STri ADDRri:$addr, $src)>; +// store 0, addr -> store %g0, addr +def : Pat<(store (i64 0), ADDRrr:$dst), (STXrr ADDRrr:$dst, (i64 G0))>; +def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>; + } // Predicates = [Is64Bit] @@ -308,7 +313,7 @@ let Predicates = [Is64Bit] in { let Uses = [ICC] in def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), - "bp$cc %xcc, $dst", + "b$cc %xcc, $dst", [(SPbrxcc bb:$dst, imm:$cc)]>; // Conditional moves on %xcc. @@ -322,7 +327,17 @@ def MOVXCCri : Pseudo<(outs IntRegs:$rd), (ins i32imm:$i, IntRegs:$f, CCOp:$cond), "mov$cond %xcc, $i, $rd", [(set i32:$rd, - (SPselecticc simm11:$i, i32:$f, imm:$cond))]>; + (SPselectxcc simm11:$i, i32:$f, imm:$cond))]>; +def FMOVS_XCC : Pseudo<(outs FPRegs:$rd), + (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond), + "fmovs$cond %xcc, $rs2, $rd", + [(set f32:$rd, + (SPselectxcc f32:$rs2, f32:$f, imm:$cond))]>; +def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd), + (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond), + "fmovd$cond %xcc, $rs2, $rd", + [(set f64:$rd, + (SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>; } // Uses, Constraints def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), @@ -330,4 +345,14 @@ def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond), def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond), (MOVXCCri (as_i32imm $t), $f, imm:$cond)>; +def : Pat<(SPselecticc i64:$t, i64:$f, imm:$cond), + (MOVICCrr $t, $f, imm:$cond)>; +def : Pat<(SPselecticc (i64 simm11:$t), i64:$f, imm:$cond), + (MOVICCri (as_i32imm $t), $f, imm:$cond)>; + +def : Pat<(SPselectfcc i64:$t, i64:$f, imm:$cond), + (MOVFCCrr $t, $f, imm:$cond)>; +def : Pat<(SPselectfcc (i64 simm11:$t), i64:$f, imm:$cond), + (MOVFCCri (as_i32imm $t), $f, imm:$cond)>; + } // Predicates = [Is64Bit] |