diff options
Diffstat (limited to 'lib/Target/Sparc')
38 files changed, 171 insertions, 926 deletions
diff --git a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp index 9df0054..d0b362c 100644 --- a/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ b/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -48,7 +48,7 @@ class SparcAsmParser : public MCTargetAsmParser { // public interface of the MCTargetAsmParser. bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - unsigned &ErrorInfo, + uint64_t &ErrorInfo, bool MatchingInlineAsm) override; bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, @@ -386,7 +386,7 @@ public: bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, - unsigned &ErrorInfo, + uint64_t &ErrorInfo, bool MatchingInlineAsm) { MCInst Inst; SmallVector<MCInst, 8> Instructions; @@ -408,7 +408,7 @@ bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_InvalidOperand: { SMLoc ErrorLoc = IDLoc; - if (ErrorInfo != ~0U) { + if (ErrorInfo != ~0ULL) { if (ErrorInfo >= Operands.size()) return Error(IDLoc, "too few operands for instruction"); @@ -444,7 +444,7 @@ ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) return Error(StartLoc, "invalid register name"); } -static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features, +static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID); bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info, diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt index cebda92..c486411 100644 --- a/lib/Target/Sparc/CMakeLists.txt +++ b/lib/Target/Sparc/CMakeLists.txt @@ -2,9 +2,8 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) tablegen(LLVM SparcGenRegisterInfo.inc -gen-register-info) tablegen(LLVM SparcGenInstrInfo.inc -gen-instr-info) -tablegen(LLVM SparcGenCodeEmitter.inc -gen-emitter) tablegen(LLVM SparcGenDisassemblerTables.inc -gen-disassembler) -tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter -mc-emitter) +tablegen(LLVM SparcGenMCCodeEmitter.inc -gen-emitter) tablegen(LLVM SparcGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM SparcGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM SparcGenDAGISel.inc -gen-dag-isel) @@ -24,8 +23,6 @@ add_llvm_target(SparcCodeGen SparcSubtarget.cpp SparcTargetMachine.cpp SparcSelectionDAGInfo.cpp - SparcJITInfo.cpp - SparcCodeEmitter.cpp SparcMCInstLower.cpp SparcTargetObjectFile.cpp ) diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp index f3441ff..28369fd 100644 --- a/lib/Target/Sparc/DelaySlotFiller.cpp +++ b/lib/Target/Sparc/DelaySlotFiller.cpp @@ -110,7 +110,7 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) { bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { bool Changed = false; - const TargetInstrInfo *TII = TM.getInstrInfo(); + const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) { MachineBasicBlock::iterator MI = I; @@ -187,7 +187,7 @@ Filler::findDelayInstr(MachineBasicBlock &MBB, if (J->getOpcode() == SP::RESTORErr || J->getOpcode() == SP::RESTOREri) { // change retl to ret. - slot->setDesc(TM.getInstrInfo()->get(SP::RET)); + slot->setDesc(TM.getSubtargetImpl()->getInstrInfo()->get(SP::RET)); return J; } } @@ -329,7 +329,8 @@ void Filler::insertDefsUses(MachineBasicBlock::iterator MI, bool Filler::IsRegInSet(SmallSet<unsigned, 32>& RegSet, unsigned Reg) { // Check Reg and all aliased Registers. - for (MCRegAliasIterator AI(Reg, TM.getRegisterInfo(), true); + for (MCRegAliasIterator AI(Reg, TM.getSubtargetImpl()->getRegisterInfo(), + true); AI.isValid(); ++AI) if (RegSet.count(*AI)) return true; @@ -482,7 +483,7 @@ bool Filler::tryCombineRestoreWithPrevInst(MachineBasicBlock &MBB, if (PrevInst->isBundledWithSucc()) return false; - const TargetInstrInfo *TII = TM.getInstrInfo(); + const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo(); switch (PrevInst->getOpcode()) { default: break; diff --git a/lib/Target/Sparc/Disassembler/LLVMBuild.txt b/lib/Target/Sparc/Disassembler/LLVMBuild.txt index c27398f..bd5397d 100644 --- a/lib/Target/Sparc/Disassembler/LLVMBuild.txt +++ b/lib/Target/Sparc/Disassembler/LLVMBuild.txt @@ -19,5 +19,5 @@ type = Library name = SparcDisassembler parent = Sparc -required_libraries = MC SparcInfo Support +required_libraries = MCDisassembler SparcInfo Support add_to_library_groups = Sparc diff --git a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp index 4df0990..8bc4ca9 100644 --- a/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp +++ b/lib/Target/Sparc/Disassembler/SparcDisassembler.cpp @@ -16,7 +16,6 @@ #include "SparcSubtarget.h" #include "llvm/MC/MCDisassembler.h" #include "llvm/MC/MCFixedLenDisassembler.h" -#include "llvm/Support/MemoryObject.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -27,23 +26,17 @@ typedef MCDisassembler::DecodeStatus DecodeStatus; namespace { -/// SparcDisassembler - a disassembler class for Sparc. +/// A disassembler class for Sparc. class SparcDisassembler : public MCDisassembler { public: - /// Constructor - Initializes the disassembler. - /// - SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : - MCDisassembler(STI, Ctx) - {} + SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) + : MCDisassembler(STI, Ctx) {} virtual ~SparcDisassembler() {} - /// getInstruction - See MCDisassembler. - DecodeStatus getInstruction(MCInst &instr, - uint64_t &size, - const MemoryObject ®ion, - uint64_t address, - raw_ostream &vStream, - raw_ostream &cStream) const override; + DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const override; }; } @@ -213,47 +206,37 @@ static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address, #include "SparcGenDisassemblerTables.inc" -/// readInstruction - read four bytes from the MemoryObject -/// and return 32 bit word. -static DecodeStatus readInstruction32(const MemoryObject ®ion, - uint64_t address, - uint64_t &size, - uint32_t &insn) { - uint8_t Bytes[4]; - +/// Read four bytes from the ArrayRef and return 32 bit word. +static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, + uint64_t &Size, uint32_t &Insn) { // We want to read exactly 4 Bytes of data. - if (region.readBytes(address, 4, Bytes) == -1) { - size = 0; + if (Bytes.size() < 4) { + Size = 0; return MCDisassembler::Fail; } // Encoded as a big-endian 32-bit word in the stream. - insn = (Bytes[3] << 0) | - (Bytes[2] << 8) | - (Bytes[1] << 16) | - (Bytes[0] << 24); + Insn = + (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24); return MCDisassembler::Success; } - -DecodeStatus -SparcDisassembler::getInstruction(MCInst &instr, - uint64_t &Size, - const MemoryObject &Region, - uint64_t Address, - raw_ostream &vStream, - raw_ostream &cStream) const { +DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, + ArrayRef<uint8_t> Bytes, + uint64_t Address, + raw_ostream &VStream, + raw_ostream &CStream) const { uint32_t Insn; - DecodeStatus Result = readInstruction32(Region, Address, Size, Insn); + DecodeStatus Result = readInstruction32(Bytes, Address, Size, Insn); if (Result == MCDisassembler::Fail) return MCDisassembler::Fail; // Calling the auto-generated decoder function. - Result = decodeInstruction(DecoderTableSparc32, instr, Insn, Address, - this, STI); + Result = + decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI); if (Result != MCDisassembler::Fail) { Size = 4; diff --git a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h index 8fe4075..c96d5ad 100644 --- a/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h +++ b/lib/Target/Sparc/InstPrinter/SparcInstPrinter.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SparcINSTPRINTER_H -#define SparcINSTPRINTER_H +#ifndef LLVM_LIB_TARGET_SPARC_INSTPRINTER_SPARCINSTPRINTER_H +#define LLVM_LIB_TARGET_SPARC_INSTPRINTER_SPARCINSTPRINTER_H #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCSubtargetInfo.h" diff --git a/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h b/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h index d42bcee..8d79396 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_SPARC_FIXUPKINDS_H -#define LLVM_SPARC_FIXUPKINDS_H +#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H +#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCFIXUPKINDS_H #include "llvm/MC/MCFixup.h" diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp index 6875fc6..3a9c987 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -35,7 +35,6 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { Data64bitsDirective = (isV9) ? "\t.xword\t" : nullptr; ZeroDirective = "\t.skip\t"; CommentString = "!"; - HasLEB128 = true; SupportsDebugInformation = true; ExceptionsType = ExceptionHandling::DwarfCFI; @@ -43,7 +42,8 @@ SparcELFMCAsmInfo::SparcELFMCAsmInfo(StringRef TT) { SunStyleELFSectionSwitchSyntax = true; UsesELFSectionDirectiveForBSS = true; - if (TheTriple.getOS() == llvm::Triple::Solaris) + if (TheTriple.getOS() == llvm::Triple::Solaris || + TheTriple.getOS() == llvm::Triple::OpenBSD) UseIntegratedAssembler = true; } diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h index e126b68..84de551 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCTARGETASMINFO_H -#define SPARCTARGETASMINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H +#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCASMINFO_H #include "llvm/MC/MCAsmInfoELF.h" diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp index 7f01ab0..d97e3a2 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp @@ -161,8 +161,9 @@ Sparc::Fixups SparcMCExpr::getFixupKind(SparcMCExpr::VariantKind Kind) { bool SparcMCExpr::EvaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout) const { - return getSubExpr()->EvaluateAsRelocatable(Res, Layout); + const MCAsmLayout *Layout, + const MCFixup *Fixup) const { + return getSubExpr()->EvaluateAsRelocatable(Res, Layout, Fixup); } static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) { diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h index f0d0ef3..f72c6c4 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_SPARCMCEXPR_H -#define LLVM_SPARCMCEXPR_H +#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCEXPR_H +#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCEXPR_H #include "SparcFixupKinds.h" #include "llvm/MC/MCExpr.h" @@ -87,7 +87,8 @@ public: /// @} void PrintImpl(raw_ostream &OS) const override; bool EvaluateAsRelocatableImpl(MCValue &Res, - const MCAsmLayout *Layout) const override; + const MCAsmLayout *Layout, + const MCFixup *Fixup) const override; void visitUsedExpr(MCStreamer &Streamer) const override; const MCSection *FindAssociatedSection() const override { return getSubExpr()->FindAssociatedSection(); diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp index 571017d..3cc4314 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -125,10 +125,8 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, static MCStreamer *createMCStreamer(const Target &T, StringRef TT, MCContext &Context, MCAsmBackend &MAB, raw_ostream &OS, MCCodeEmitter *Emitter, - const MCSubtargetInfo &STI, bool RelaxAll, - bool NoExecStack) { - MCStreamer *S = - createELFStreamer(Context, MAB, OS, Emitter, RelaxAll, NoExecStack); + const MCSubtargetInfo &STI, bool RelaxAll) { + MCStreamer *S = createELFStreamer(Context, MAB, OS, Emitter, RelaxAll); new SparcTargetELFStreamer(*S); return S; } diff --git a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h index c8029a8..c31943d 100644 --- a/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h +++ b/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCMCTARGETDESC_H -#define SPARCMCTARGETDESC_H +#ifndef LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H +#define LLVM_LIB_TARGET_SPARC_MCTARGETDESC_SPARCMCTARGETDESC_H #include "llvm/Support/DataTypes.h" diff --git a/lib/Target/Sparc/Makefile b/lib/Target/Sparc/Makefile index bcc0291..c2a95b4 100644 --- a/lib/Target/Sparc/Makefile +++ b/lib/Target/Sparc/Makefile @@ -16,7 +16,7 @@ BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \ SparcGenAsmWriter.inc SparcGenAsmMatcher.inc \ SparcGenDAGISel.inc SparcGenDisassemblerTables.inc \ SparcGenSubtargetInfo.inc SparcGenCallingConv.inc \ - SparcGenCodeEmitter.inc SparcGenMCCodeEmitter.inc + SparcGenMCCodeEmitter.inc DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt index 34e68cf..647c276 100644 --- a/lib/Target/Sparc/README.txt +++ b/lib/Target/Sparc/README.txt @@ -56,6 +56,4 @@ int %t1(int %a, int %b) { leaf fns. * Fill delay slots -* Implement JIT support - * Use %g0 directly to materialize 0. No instruction is required. diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h index de20aaa..96378d5 100644 --- a/lib/Target/Sparc/Sparc.h +++ b/lib/Target/Sparc/Sparc.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef TARGET_SPARC_H -#define TARGET_SPARC_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARC_H +#define LLVM_LIB_TARGET_SPARC_SPARC_H #include "MCTargetDesc/SparcMCTargetDesc.h" #include "llvm/Support/ErrorHandling.h" @@ -29,8 +29,6 @@ namespace llvm { FunctionPass *createSparcISelDag(SparcTargetMachine &TM); FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM); - FunctionPass *createSparcJITCodeEmitterPass(SparcTargetMachine &TM, - JITCodeEmitter &JCE); void LowerSparcMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp index 1b7330e..6432003 100644 --- a/lib/Target/Sparc/SparcAsmPrinter.cpp +++ b/lib/Target/Sparc/SparcAsmPrinter.cpp @@ -296,7 +296,7 @@ void SparcAsmPrinter::EmitFunctionBodyStart() { void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) { - const DataLayout *DL = TM.getDataLayout(); + const DataLayout *DL = TM.getSubtargetImpl()->getDataLayout(); const MachineOperand &MO = MI->getOperand (opNum); SparcMCExpr::VariantKind TF = (SparcMCExpr::VariantKind) MO.getTargetFlags(); @@ -450,7 +450,8 @@ void SparcAsmPrinter::EmitEndOfAsmFile(Module &M) { MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList(); if (!Stubs.empty()) { OutStreamer.SwitchSection(TLOFELF.getDataSection()); - unsigned PtrSize = TM.getDataLayout()->getPointerSize(0); + unsigned PtrSize = + TM.getSubtargetImpl()->getDataLayout()->getPointerSize(0); for (unsigned i = 0, e = Stubs.size(); i != e; ++i) { OutStreamer.EmitLabel(Stubs[i].first); OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(), PtrSize); diff --git a/lib/Target/Sparc/SparcCodeEmitter.cpp b/lib/Target/Sparc/SparcCodeEmitter.cpp deleted file mode 100644 index 247da2a..0000000 --- a/lib/Target/Sparc/SparcCodeEmitter.cpp +++ /dev/null @@ -1,280 +0,0 @@ -//===-- Sparc/SparcCodeEmitter.cpp - Convert Sparc Code to Machine Code ---===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===---------------------------------------------------------------------===// -// -// This file contains the pass that transforms the Sparc machine instructions -// into relocatable machine code. -// -//===---------------------------------------------------------------------===// - -#include "Sparc.h" -#include "MCTargetDesc/SparcMCExpr.h" -#include "SparcRelocations.h" -#include "SparcTargetMachine.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/CodeGen/JITCodeEmitter.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/Support/Debug.h" - -using namespace llvm; - -#define DEBUG_TYPE "jit" - -STATISTIC(NumEmitted, "Number of machine instructions emitted"); - -namespace { - -class SparcCodeEmitter : public MachineFunctionPass { - SparcJITInfo *JTI; - const SparcInstrInfo *II; - const DataLayout *TD; - const SparcSubtarget *Subtarget; - TargetMachine &TM; - JITCodeEmitter &MCE; - const std::vector<MachineConstantPoolEntry> *MCPEs; - bool IsPIC; - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired<MachineModuleInfo> (); - MachineFunctionPass::getAnalysisUsage(AU); - } - - static char ID; - -public: - SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) - : MachineFunctionPass(ID), JTI(nullptr), II(nullptr), TD(nullptr), - TM(tm), MCE(mce), MCPEs(nullptr), - IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} - - bool runOnMachineFunction(MachineFunction &MF) override; - - const char *getPassName() const override { - return "Sparc Machine Code Emitter"; - } - - /// getBinaryCodeForInstr - This function, generated by the - /// CodeEmitterGenerator using TableGen, produces the binary encoding for - /// machine instructions. - uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; - - void emitInstruction(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB); - -private: - /// getMachineOpValue - Return binary encoding of operand. If the machine - /// operand requires relocation, record the relocation and return zero. - unsigned getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) const; - - unsigned getCallTargetOpValue(const MachineInstr &MI, - unsigned) const; - unsigned getBranchTargetOpValue(const MachineInstr &MI, - unsigned) const; - unsigned getBranchPredTargetOpValue(const MachineInstr &MI, - unsigned) const; - unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI, - unsigned) const; - - void emitWord(unsigned Word); - - unsigned getRelocation(const MachineInstr &MI, - const MachineOperand &MO) const; - - void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc) const; - void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; - void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; - void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const; -}; -} // end anonymous namespace. - -char SparcCodeEmitter::ID = 0; - -bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) { - SparcTargetMachine &Target = static_cast<SparcTargetMachine &>( - const_cast<TargetMachine &>(MF.getTarget())); - - JTI = Target.getJITInfo(); - II = Target.getInstrInfo(); - TD = Target.getDataLayout(); - Subtarget = &TM.getSubtarget<SparcSubtarget> (); - MCPEs = &MF.getConstantPool()->getConstants(); - JTI->Initialize(MF, IsPIC); - MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ()); - - do { - DEBUG(errs() << "JITTing function '" - << MF.getName() << "'\n"); - MCE.startFunction(MF); - - for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); - MBB != E; ++MBB){ - MCE.StartMachineBasicBlock(MBB); - for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(), - E = MBB->instr_end(); I != E;) - emitInstruction(*I++, *MBB); - } - } while (MCE.finishFunction(MF)); - - return false; -} - -void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI, - MachineBasicBlock &MBB) { - DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI); - - MCE.processDebugLoc(MI->getDebugLoc(), true); - - ++NumEmitted; - - switch (MI->getOpcode()) { - default: { - emitWord(getBinaryCodeForInstr(*MI)); - break; - } - case TargetOpcode::INLINEASM: { - // We allow inline assembler nodes with empty bodies - they can - // implicitly define registers, which is ok for JIT. - if (MI->getOperand(0).getSymbolName()[0]) { - report_fatal_error("JIT does not support inline asm!"); - } - break; - } - case TargetOpcode::CFI_INSTRUCTION: - break; - case TargetOpcode::EH_LABEL: { - MCE.emitLabel(MI->getOperand(0).getMCSymbol()); - break; - } - case TargetOpcode::IMPLICIT_DEF: - case TargetOpcode::KILL: { - // Do nothing. - break; - } - case SP::GETPCX: { - report_fatal_error("JIT does not support pseudo instruction GETPCX yet!"); - break; - } - } - - MCE.processDebugLoc(MI->getDebugLoc(), false); -} - -void SparcCodeEmitter::emitWord(unsigned Word) { - DEBUG(errs() << " 0x"; - errs().write_hex(Word) << "\n"); - MCE.emitWordBE(Word); -} - -/// getMachineOpValue - Return binary encoding of operand. If the machine -/// operand requires relocation, record the relocation and return zero. -unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI, - const MachineOperand &MO) const { - if (MO.isReg()) - return TM.getRegisterInfo()->getEncodingValue(MO.getReg()); - else if (MO.isImm()) - return static_cast<unsigned>(MO.getImm()); - else if (MO.isGlobal()) - emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO)); - else if (MO.isSymbol()) - emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO)); - else if (MO.isCPI()) - emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO)); - else if (MO.isMBB()) - emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO)); - else - llvm_unreachable("Unable to encode MachineOperand!"); - return 0; -} -unsigned SparcCodeEmitter::getCallTargetOpValue(const MachineInstr &MI, - unsigned opIdx) const { - const MachineOperand MO = MI.getOperand(opIdx); - return getMachineOpValue(MI, MO); -} - -unsigned SparcCodeEmitter::getBranchTargetOpValue(const MachineInstr &MI, - unsigned opIdx) const { - const MachineOperand MO = MI.getOperand(opIdx); - return getMachineOpValue(MI, MO); -} - -unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI, - unsigned opIdx) const { - const MachineOperand MO = MI.getOperand(opIdx); - return getMachineOpValue(MI, MO); -} - -unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI, - unsigned opIdx) const { - const MachineOperand MO = MI.getOperand(opIdx); - return getMachineOpValue(MI, MO); -} - -unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI, - const MachineOperand &MO) const { - - unsigned TF = MO.getTargetFlags(); - switch (TF) { - default: - case SparcMCExpr::VK_Sparc_None: break; - case SparcMCExpr::VK_Sparc_LO: return SP::reloc_sparc_lo; - case SparcMCExpr::VK_Sparc_HI: return SP::reloc_sparc_hi; - case SparcMCExpr::VK_Sparc_H44: return SP::reloc_sparc_h44; - case SparcMCExpr::VK_Sparc_M44: return SP::reloc_sparc_m44; - case SparcMCExpr::VK_Sparc_L44: return SP::reloc_sparc_l44; - case SparcMCExpr::VK_Sparc_HH: return SP::reloc_sparc_hh; - case SparcMCExpr::VK_Sparc_HM: return SP::reloc_sparc_hm; - } - - unsigned Opc = MI.getOpcode(); - switch (Opc) { - default: break; - case SP::CALL: return SP::reloc_sparc_pc30; - case SP::BA: - case SP::BCOND: - case SP::FBCOND: return SP::reloc_sparc_pc22; - case SP::BPXCC: return SP::reloc_sparc_pc19; - } - llvm_unreachable("unknown reloc!"); -} - -void SparcCodeEmitter::emitGlobalAddress(const GlobalValue *GV, - unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, - const_cast<GlobalValue *>(GV), 0, - true)); -} - -void SparcCodeEmitter:: -emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), - Reloc, ES, 0, 0)); -} - -void SparcCodeEmitter:: -emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), - Reloc, CPI, 0, false)); -} - -void SparcCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, - unsigned Reloc) const { - MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), - Reloc, BB)); -} - - -/// createSparcJITCodeEmitterPass - Return a pass that emits the collected Sparc -/// code to the specified MCE object. -FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM, - JITCodeEmitter &JCE) { - return new SparcCodeEmitter(TM, JCE); -} - -#include "SparcGenCodeEmitter.inc" diff --git a/lib/Target/Sparc/SparcFrameLowering.cpp b/lib/Target/Sparc/SparcFrameLowering.cpp index 3cdfda3..1b67b4b 100644 --- a/lib/Target/Sparc/SparcFrameLowering.cpp +++ b/lib/Target/Sparc/SparcFrameLowering.cpp @@ -46,7 +46,7 @@ void SparcFrameLowering::emitSPAdjustment(MachineFunction &MF, DebugLoc dl = (MBBI != MBB.end()) ? MBBI->getDebugLoc() : DebugLoc(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); if (NumBytes >= -4096 && NumBytes < 4096) { BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) @@ -88,7 +88,7 @@ void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); @@ -153,7 +153,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SparcInstrInfo &TII = - *static_cast<const SparcInstrInfo*>(MF.getTarget().getInstrInfo()); + *static_cast<const SparcInstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); assert(MBBI->getOpcode() == SP::RETL && "Can only put epilog before 'retl' instruction!"); diff --git a/lib/Target/Sparc/SparcFrameLowering.h b/lib/Target/Sparc/SparcFrameLowering.h index a7d1b89..9e53994 100644 --- a/lib/Target/Sparc/SparcFrameLowering.h +++ b/lib/Target/Sparc/SparcFrameLowering.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARC_FRAMEINFO_H -#define SPARC_FRAMEINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCFRAMELOWERING_H +#define LLVM_LIB_TARGET_SPARC_SPARCFRAMELOWERING_H #include "Sparc.h" #include "llvm/Target/TargetFrameLowering.h" diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 2fade27..b3b029e 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -66,16 +66,15 @@ private: } // end anonymous namespace SDNode* SparcDAGToDAGISel::getGlobalBaseReg() { - unsigned GlobalBaseReg = TM.getInstrInfo()->getGlobalBaseReg(MF); - return CurDAG->getRegister(GlobalBaseReg, - getTargetLowering()->getPointerTy()).getNode(); + unsigned GlobalBaseReg = + TM.getSubtargetImpl()->getInstrInfo()->getGlobalBaseReg(MF); + return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode(); } bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, SDValue &Base, SDValue &Offset) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), - getTargetLowering()->getPointerTy()); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy()); Offset = CurDAG->getTargetConstant(0, MVT::i32); return true; } @@ -90,8 +89,8 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr, if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { // Constant offset from frame ref. - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), - getTargetLowering()->getPointerTy()); + Base = + CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy()); } else { Base = Addr.getOperand(0); } @@ -135,7 +134,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) { } R1 = Addr; - R2 = CurDAG->getRegister(SP::G0, getTargetLowering()->getPointerTy()); + R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy()); return true; } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index 990f52a..e6a69d2 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -190,8 +190,8 @@ SparcTargetLowering::LowerReturn_32(SDValue Chain, SmallVector<CCValAssign, 16> RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - DAG.getTarget(), RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); // Analyze return values. CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); @@ -250,8 +250,8 @@ SparcTargetLowering::LowerReturn_64(SDValue Chain, SmallVector<CCValAssign, 16> RVLocs; // CCState - Info about the registers and stack slot. - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - DAG.getTarget(), RVLocs, *DAG.getContext()); + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); // Analyze return values. CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); @@ -349,8 +349,8 @@ LowerFormalArguments_32(SDValue Chain, // Assign locations to all of the incoming arguments. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); const unsigned StackOffset = 92; @@ -474,7 +474,7 @@ LowerFormalArguments_32(SDValue Chain, DAG.getConstant(Offset, MVT::i32)); Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, MachinePointerInfo(), - VA.getValVT(), false, false,0); + VA.getValVT(), false, false, false,0); Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); } InVals.push_back(Load); @@ -549,8 +549,8 @@ LowerFormalArguments_64(SDValue Chain, // Analyze arguments according to CC_Sparc64. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), - getTargetMachine(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); // The argument array begins at %fp+BIAS+128, after the register save area. @@ -698,8 +698,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), - DAG.getTarget(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); // Get the size of the outgoing arguments stack space requirement. @@ -915,7 +915,7 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // Add a register mask operand representing the call-preserved registers. const SparcRegisterInfo *TRI = - ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); + getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); const uint32_t *Mask = ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CallConv) : TRI->getCallPreservedMask(CallConv)); @@ -934,8 +934,8 @@ SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, // Assign locations to each value returned by this call. SmallVector<CCValAssign, 16> RVLocs; - CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), - DAG.getTarget(), RVLocs, *DAG.getContext()); + CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); @@ -1061,8 +1061,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Analyze operands of the call, assigning locations to each operand. SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), - DAG.getTarget(), ArgLocs, *DAG.getContext()); + CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); // Get the size of the outgoing arguments stack space requirement. @@ -1228,10 +1228,10 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Add a register mask operand representing the call-preserved registers. const SparcRegisterInfo *TRI = - ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); - const uint32_t *Mask = ((hasReturnsTwice) - ? TRI->getRTCallPreservedMask(CLI.CallConv) - : TRI->getCallPreservedMask(CLI.CallConv)); + getTargetMachine().getSubtarget<SparcSubtarget>().getRegisterInfo(); + const uint32_t *Mask = + ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv) + : TRI->getCallPreservedMask(CLI.CallConv)); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); @@ -1255,8 +1255,8 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, // Assign locations to each value returned by this call. SmallVector<CCValAssign, 16> RVLocs; - CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), - DAG.getTarget(), RVLocs, *DAG.getContext()); + CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs, + *DAG.getContext()); // Set inreg flag manually for codegen generated library calls that // return float. @@ -1366,7 +1366,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { } SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) - : TargetLowering(TM, new SparcELFTargetObjectFile()) { + : TargetLowering(TM) { Subtarget = &TM.getSubtarget<SparcSubtarget>(); // Set up the register classes. @@ -1905,7 +1905,9 @@ SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, Ops.push_back(Symbol); Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); const uint32_t *Mask = getTargetMachine() - .getRegisterInfo()->getCallPreservedMask(CallingConv::C); + .getSubtargetImpl() + ->getRegisterInfo() + ->getCallPreservedMask(CallingConv::C); assert(Mask && "Missing call preserved mask for calling convention"); Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(InFlag); @@ -2754,9 +2756,10 @@ static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, ISD::SETNE); } // MulResult is a node with an illegal type. Because such things are not - // generally permitted during this phase of legalization, delete the - // node. The above EXTRACT_ELEMENT nodes should have been folded. - DAG.DeleteNode(MulResult.getNode()); + // generally permitted during this phase of legalization, ensure that + // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have + // been folded. + assert(MulResult->use_empty() && "Illegally typed node still in use!"); SDValue Ops[2] = { BottomHalf, TopHalf } ; return DAG.getMergeValues(Ops, dl); @@ -2900,7 +2903,8 @@ MachineBasicBlock* SparcTargetLowering::expandSelectCC(MachineInstr *MI, MachineBasicBlock *BB, unsigned BROpcode) const { - const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); + const TargetInstrInfo &TII = + *getTargetMachine().getSubtargetImpl()->getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); @@ -2961,7 +2965,8 @@ SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, MachineBasicBlock *MBB, unsigned Opcode, unsigned CondCode) const { - const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); + const TargetInstrInfo &TII = + *getTargetMachine().getSubtargetImpl()->getInstrInfo(); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); DebugLoc DL = MI->getDebugLoc(); diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index a24cc82..a62d569 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -12,8 +12,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARC_ISELLOWERING_H -#define SPARC_ISELLOWERING_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H +#define LLVM_LIB_TARGET_SPARC_SPARCISELLOWERING_H #include "Sparc.h" #include "llvm/Target/TargetLowering.h" diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index 3a1472e..fe93ed7 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCINSTRUCTIONINFO_H -#define SPARCINSTRUCTIONINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H +#define LLVM_LIB_TARGET_SPARC_SPARCINSTRINFO_H #include "SparcRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 960261c..c320239 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -331,7 +331,7 @@ let hasSideEffects = 1, mayStore = 1 in { [(flushw)]>; } -let isBarrier = 1, isTerminator = 1, rd = 0b1000, rs1 = 0, simm13 = 5 in +let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; let rd = 0 in diff --git a/lib/Target/Sparc/SparcInstrVIS.td b/lib/Target/Sparc/SparcInstrVIS.td index 3e2b49d..d9adf3e 100644 --- a/lib/Target/Sparc/SparcInstrVIS.td +++ b/lib/Target/Sparc/SparcInstrVIS.td @@ -71,13 +71,13 @@ def FPACKFIX : VISInst2<0b000111101, "fpackfix">; def FEXPAND : VISInst2<0b001001101, "fexpand">; def FPMERGE : VISInst <0b001001011, "fpmerge">; -def FMUL8X16 : VISInst<0b00110001, "fmul8x16">; -def FMUL8X16AU : VISInst<0b00110011, "fmul8x16au">; -def FMUL8X16AL : VISInst<0b00110101, "fmul8x16al">; -def FMUL8SUX16 : VISInst<0b00110110, "fmul8sux16">; -def FMUL8ULX16 : VISInst<0b00110111, "fmul8ulx16">; -def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">; -def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">; +def FMUL8X16 : VISInst<0b000110001, "fmul8x16">; +def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">; +def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">; +def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">; +def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">; +def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">; +def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">; def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>; def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>; @@ -134,7 +134,7 @@ def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>; def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>; def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>; -def PDIST : VISInst<0b00111110, "pdist">; +def PDIST : VISInst<0b000111110, "pdist">; def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>; def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>; @@ -181,7 +181,7 @@ def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2), } -def FCHKSM16 : VISInst<0b01000100, "fchksm16">; +def FCHKSM16 : VISInst<0b001000100, "fchksm16">; def FHADDS : F3_3<0b10, 0b110100, 0b001100001, (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), @@ -229,14 +229,14 @@ def FNSMULD : F3_3<0b10, 0b110100, 0b001111001, def FPADD64 : VISInst<0b001000010, "fpadd64">; -def FSLL16 : VISInst<0b00100001, "fsll16">; -def FSRL16 : VISInst<0b00100011, "fsrl16">; -def FSLL32 : VISInst<0b00100101, "fsll32">; -def FSRL32 : VISInst<0b00100111, "fsrl32">; -def FSLAS16 : VISInst<0b00101001, "fslas16">; -def FSRA16 : VISInst<0b00101011, "fsra16">; -def FSLAS32 : VISInst<0b00101101, "fslas32">; -def FSRA32 : VISInst<0b00101111, "fsra32">; +def FSLL16 : VISInst<0b000100001, "fsll16">; +def FSRL16 : VISInst<0b000100011, "fsrl16">; +def FSLL32 : VISInst<0b000100101, "fsll32">; +def FSRL32 : VISInst<0b000100111, "fsrl32">; +def FSLAS16 : VISInst<0b000101001, "fslas16">; +def FSRA16 : VISInst<0b000101011, "fsra16">; +def FSLAS32 : VISInst<0b000101101, "fslas32">; +def FSRA32 : VISInst<0b000101111, "fsra32">; let rs1 = 0 in def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd), diff --git a/lib/Target/Sparc/SparcJITInfo.cpp b/lib/Target/Sparc/SparcJITInfo.cpp deleted file mode 100644 index d0eec98..0000000 --- a/lib/Target/Sparc/SparcJITInfo.cpp +++ /dev/null @@ -1,326 +0,0 @@ -//===-- SparcJITInfo.cpp - Implement the Sparc JIT Interface --------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the JIT interfaces for the Sparc target. -// -//===----------------------------------------------------------------------===// -#include "SparcJITInfo.h" -#include "Sparc.h" -#include "SparcRelocations.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/JITCodeEmitter.h" -#include "llvm/Support/Memory.h" - -using namespace llvm; - -#define DEBUG_TYPE "jit" - -/// JITCompilerFunction - This contains the address of the JIT function used to -/// compile a function lazily. -static TargetJITInfo::JITCompilerFn JITCompilerFunction; - -extern "C" void SparcCompilationCallback(); - -extern "C" { -#if defined (__sparc__) - -#if defined(__arch64__) -#define FRAME_PTR(X) #X "+2047" -#else -#define FRAME_PTR(X) #X -#endif - - asm( - ".text\n" - "\t.align 4\n" - "\t.global SparcCompilationCallback\n" - "\t.type SparcCompilationCallback, #function\n" - "SparcCompilationCallback:\n" - // Save current register window and create stack. - // 128 (save area) + 6*8 (for arguments) + 16*8 (for float regfile) = 304 - "\tsave %sp, -304, %sp\n" - // save float regfile to the stack. - "\tstd %f0, [" FRAME_PTR(%fp) "-0]\n" - "\tstd %f2, [" FRAME_PTR(%fp) "-8]\n" - "\tstd %f4, [" FRAME_PTR(%fp) "-16]\n" - "\tstd %f6, [" FRAME_PTR(%fp) "-24]\n" - "\tstd %f8, [" FRAME_PTR(%fp) "-32]\n" - "\tstd %f10, [" FRAME_PTR(%fp) "-40]\n" - "\tstd %f12, [" FRAME_PTR(%fp) "-48]\n" - "\tstd %f14, [" FRAME_PTR(%fp) "-56]\n" - "\tstd %f16, [" FRAME_PTR(%fp) "-64]\n" - "\tstd %f18, [" FRAME_PTR(%fp) "-72]\n" - "\tstd %f20, [" FRAME_PTR(%fp) "-80]\n" - "\tstd %f22, [" FRAME_PTR(%fp) "-88]\n" - "\tstd %f24, [" FRAME_PTR(%fp) "-96]\n" - "\tstd %f26, [" FRAME_PTR(%fp) "-104]\n" - "\tstd %f28, [" FRAME_PTR(%fp) "-112]\n" - "\tstd %f30, [" FRAME_PTR(%fp) "-120]\n" - // stubaddr is in %g1. - "\tcall SparcCompilationCallbackC\n" - "\t mov %g1, %o0\n" - // restore float regfile from the stack. - "\tldd [" FRAME_PTR(%fp) "-0], %f0\n" - "\tldd [" FRAME_PTR(%fp) "-8], %f2\n" - "\tldd [" FRAME_PTR(%fp) "-16], %f4\n" - "\tldd [" FRAME_PTR(%fp) "-24], %f6\n" - "\tldd [" FRAME_PTR(%fp) "-32], %f8\n" - "\tldd [" FRAME_PTR(%fp) "-40], %f10\n" - "\tldd [" FRAME_PTR(%fp) "-48], %f12\n" - "\tldd [" FRAME_PTR(%fp) "-56], %f14\n" - "\tldd [" FRAME_PTR(%fp) "-64], %f16\n" - "\tldd [" FRAME_PTR(%fp) "-72], %f18\n" - "\tldd [" FRAME_PTR(%fp) "-80], %f20\n" - "\tldd [" FRAME_PTR(%fp) "-88], %f22\n" - "\tldd [" FRAME_PTR(%fp) "-96], %f24\n" - "\tldd [" FRAME_PTR(%fp) "-104], %f26\n" - "\tldd [" FRAME_PTR(%fp) "-112], %f28\n" - "\tldd [" FRAME_PTR(%fp) "-120], %f30\n" - // restore original register window and - // copy %o0 to %g1 - "\trestore %o0, 0, %g1\n" - // call the new stub - "\tjmp %g1\n" - "\t nop\n" - "\t.size SparcCompilationCallback, .-SparcCompilationCallback" - ); -#else - void SparcCompilationCallback() { - llvm_unreachable( - "Cannot call SparcCompilationCallback() on a non-sparc arch!"); - } -#endif -} - - -#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF)) -#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \ - | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF)) -#define NOP_INST SETHI_INST(0, 0) -#define OR_INST_I(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ - | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF)) -#define OR_INST_R(rs1, rs2, rd) (0x80000000 | ((rd) << 25) | (0x02 << 19) \ - | ((rs1) << 14) | (0 << 13) | ((rs2) & 0x1F)) -#define RDPC_INST(rd) (0x80000000 | ((rd) << 25) | (0x28 << 19) \ - | (5 << 14)) -#define LDX_INST(rs1, imm, rd) (0xC0000000 | ((rd) << 25) | (0x0B << 19) \ - | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF)) -#define SLLX_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x25 << 19) \ - | ((rs1) << 14) | (3 << 12) | ((imm) & 0x3F)) -#define SUB_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x04 << 19) \ - | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF)) -#define XOR_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x03 << 19) \ - | ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF)) -#define BA_INST(tgt) (0x10800000 | ((tgt) & 0x3FFFFF)) - -// Emit instructions to jump to Addr and store the starting address of -// the instructions emitted in the scratch register. -static void emitInstrForIndirectJump(intptr_t Addr, - unsigned scratch, - SmallVectorImpl<uint32_t> &Insts) { - - if (isInt<13>(Addr)) { - // Emit: jmpl %g0+Addr, <scratch> - // nop - Insts.push_back(JMP_INST(0, LO10(Addr), scratch)); - Insts.push_back(NOP_INST); - return; - } - - if (isUInt<32>(Addr)) { - // Emit: sethi %hi(Addr), scratch - // jmpl scratch+%lo(Addr), scratch - // sub scratch, 4, scratch - Insts.push_back(SETHI_INST(HI22(Addr), scratch)); - Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch)); - Insts.push_back(SUB_INST(scratch, 4, scratch)); - return; - } - - if (Addr < 0 && isInt<33>(Addr)) { - // Emit: sethi %hix(Addr), scratch) - // xor scratch, %lox(Addr), scratch - // jmpl scratch+0, scratch - // sub scratch, 8, scratch - Insts.push_back(SETHI_INST(HIX22(Addr), scratch)); - Insts.push_back(XOR_INST(scratch, LOX10(Addr), scratch)); - Insts.push_back(JMP_INST(scratch, 0, scratch)); - Insts.push_back(SUB_INST(scratch, 8, scratch)); - return; - } - - // Emit: rd %pc, scratch - // ldx [scratch+16], scratch - // jmpl scratch+0, scratch - // sub scratch, 8, scratch - // <Addr: 8 byte> - Insts.push_back(RDPC_INST(scratch)); - Insts.push_back(LDX_INST(scratch, 16, scratch)); - Insts.push_back(JMP_INST(scratch, 0, scratch)); - Insts.push_back(SUB_INST(scratch, 8, scratch)); - Insts.push_back((uint32_t)(((int64_t)Addr) >> 32) & 0xffffffff); - Insts.push_back((uint32_t)(Addr & 0xffffffff)); - - // Instruction sequence without rdpc instruction - // 7 instruction and 2 scratch register - // Emit: sethi %hh(Addr), scratch - // or scratch, %hm(Addr), scratch - // sllx scratch, 32, scratch - // sethi %hi(Addr), scratch2 - // or scratch, scratch2, scratch - // jmpl scratch+%lo(Addr), scratch - // sub scratch, 20, scratch - // Insts.push_back(SETHI_INST(HH22(Addr), scratch)); - // Insts.push_back(OR_INST_I(scratch, HM10(Addr), scratch)); - // Insts.push_back(SLLX_INST(scratch, 32, scratch)); - // Insts.push_back(SETHI_INST(HI22(Addr), scratch2)); - // Insts.push_back(OR_INST_R(scratch, scratch2, scratch)); - // Insts.push_back(JMP_INST(scratch, LO10(Addr), scratch)); - // Insts.push_back(SUB_INST(scratch, 20, scratch)); -} - -extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) { - // Get the address of the compiled code for this function. - intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr); - - // Rewrite the function stub so that we don't end up here every time we - // execute the call. We're replacing the stub instructions with code - // that jumps to the compiled function: - - SmallVector<uint32_t, 8> Insts; - intptr_t diff = (NewVal - StubAddr) >> 2; - if (isInt<22>(diff)) { - // Use branch instruction to jump - Insts.push_back(BA_INST(diff)); - Insts.push_back(NOP_INST); - } else { - // Otherwise, use indirect jump to the compiled function - emitInstrForIndirectJump(NewVal, 1, Insts); - } - - for (unsigned i = 0, e = Insts.size(); i != e; ++i) - *(uint32_t *)(StubAddr + i*4) = Insts[i]; - - sys::Memory::InvalidateInstructionCache((void*) StubAddr, Insts.size() * 4); - return (void*)StubAddr; -} - - -void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { - llvm_unreachable("FIXME: Implement SparcJITInfo::" - "replaceMachineCodeForFunction"); -} - - -TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() { - // The stub contains maximum of 4 4-byte instructions and 8 bytes for address, - // aligned at 32 bytes. - // See emitFunctionStub and emitInstrForIndirectJump for details. - StubLayout Result = { 4*4 + 8, 32 }; - return Result; -} - -void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn, - JITCodeEmitter &JCE) -{ - JCE.emitAlignment(32); - void *Addr = (void*) (JCE.getCurrentPCValue()); - - intptr_t CurrentAddr = (intptr_t)Addr; - intptr_t EmittedAddr; - SmallVector<uint32_t, 8> Insts; - if (Fn != (void*)(intptr_t)SparcCompilationCallback) { - EmittedAddr = (intptr_t)Fn; - intptr_t diff = (EmittedAddr - CurrentAddr) >> 2; - if (isInt<22>(diff)) { - Insts.push_back(BA_INST(diff)); - Insts.push_back(NOP_INST); - } - } else { - EmittedAddr = (intptr_t)SparcCompilationCallback; - } - - if (Insts.size() == 0) - emitInstrForIndirectJump(EmittedAddr, 1, Insts); - - - if (!sys::Memory::setRangeWritable(Addr, 4 * Insts.size())) - llvm_unreachable("ERROR: Unable to mark stub writable."); - - for (unsigned i = 0, e = Insts.size(); i != e; ++i) - JCE.emitWordBE(Insts[i]); - - sys::Memory::InvalidateInstructionCache(Addr, 4 * Insts.size()); - if (!sys::Memory::setRangeExecutable(Addr, 4 * Insts.size())) - llvm_unreachable("ERROR: Unable to mark stub executable."); - - return Addr; -} - - -TargetJITInfo::LazyResolverFn -SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) { - JITCompilerFunction = F; - return SparcCompilationCallback; -} - -/// relocate - Before the JIT can run a block of code that has been emitted, -/// it must rewrite the code to contain the actual addresses of any -/// referenced global symbols. -void SparcJITInfo::relocate(void *Function, MachineRelocation *MR, - unsigned NumRelocs, unsigned char *GOTBase) { - for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { - void *RelocPos = (char*) Function + MR->getMachineCodeOffset(); - intptr_t ResultPtr = (intptr_t) MR->getResultPointer(); - - switch ((SP::RelocationType) MR->getRelocationType()) { - case SP::reloc_sparc_hi: - ResultPtr = (ResultPtr >> 10) & 0x3fffff; - break; - - case SP::reloc_sparc_lo: - ResultPtr = (ResultPtr & 0x3ff); - break; - - case SP::reloc_sparc_pc30: - ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffffff; - break; - - case SP::reloc_sparc_pc22: - ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffff; - break; - - case SP::reloc_sparc_pc19: - ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff; - break; - - case SP::reloc_sparc_h44: - ResultPtr = (ResultPtr >> 22) & 0x3fffff; - break; - - case SP::reloc_sparc_m44: - ResultPtr = (ResultPtr >> 12) & 0x3ff; - break; - - case SP::reloc_sparc_l44: - ResultPtr = (ResultPtr & 0xfff); - break; - - case SP::reloc_sparc_hh: - ResultPtr = (((int64_t)ResultPtr) >> 42) & 0x3fffff; - break; - - case SP::reloc_sparc_hm: - ResultPtr = (((int64_t)ResultPtr) >> 32) & 0x3ff; - break; - - } - *((unsigned*) RelocPos) |= (unsigned) ResultPtr; - } -} diff --git a/lib/Target/Sparc/SparcJITInfo.h b/lib/Target/Sparc/SparcJITInfo.h deleted file mode 100644 index ff1b43a..0000000 --- a/lib/Target/Sparc/SparcJITInfo.h +++ /dev/null @@ -1,67 +0,0 @@ -//==- SparcJITInfo.h - Sparc Implementation of the JIT Interface -*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the declaration of the SparcJITInfo class. -// -//===----------------------------------------------------------------------===// - -#ifndef SPARCJITINFO_H -#define SPARCJITINFO_H - -#include "llvm/CodeGen/MachineConstantPool.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/TargetJITInfo.h" - -namespace llvm { -class SparcTargetMachine; - -class SparcJITInfo : public TargetJITInfo { - - bool IsPIC; - - public: - explicit SparcJITInfo() - : IsPIC(false) {} - - /// replaceMachineCodeForFunction - Make it so that calling the function - /// whose machine code is at OLD turns into a call to NEW, perhaps by - /// overwriting OLD with a branch to NEW. This is used for self-modifying - /// code. - /// - void replaceMachineCodeForFunction(void *Old, void *New) override; - - // getStubLayout - Returns the size and alignment of the largest call stub - // on Sparc. - StubLayout getStubLayout() override; - - - /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a - /// small native function that simply calls the function at the specified - /// address. - void *emitFunctionStub(const Function *F, void *Fn, - JITCodeEmitter &JCE) override; - - /// getLazyResolverFunction - Expose the lazy resolver to the JIT. - LazyResolverFn getLazyResolverFunction(JITCompilerFn) override; - - /// relocate - Before the JIT can run a block of code that has been emitted, - /// it must rewrite the code to contain the actual addresses of any - /// referenced global symbols. - void relocate(void *Function, MachineRelocation *MR, - unsigned NumRelocs, unsigned char *GOTBase) override; - - /// Initialize - Initialize internal stage for the function being JITted. - void Initialize(const MachineFunction &MF, bool isPIC) { - IsPIC = isPIC; - } - -}; -} - -#endif diff --git a/lib/Target/Sparc/SparcMachineFunctionInfo.h b/lib/Target/Sparc/SparcMachineFunctionInfo.h index 3783c16..1047442 100644 --- a/lib/Target/Sparc/SparcMachineFunctionInfo.h +++ b/lib/Target/Sparc/SparcMachineFunctionInfo.h @@ -10,8 +10,8 @@ // This file declares Sparc specific per-machine-function information. // //===----------------------------------------------------------------------===// -#ifndef SPARCMACHINEFUNCTIONINFO_H -#define SPARCMACHINEFUNCTIONINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCMACHINEFUNCTIONINFO_H +#define LLVM_LIB_TARGET_SPARC_SPARCMACHINEFUNCTIONINFO_H #include "llvm/CodeGen/MachineFunction.h" diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index dc1ec7c..3cca98f 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -108,7 +108,7 @@ static void replaceFI(MachineFunction &MF, return; } - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); // FIXME: it would be better to scavenge a register here instead of // reserving G1 all of the time. @@ -174,7 +174,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) { if (MI.getOpcode() == SP::STQFri) { - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned SrcReg = MI.getOperand(2).getReg(); unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); @@ -186,7 +186,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MI.getOperand(2).setReg(SrcOddReg); Offset += 8; } else if (MI.getOpcode() == SP::LDQFri) { - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned DestReg = MI.getOperand(0).getReg(); unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64); unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64); diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 77f879a..63567b0 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCREGISTERINFO_H -#define SPARCREGISTERINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H +#define LLVM_LIB_TARGET_SPARC_SPARCREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" diff --git a/lib/Target/Sparc/SparcRelocations.h b/lib/Target/Sparc/SparcRelocations.h deleted file mode 100644 index c1ff78d..0000000 --- a/lib/Target/Sparc/SparcRelocations.h +++ /dev/null @@ -1,56 +0,0 @@ -//===-- SparcRelocations.h - Sparc Code Relocations -------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the Sparc target-specific relocation types -// (for relocation-model=static). -// -//===----------------------------------------------------------------------===// - -#ifndef SPARC_RELOCATIONS_H -#define SPARC_RELOCATIONS_H - -#include "llvm/CodeGen/MachineRelocation.h" - -namespace llvm { - namespace SP { - enum RelocationType { - // reloc_sparc_hi - upper 22 bits - reloc_sparc_hi = 1, - - // reloc_sparc_lo - lower 10 bits - reloc_sparc_lo = 2, - - // reloc_sparc_pc30 - pc rel. 30 bits for call - reloc_sparc_pc30 = 3, - - // reloc_sparc_pc22 - pc rel. 22 bits for branch - reloc_sparc_pc22 = 4, - - // reloc_sparc_pc22 - pc rel. 19 bits for branch with icc/xcc - reloc_sparc_pc19 = 5, - - // reloc_sparc_h44 - 43-22 bits - reloc_sparc_h44 = 6, - - // reloc_sparc_m44 - 21-12 bits - reloc_sparc_m44 = 7, - - // reloc_sparc_l44 - lower 12 bits - reloc_sparc_l44 = 8, - - // reloc_sparc_hh - 63-42 bits - reloc_sparc_hh = 9, - - // reloc_sparc_hm - 41-32 bits - reloc_sparc_hm = 10 - }; - } -} - -#endif diff --git a/lib/Target/Sparc/SparcSelectionDAGInfo.h b/lib/Target/Sparc/SparcSelectionDAGInfo.h index 2346f41..a3a21d6 100644 --- a/lib/Target/Sparc/SparcSelectionDAGInfo.h +++ b/lib/Target/Sparc/SparcSelectionDAGInfo.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCSELECTIONDAGINFO_H -#define SPARCSELECTIONDAGINFO_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCSELECTIONDAGINFO_H +#define LLVM_LIB_TARGET_SPARC_SPARCSELECTIONDAGINFO_H #include "llvm/Target/TargetSelectionDAGInfo.h" diff --git a/lib/Target/Sparc/SparcSubtarget.h b/lib/Target/Sparc/SparcSubtarget.h index a335778..d503b2b 100644 --- a/lib/Target/Sparc/SparcSubtarget.h +++ b/lib/Target/Sparc/SparcSubtarget.h @@ -11,13 +11,12 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARC_SUBTARGET_H -#define SPARC_SUBTARGET_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H +#define LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H #include "SparcFrameLowering.h" #include "SparcInstrInfo.h" #include "SparcISelLowering.h" -#include "SparcJITInfo.h" #include "SparcSelectionDAGInfo.h" #include "llvm/IR/DataLayout.h" #include "llvm/Target/TargetFrameLowering.h" @@ -43,21 +42,25 @@ class SparcSubtarget : public SparcGenSubtargetInfo { SparcTargetLowering TLInfo; SparcSelectionDAGInfo TSInfo; SparcFrameLowering FrameLowering; - SparcJITInfo JITInfo; public: SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, TargetMachine &TM, bool is64bit); - const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } - const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; } - const SparcRegisterInfo *getRegisterInfo() const { + const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } + const TargetFrameLowering *getFrameLowering() const override { + return &FrameLowering; + } + const SparcRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } - const SparcTargetLowering *getTargetLowering() const { return &TLInfo; } - const SparcSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; } - SparcJITInfo *getJITInfo() { return &JITInfo; } - const DataLayout *getDataLayout() const { return &DL; } + const SparcTargetLowering *getTargetLowering() const override { + return &TLInfo; + } + const SparcSelectionDAGInfo *getSelectionDAGInfo() const override { + return &TSInfo; + } + const DataLayout *getDataLayout() const override { return &DL; } bool isV9() const { return IsV9; } bool isVIS() const { return IsVIS; } diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp index 0130fac..489bb69 100644 --- a/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/lib/Target/Sparc/SparcTargetMachine.cpp @@ -11,6 +11,7 @@ //===----------------------------------------------------------------------===// #include "SparcTargetMachine.h" +#include "SparcTargetObjectFile.h" #include "Sparc.h" #include "llvm/CodeGen/Passes.h" #include "llvm/PassManager.h" @@ -32,10 +33,13 @@ SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, CodeGenOpt::Level OL, bool is64bit) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), + TLOF(make_unique<SparcELFTargetObjectFile>()), Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } +SparcTargetMachine::~SparcTargetMachine() {} + namespace { /// Sparc Code Generator Pass Configuration Options. class SparcPassConfig : public TargetPassConfig { @@ -47,6 +51,7 @@ public: return getTM<SparcTargetMachine>(); } + void addIRPasses() override; bool addInstSelector() override; bool addPreEmitPass() override; }; @@ -56,15 +61,14 @@ TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) { return new SparcPassConfig(this, PM); } -bool SparcPassConfig::addInstSelector() { - addPass(createSparcISelDag(getSparcTargetMachine())); - return false; +void SparcPassConfig::addIRPasses() { + addPass(createAtomicExpandPass(&getSparcTargetMachine())); + + TargetPassConfig::addIRPasses(); } -bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM, - JITCodeEmitter &JCE) { - // Machine code emitter pass for Sparc. - PM.add(createSparcJITCodeEmitterPass(*this, JCE)); +bool SparcPassConfig::addInstSelector() { + addPass(createSparcISelDag(getSparcTargetMachine())); return false; } diff --git a/lib/Target/Sparc/SparcTargetMachine.h b/lib/Target/Sparc/SparcTargetMachine.h index 03b5137..096e7c8 100644 --- a/lib/Target/Sparc/SparcTargetMachine.h +++ b/lib/Target/Sparc/SparcTargetMachine.h @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCTARGETMACHINE_H -#define SPARCTARGETMACHINE_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H +#define LLVM_LIB_TARGET_SPARC_SPARCTARGETMACHINE_H #include "SparcInstrInfo.h" #include "SparcSubtarget.h" @@ -21,37 +21,22 @@ namespace llvm { class SparcTargetMachine : public LLVMTargetMachine { + std::unique_ptr<TargetLoweringObjectFile> TLOF; SparcSubtarget Subtarget; public: SparcTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit); + ~SparcTargetMachine() override; - const SparcInstrInfo *getInstrInfo() const override { - return getSubtargetImpl()->getInstrInfo(); - } - const TargetFrameLowering *getFrameLowering() const override { - return getSubtargetImpl()->getFrameLowering(); - } const SparcSubtarget *getSubtargetImpl() const override { return &Subtarget; } - const SparcRegisterInfo *getRegisterInfo() const override { - return getSubtargetImpl()->getRegisterInfo(); - } - const SparcTargetLowering *getTargetLowering() const override { - return getSubtargetImpl()->getTargetLowering(); - } - const SparcSelectionDAGInfo *getSelectionDAGInfo() const override { - return getSubtargetImpl()->getSelectionDAGInfo(); - } - SparcJITInfo *getJITInfo() override { return Subtarget.getJITInfo(); } - const DataLayout *getDataLayout() const override { - return getSubtargetImpl()->getDataLayout(); - } // Pass Pipeline Configuration TargetPassConfig *createPassConfig(PassManagerBase &PM) override; - bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override; + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } }; /// SparcV8TargetMachine - Sparc 32-bit target machine diff --git a/lib/Target/Sparc/SparcTargetObjectFile.h b/lib/Target/Sparc/SparcTargetObjectFile.h index c60675b..76c8cca 100644 --- a/lib/Target/Sparc/SparcTargetObjectFile.h +++ b/lib/Target/Sparc/SparcTargetObjectFile.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_SPARC_TARGETOBJECTFILE_H -#define LLVM_TARGET_SPARC_TARGETOBJECTFILE_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCTARGETOBJECTFILE_H +#define LLVM_LIB_TARGET_SPARC_SPARCTARGETOBJECTFILE_H #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" diff --git a/lib/Target/Sparc/SparcTargetStreamer.h b/lib/Target/Sparc/SparcTargetStreamer.h index 3767d8e..3b50350 100644 --- a/lib/Target/Sparc/SparcTargetStreamer.h +++ b/lib/Target/Sparc/SparcTargetStreamer.h @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// -#ifndef SPARCTARGETSTREAMER_H -#define SPARCTARGETSTREAMER_H +#ifndef LLVM_LIB_TARGET_SPARC_SPARCTARGETSTREAMER_H +#define LLVM_LIB_TARGET_SPARC_SPARCTARGETSTREAMER_H #include "llvm/MC/MCELFStreamer.h" #include "llvm/MC/MCStreamer.h" |