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-rw-r--r--lib/Target/SparcV9/InstrSched/SchedGraph.cpp8
-rw-r--r--lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp3
-rw-r--r--lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp7
-rw-r--r--lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp5
-rw-r--r--lib/Target/SparcV9/SparcV9AsmPrinter.cpp2
-rw-r--r--lib/Target/SparcV9/SparcV9CodeEmitter.cpp2
-rw-r--r--lib/Target/SparcV9/SparcV9PeepholeOpts.cpp9
-rw-r--r--lib/Target/SparcV9/SparcV9RegInfo.cpp2
-rw-r--r--lib/Target/SparcV9/SparcV9RegInfo.h2
9 files changed, 19 insertions, 21 deletions
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 01ca36f..0547159 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -487,11 +487,11 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
// if this references a register other than the hardwired
// "zero" register, record the reference.
if (mop.hasAllocatedReg()) {
- int regNum = mop.getAllocatedRegNum();
+ unsigned regNum = mop.getReg();
// If this is not a dummy zero register, record the reference in order
if (regNum != target.getRegInfo().getZeroRegNum())
- regToRefVecMap[mop.getAllocatedRegNum()]
+ regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i));
// If this is a volatile register, add the instruction to callDepVec
@@ -528,9 +528,9 @@ void SchedGraph::findDefUseInfoAtInstr(const TargetMachine& target,
for (unsigned i=0, N = MI.getNumImplicitRefs(); i != N; ++i) {
const MachineOperand& mop = MI.getImplicitOp(i);
if (mop.hasAllocatedReg()) {
- int regNum = mop.getAllocatedRegNum();
+ unsigned regNum = mop.getReg();
if (regNum != target.getRegInfo().getZeroRegNum())
- regToRefVecMap[mop.getAllocatedRegNum()]
+ regToRefVecMap[mop.getReg()]
.push_back(std::make_pair(node, i + MI.getNumOperands()));
continue; // nothing more to do
}
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index 131107b..a792386 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -71,7 +71,8 @@ ChooseRegOrImmed(int64_t intValue,
opType = isSigned? MachineOperand::MO_SignExtendedImmed
: MachineOperand::MO_UnextendedImmed;
getImmedValue = intValue;
- } else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0) {
+ } else if (intValue == 0 &&
+ target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
opType = MachineOperand::MO_MachineRegister;
getMachineRegNum = target.getRegInfo().getZeroRegNum();
}
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index f28ca86..100f9eb 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -194,9 +194,8 @@ void LiveRangeInfo::constructLiveRanges() {
// set it directly in the LiveRange
if (OpI.getMachineOperand().hasAllocatedReg()) {
unsigned getClassId;
- LR->setColor(MRI.getClassRegNum(
- OpI.getMachineOperand().getAllocatedRegNum(),
- getClassId));
+ LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
+ getClassId));
}
}
@@ -212,7 +211,7 @@ void LiveRangeInfo::constructLiveRanges() {
if (MInst->getImplicitOp(i).hasAllocatedReg()) {
unsigned getClassId;
LR->setColor(MRI.getClassRegNum(
- MInst->getImplicitOp(i).getAllocatedRegNum(),
+ MInst->getImplicitOp(i).getReg(),
getClassId));
}
}
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 4a7d503..cc019b4 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -1019,12 +1019,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
// explicit and implicit operands are set.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).hasAllocatedReg())
- markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
+ markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
if (MI->getImplicitOp(i).hasAllocatedReg())
- markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
- RegType,MRI);
+ markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
// Add all of the scratch registers that are used to save values across the
// instruction (e.g., for saving state register values).
diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 20fbfa3..e87f6a2 100644
--- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -637,7 +637,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_MachineRegister:
{
- int regNum = (int)mop.getAllocatedRegNum();
+ int regNum = (int)mop.getReg();
if (regNum == Target.getRegInfo().getInvalidRegNum()) {
// better to print code with NULL registers than to die
diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
index 753f5d3..0db45e3 100644
--- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
+++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
@@ -661,7 +661,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
// This is necessary because the Sparc backend doesn't actually lay out
// registers in the real fashion -- it skips those that it chooses not to
// allocate, i.e. those that are the FP, SP, etc.
- unsigned fakeReg = MO.getAllocatedRegNum();
+ unsigned fakeReg = MO.getReg();
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
<< realRegByClass << " (LLC: "
diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index a69171c..d8a5515 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -63,16 +63,15 @@ DeleteInstruction(MachineBasicBlock& mvec,
static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
return (// both operands are allocated to the same register
- MI->getOperand(0).getAllocatedRegNum() ==
- MI->getOperand(1).getAllocatedRegNum());
+ MI->getOperand(0).getReg() == MI->getOperand(1).getReg());
} else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
- MI->getOperand(srcWithDestReg).getAllocatedRegNum()
- == MI->getOperand(2).getAllocatedRegNum())
+ MI->getOperand(srcWithDestReg).getReg()
+ == MI->getOperand(2).getReg())
break;
if (srcWithDestReg == 2)
@@ -82,7 +81,7 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
unsigned otherOp = 1 - srcWithDestReg;
return (// either operand otherOp is register %g0
(MI->getOperand(otherOp).hasAllocatedReg() &&
- MI->getOperand(otherOp).getAllocatedRegNum() ==
+ MI->getOperand(otherOp).getReg() ==
target.getRegInfo().getZeroRegNum()) ||
// or operand otherOp == 0
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp
index 5033a0a..8d6e6d5 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp
@@ -52,7 +52,7 @@ SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
// getZeroRegNum - returns the register that contains always zero.
// this is the unified register number
//
-int SparcRegInfo::getZeroRegNum() const {
+unsigned SparcRegInfo::getZeroRegNum() const {
return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
SparcIntRegClass::g0);
}
diff --git a/lib/Target/SparcV9/SparcV9RegInfo.h b/lib/Target/SparcV9/SparcV9RegInfo.h
index 34069d8..3dd9e68 100644
--- a/lib/Target/SparcV9/SparcV9RegInfo.h
+++ b/lib/Target/SparcV9/SparcV9RegInfo.h
@@ -86,7 +86,7 @@ public:
// getZeroRegNum - returns the register that contains always zero this is the
// unified register number
//
- virtual int getZeroRegNum() const;
+ virtual unsigned getZeroRegNum() const;
// getCallAddressReg - returns the reg used for pushing the address when a
// function is called. This can be used for other purposes between calls
generated by cgit v1.1 at 2025-08-15 22:25:56 +0000