diff options
Diffstat (limited to 'lib/Target/X86/X86InstrFormats.td')
| -rw-r--r-- | lib/Target/X86/X86InstrFormats.td | 165 |
1 files changed, 93 insertions, 72 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td index fe4ead1..56043fb 100644 --- a/lib/Target/X86/X86InstrFormats.td +++ b/lib/Target/X86/X86InstrFormats.td @@ -34,23 +34,27 @@ def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>; def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>; def MRM6m : Format<30>; def MRM7m : Format<31>; def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>; -def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>; -def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>; -def MRM_CF : Format<41>; def MRM_D0 : Format<42>; def MRM_D1 : Format<43>; -def MRM_D4 : Format<44>; def MRM_D5 : Format<45>; def MRM_D6 : Format<46>; -def MRM_D7 : Format<47>; def MRM_D8 : Format<48>; def MRM_D9 : Format<49>; -def MRM_DA : Format<50>; def MRM_DB : Format<51>; def MRM_DC : Format<52>; -def MRM_DD : Format<53>; def MRM_DE : Format<54>; def MRM_DF : Format<55>; -def MRM_E0 : Format<56>; def MRM_E1 : Format<57>; def MRM_E2 : Format<58>; -def MRM_E3 : Format<59>; def MRM_E4 : Format<60>; def MRM_E5 : Format<61>; -def MRM_E8 : Format<62>; def MRM_E9 : Format<63>; def MRM_EA : Format<64>; -def MRM_EB : Format<65>; def MRM_EC : Format<66>; def MRM_ED : Format<67>; -def MRM_EE : Format<68>; def MRM_F0 : Format<69>; def MRM_F1 : Format<70>; -def MRM_F2 : Format<71>; def MRM_F3 : Format<72>; def MRM_F4 : Format<73>; -def MRM_F5 : Format<74>; def MRM_F6 : Format<75>; def MRM_F7 : Format<76>; -def MRM_F8 : Format<77>; def MRM_F9 : Format<78>; def MRM_FA : Format<79>; -def MRM_FB : Format<80>; def MRM_FC : Format<81>; def MRM_FD : Format<82>; -def MRM_FE : Format<83>; def MRM_FF : Format<84>; +def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C5 : Format<37>; +def MRM_C6 : Format<38>; def MRM_C7 : Format<39>; def MRM_C8 : Format<40>; +def MRM_C9 : Format<41>; def MRM_CA : Format<42>; def MRM_CB : Format<43>; +def MRM_CC : Format<44>; def MRM_CD : Format<45>; def MRM_CE : Format<46>; +def MRM_CF : Format<47>; def MRM_D0 : Format<48>; def MRM_D1 : Format<49>; +def MRM_D2 : Format<50>; def MRM_D3 : Format<51>; def MRM_D4 : Format<52>; +def MRM_D5 : Format<53>; def MRM_D6 : Format<54>; def MRM_D7 : Format<55>; +def MRM_D8 : Format<56>; def MRM_D9 : Format<57>; def MRM_DA : Format<58>; +def MRM_DB : Format<59>; def MRM_DC : Format<60>; def MRM_DD : Format<61>; +def MRM_DE : Format<62>; def MRM_DF : Format<63>; def MRM_E0 : Format<64>; +def MRM_E1 : Format<65>; def MRM_E2 : Format<66>; def MRM_E3 : Format<67>; +def MRM_E4 : Format<68>; def MRM_E5 : Format<69>; def MRM_E6 : Format<70>; +def MRM_E7 : Format<71>; def MRM_E8 : Format<72>; def MRM_E9 : Format<73>; +def MRM_EA : Format<74>; def MRM_EB : Format<75>; def MRM_EC : Format<76>; +def MRM_ED : Format<77>; def MRM_EE : Format<78>; def MRM_EF : Format<79>; +def MRM_F0 : Format<80>; def MRM_F1 : Format<81>; def MRM_F2 : Format<82>; +def MRM_F3 : Format<83>; def MRM_F4 : Format<84>; def MRM_F5 : Format<85>; +def MRM_F6 : Format<86>; def MRM_F7 : Format<87>; def MRM_F8 : Format<88>; +def MRM_F9 : Format<89>; def MRM_FA : Format<90>; def MRM_FB : Format<91>; +def MRM_FC : Format<92>; def MRM_FD : Format<93>; def MRM_FE : Format<94>; +def MRM_FF : Format<95>; // ImmType - This specifies the immediate type used by an instruction. This is // part of the ad-hoc solution used to emit machine instruction encodings by our @@ -146,11 +150,22 @@ def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix. def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode. def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode. +// Address size for encodings that change based on mode. +class AddressSize<bits<2> val> { + bits<2> Value = val; +} +def AdSizeX : AddressSize<0>; // Address size determined using addr operand. +def AdSize16 : AddressSize<1>; // Encodes a 16-bit address. +def AdSize32 : AddressSize<2>; // Encodes a 32-bit address. +def AdSize64 : AddressSize<3>; // Encodes a 64-bit address. + // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. class OpSize16 { OperandSize OpSize = OpSize16; } class OpSize32 { OperandSize OpSize = OpSize32; } -class AdSize { bit hasAdSizePrefix = 1; } +class AdSize16 { AddressSize AdSize = AdSize16; } +class AdSize32 { AddressSize AdSize = AdSize32; } +class AdSize64 { AddressSize AdSize = AdSize64; } class REX_W { bit hasREX_WPrefix = 1; } class LOCK { bit hasLockPrefix = 1; } class REP { bit hasREPPrefix = 1; } @@ -231,9 +246,11 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, // AsmString from the parser, but still disassemble. OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change - // based on operand size of the mode + // based on operand size of the mode? bits<2> OpSizeBits = OpSize.Value; - bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix? + AddressSize AdSize = AdSizeX; // Does this instruction's encoding change + // based on address size of the mode? + bits<2> AdSizeBits = AdSize.Value; Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have? bits<3> OpPrefixBits = OpPrefix.Value; @@ -284,35 +301,35 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins, CD8_EltSize, !srl(VectSize, CD8_Form{1-0}))), 0); - // TSFlags layout should be kept in sync with X86InstrInfo.h. + // TSFlags layout should be kept in sync with X86BaseInfo.h. let TSFlags{6-0} = FormBits; let TSFlags{8-7} = OpSizeBits; - let TSFlags{9} = hasAdSizePrefix; - let TSFlags{12-10} = OpPrefixBits; - let TSFlags{15-13} = OpMapBits; - let TSFlags{16} = hasREX_WPrefix; - let TSFlags{20-17} = ImmT.Value; - let TSFlags{23-21} = FPForm.Value; - let TSFlags{24} = hasLockPrefix; - let TSFlags{25} = hasREPPrefix; - let TSFlags{27-26} = ExeDomain.Value; - let TSFlags{29-28} = OpEncBits; - let TSFlags{37-30} = Opcode; - let TSFlags{38} = hasVEX_WPrefix; - let TSFlags{39} = hasVEX_4V; - let TSFlags{40} = hasVEX_4VOp3; - let TSFlags{41} = hasVEX_i8ImmReg; - let TSFlags{42} = hasVEX_L; - let TSFlags{43} = ignoresVEX_L; - let TSFlags{44} = hasEVEX_K; - let TSFlags{45} = hasEVEX_Z; - let TSFlags{46} = hasEVEX_L2; - let TSFlags{47} = hasEVEX_B; + let TSFlags{10-9} = AdSizeBits; + let TSFlags{13-11} = OpPrefixBits; + let TSFlags{16-14} = OpMapBits; + let TSFlags{17} = hasREX_WPrefix; + let TSFlags{21-18} = ImmT.Value; + let TSFlags{24-22} = FPForm.Value; + let TSFlags{25} = hasLockPrefix; + let TSFlags{26} = hasREPPrefix; + let TSFlags{28-27} = ExeDomain.Value; + let TSFlags{30-29} = OpEncBits; + let TSFlags{38-31} = Opcode; + let TSFlags{39} = hasVEX_WPrefix; + let TSFlags{40} = hasVEX_4V; + let TSFlags{41} = hasVEX_4VOp3; + let TSFlags{42} = hasVEX_i8ImmReg; + let TSFlags{43} = hasVEX_L; + let TSFlags{44} = ignoresVEX_L; + let TSFlags{45} = hasEVEX_K; + let TSFlags{46} = hasEVEX_Z; + let TSFlags{47} = hasEVEX_L2; + let TSFlags{48} = hasEVEX_B; // If we run out of TSFlags bits, it's possible to encode this in 3 bits. - let TSFlags{54-48} = CD8_Scale; - let TSFlags{55} = has3DNow0F0FOpcode; - let TSFlags{56} = hasMemOp4Prefix; - let TSFlags{57} = hasEVEX_RC; + let TSFlags{55-49} = CD8_Scale; + let TSFlags{56} = has3DNow0F0FOpcode; + let TSFlags{57} = hasMemOp4Prefix; + let TSFlags{58} = hasEVEX_RC; } class PseudoI<dag oops, dag iops, list<dag> pattern> @@ -327,26 +344,26 @@ class I<bits<8> o, Format f, dag outs, dag ins, string asm, let Pattern = pattern; let CodeSize = 3; } -class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary, Domain d = GenericDomain> : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> { let Pattern = pattern; let CodeSize = 3; } -class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> { let Pattern = pattern; let CodeSize = 3; } -class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm16, outs, ins, asm, itin> { let Pattern = pattern; let CodeSize = 3; } -class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm32, outs, ins, asm, itin> { let Pattern = pattern; @@ -359,14 +376,14 @@ class Ii32S<bits<8> o, Format f, dag outs, dag ins, string asm, let CodeSize = 3; } -class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> { let Pattern = pattern; let CodeSize = 3; } -class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, +class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> { let Pattern = pattern; @@ -393,14 +410,14 @@ class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern, // Iseg16 - 16-bit segment selector, 16-bit offset // Iseg32 - 16-bit segment selector, 32-bit offset -class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, +class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm16, outs, ins, asm, itin> { let Pattern = pattern; let CodeSize = 3; } -class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, +class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : X86Inst<o, f, Imm32, outs, ins, asm, itin> { let Pattern = pattern; @@ -409,8 +426,9 @@ class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm, // SI - SSE 1 & 2 scalar instructions class SI<bits<8> o, Format F, dag outs, dag ins, string asm, - list<dag> pattern, InstrItinClass itin = NoItinerary> - : I<o, F, outs, ins, asm, pattern, itin> { + list<dag> pattern, InstrItinClass itin = NoItinerary, + Domain d = GenericDomain> + : I<o, F, outs, ins, asm, pattern, itin, d> { let Predicates = !if(!eq(OpEnc.Value, EncEVEX.Value), [HasAVX512], !if(!eq(OpEnc.Value, EncVEX.Value), [UseAVX], !if(!eq(OpPrefix.Value, XS.Value), [UseSSE1], @@ -478,7 +496,7 @@ class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm, } // SSE1 Instruction Templates: -// +// // SSI - SSE1 instructions with XS prefix. // PSI - SSE1 instructions with PS prefix. // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix. @@ -509,7 +527,7 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm, Requires<[HasAVX]>; // SSE2 Instruction Templates: -// +// // SDI - SSE2 instructions with XD prefix. // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix. // S2SI - SSE2 instructions with XS prefix. @@ -573,16 +591,16 @@ class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm, : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>; // SSE3 Instruction Templates: -// +// // S3I - SSE3 instructions with PD prefixes. // S3SI - SSE3 instructions with XS prefix. // S3DI - SSE3 instructions with XD prefix. -class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, +class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS, Requires<[UseSSE3]>; -class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, +class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD, Requires<[UseSSE3]>; @@ -593,7 +611,7 @@ class S3I<bits<8> o, Format F, dag outs, dag ins, string asm, // SSSE3 Instruction Templates: -// +// // SS38I - SSSE3 instructions with T8 prefix. // SS3AI - SSSE3 instructions with TA prefix. // MMXSS38I - SSSE3 instructions with T8 prefix and MMX operands. @@ -621,7 +639,7 @@ class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm, Requires<[HasSSSE3]>; // SSE4.1 Instruction Templates: -// +// // SS48I - SSE 4.1 instructions with T8 prefix. // SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8. // @@ -635,7 +653,7 @@ class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm, Requires<[UseSSE41]>; // SSE4.2 Instruction Templates: -// +// // SS428I - SSE 4.2 instructions with T8 prefix. class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> @@ -699,6 +717,9 @@ class AVX5128I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8PD, Requires<[HasAVX512]>; +class AVX5128IBase : T8PD { + Domain ExeDomain = SSEPackedInt; +} class AVX512XS8I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8XS, @@ -868,27 +889,27 @@ class VRS2I<bits<8> o, Format F, dag outs, dag ins, string asm, // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix. // MMXID - MMX instructions with XD prefix. // MMXIS - MMX instructions with XS prefix. -class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; -class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXI32<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,Not64BitMode]>; -class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX,In64BitMode]>; -class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PS, REX_W, Requires<[HasMMX]>; -class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : I<o, F, outs, ins, asm, pattern, itin>, PD, Requires<[HasMMX]>; -class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : Ii8<o, F, outs, ins, asm, pattern, itin>, PS, Requires<[HasMMX]>; -class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>; -class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, +class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern, InstrItinClass itin = NoItinerary> : Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>; |