diff options
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 832 |
1 files changed, 452 insertions, 380 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 3dbf819..9881caf 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -32,7 +32,8 @@ def SDTX86Cmov : SDTypeProfile<1, 4, // Unary and binary operator instructions that set EFLAGS as a side-effect. def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, - [SDTCisInt<0>, SDTCisVT<1, i32>]>; + [SDTCisSameAs<0, 2>, + SDTCisInt<0>, SDTCisVT<1, i32>]>; def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, [SDTCisSameAs<0, 2>, @@ -188,11 +189,15 @@ def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, - [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; + [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; +def X86RecoverFrameAlloc : SDNode<"ISD::FRAME_ALLOC_RECOVER", + SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, + SDTCisInt<1>]>>; + def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; @@ -261,121 +266,75 @@ def ptr_rc_nosp : PointerLikeRegClass<1>; def X86MemAsmOperand : AsmOperandClass { let Name = "Mem"; } -def X86Mem8AsmOperand : AsmOperandClass { - let Name = "Mem8"; let RenderMethod = "addMemOperands"; -} -def X86Mem16AsmOperand : AsmOperandClass { - let Name = "Mem16"; let RenderMethod = "addMemOperands"; -} -def X86Mem32AsmOperand : AsmOperandClass { - let Name = "Mem32"; let RenderMethod = "addMemOperands"; -} -def X86Mem64AsmOperand : AsmOperandClass { - let Name = "Mem64"; let RenderMethod = "addMemOperands"; -} -def X86Mem80AsmOperand : AsmOperandClass { - let Name = "Mem80"; let RenderMethod = "addMemOperands"; -} -def X86Mem128AsmOperand : AsmOperandClass { - let Name = "Mem128"; let RenderMethod = "addMemOperands"; -} -def X86Mem256AsmOperand : AsmOperandClass { - let Name = "Mem256"; let RenderMethod = "addMemOperands"; -} -def X86Mem512AsmOperand : AsmOperandClass { - let Name = "Mem512"; let RenderMethod = "addMemOperands"; -} - -// Gather mem operands -def X86MemVX32Operand : AsmOperandClass { - let Name = "MemVX32"; let RenderMethod = "addMemOperands"; -} -def X86MemVY32Operand : AsmOperandClass { - let Name = "MemVY32"; let RenderMethod = "addMemOperands"; -} -def X86MemVZ32Operand : AsmOperandClass { - let Name = "MemVZ32"; let RenderMethod = "addMemOperands"; -} -def X86MemVX64Operand : AsmOperandClass { - let Name = "MemVX64"; let RenderMethod = "addMemOperands"; -} -def X86MemVY64Operand : AsmOperandClass { - let Name = "MemVY64"; let RenderMethod = "addMemOperands"; -} -def X86MemVZ64Operand : AsmOperandClass { - let Name = "MemVZ64"; let RenderMethod = "addMemOperands"; +let RenderMethod = "addMemOperands" in { + def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } + def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } + def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } + def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } + def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } + def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } + def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } + def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } + // Gather mem operands + def X86MemVX32Operand : AsmOperandClass { let Name = "MemVX32"; } + def X86MemVY32Operand : AsmOperandClass { let Name = "MemVY32"; } + def X86MemVZ32Operand : AsmOperandClass { let Name = "MemVZ32"; } + def X86MemVX64Operand : AsmOperandClass { let Name = "MemVX64"; } + def X86MemVY64Operand : AsmOperandClass { let Name = "MemVY64"; } + def X86MemVZ64Operand : AsmOperandClass { let Name = "MemVZ64"; } } def X86AbsMemAsmOperand : AsmOperandClass { let Name = "AbsMem"; let SuperClasses = [X86MemAsmOperand]; } -class X86MemOperand<string printMethod> : Operand<iPTR> { + +class X86MemOperand<string printMethod, + AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { let PrintMethod = printMethod; let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); - let ParserMatchClass = X86MemAsmOperand; + let ParserMatchClass = parserMatchClass; + let OperandType = "OPERAND_MEMORY"; } -let OperandType = "OPERAND_MEMORY" in { +// Gather mem operands +class X86VMemOperand<RegisterClass RC, string printMethod, + AsmOperandClass parserMatchClass> + : X86MemOperand<printMethod, parserMatchClass> { + let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, i8imm); +} + +def anymem : X86MemOperand<"printanymem">; + def opaque32mem : X86MemOperand<"printopaquemem">; def opaque48mem : X86MemOperand<"printopaquemem">; def opaque80mem : X86MemOperand<"printopaquemem">; def opaque512mem : X86MemOperand<"printopaquemem">; -def i8mem : X86MemOperand<"printi8mem"> { - let ParserMatchClass = X86Mem8AsmOperand; } -def i16mem : X86MemOperand<"printi16mem"> { - let ParserMatchClass = X86Mem16AsmOperand; } -def i32mem : X86MemOperand<"printi32mem"> { - let ParserMatchClass = X86Mem32AsmOperand; } -def i64mem : X86MemOperand<"printi64mem"> { - let ParserMatchClass = X86Mem64AsmOperand; } -def i128mem : X86MemOperand<"printi128mem"> { - let ParserMatchClass = X86Mem128AsmOperand; } -def i256mem : X86MemOperand<"printi256mem"> { - let ParserMatchClass = X86Mem256AsmOperand; } -def i512mem : X86MemOperand<"printi512mem"> { - let ParserMatchClass = X86Mem512AsmOperand; } -def f32mem : X86MemOperand<"printf32mem"> { - let ParserMatchClass = X86Mem32AsmOperand; } -def f64mem : X86MemOperand<"printf64mem"> { - let ParserMatchClass = X86Mem64AsmOperand; } -def f80mem : X86MemOperand<"printf80mem"> { - let ParserMatchClass = X86Mem80AsmOperand; } -def f128mem : X86MemOperand<"printf128mem"> { - let ParserMatchClass = X86Mem128AsmOperand; } -def f256mem : X86MemOperand<"printf256mem">{ - let ParserMatchClass = X86Mem256AsmOperand; } -def f512mem : X86MemOperand<"printf512mem">{ - let ParserMatchClass = X86Mem512AsmOperand; } -def v512mem : Operand<iPTR> { - let PrintMethod = "printf512mem"; - let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); - let ParserMatchClass = X86Mem512AsmOperand; } +def i8mem : X86MemOperand<"printi8mem", X86Mem8AsmOperand>; +def i16mem : X86MemOperand<"printi16mem", X86Mem16AsmOperand>; +def i32mem : X86MemOperand<"printi32mem", X86Mem32AsmOperand>; +def i64mem : X86MemOperand<"printi64mem", X86Mem64AsmOperand>; +def i128mem : X86MemOperand<"printi128mem", X86Mem128AsmOperand>; +def i256mem : X86MemOperand<"printi256mem", X86Mem256AsmOperand>; +def i512mem : X86MemOperand<"printi512mem", X86Mem512AsmOperand>; +def f32mem : X86MemOperand<"printf32mem", X86Mem32AsmOperand>; +def f64mem : X86MemOperand<"printf64mem", X86Mem64AsmOperand>; +def f80mem : X86MemOperand<"printf80mem", X86Mem80AsmOperand>; +def f128mem : X86MemOperand<"printf128mem", X86Mem128AsmOperand>; +def f256mem : X86MemOperand<"printf256mem", X86Mem256AsmOperand>; +def f512mem : X86MemOperand<"printf512mem", X86Mem512AsmOperand>; + +def v512mem : X86VMemOperand<VR512, "printf512mem", X86Mem512AsmOperand>; // Gather mem operands -def vx32mem : X86MemOperand<"printi32mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); - let ParserMatchClass = X86MemVX32Operand; } -def vy32mem : X86MemOperand<"printi32mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); - let ParserMatchClass = X86MemVY32Operand; } -def vx64mem : X86MemOperand<"printi64mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); - let ParserMatchClass = X86MemVX64Operand; } -def vy64mem : X86MemOperand<"printi64mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); - let ParserMatchClass = X86MemVY64Operand; } -def vy64xmem : X86MemOperand<"printi64mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm); - let ParserMatchClass = X86MemVY64Operand; } -def vz32mem : X86MemOperand<"printi32mem">{ - let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm); - let ParserMatchClass = X86MemVZ32Operand; } -def vz64mem : X86MemOperand<"printi64mem">{ - let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); - let ParserMatchClass = X86MemVZ64Operand; } -} +def vx32mem : X86VMemOperand<VR128, "printi32mem", X86MemVX32Operand>; +def vy32mem : X86VMemOperand<VR256, "printi32mem", X86MemVY32Operand>; +def vx64mem : X86VMemOperand<VR128, "printi64mem", X86MemVX64Operand>; +def vy64mem : X86VMemOperand<VR256, "printi64mem", X86MemVY64Operand>; +def vy64xmem : X86VMemOperand<VR256X, "printi64mem", X86MemVY64Operand>; +def vz32mem : X86VMemOperand<VR512, "printi32mem", X86MemVZ32Operand>; +def vz64mem : X86VMemOperand<VR512, "printi64mem", X86MemVZ64Operand>; // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of // plain GR64, so that it doesn't potentially require a REX prefix. @@ -424,125 +383,180 @@ def brtarget8 : Operand<OtherVT>; } -def X86SrcIdx8Operand : AsmOperandClass { - let Name = "SrcIdx8"; - let RenderMethod = "addSrcIdxOperands"; - let SuperClasses = [X86Mem8AsmOperand]; -} -def X86SrcIdx16Operand : AsmOperandClass { - let Name = "SrcIdx16"; - let RenderMethod = "addSrcIdxOperands"; - let SuperClasses = [X86Mem16AsmOperand]; -} -def X86SrcIdx32Operand : AsmOperandClass { - let Name = "SrcIdx32"; - let RenderMethod = "addSrcIdxOperands"; - let SuperClasses = [X86Mem32AsmOperand]; -} -def X86SrcIdx64Operand : AsmOperandClass { - let Name = "SrcIdx64"; - let RenderMethod = "addSrcIdxOperands"; - let SuperClasses = [X86Mem64AsmOperand]; -} -def X86DstIdx8Operand : AsmOperandClass { - let Name = "DstIdx8"; - let RenderMethod = "addDstIdxOperands"; - let SuperClasses = [X86Mem8AsmOperand]; -} -def X86DstIdx16Operand : AsmOperandClass { - let Name = "DstIdx16"; - let RenderMethod = "addDstIdxOperands"; - let SuperClasses = [X86Mem16AsmOperand]; -} -def X86DstIdx32Operand : AsmOperandClass { - let Name = "DstIdx32"; - let RenderMethod = "addDstIdxOperands"; - let SuperClasses = [X86Mem32AsmOperand]; -} -def X86DstIdx64Operand : AsmOperandClass { - let Name = "DstIdx64"; - let RenderMethod = "addDstIdxOperands"; - let SuperClasses = [X86Mem64AsmOperand]; -} -def X86MemOffs8AsmOperand : AsmOperandClass { - let Name = "MemOffs8"; - let RenderMethod = "addMemOffsOperands"; - let SuperClasses = [X86Mem8AsmOperand]; -} -def X86MemOffs16AsmOperand : AsmOperandClass { - let Name = "MemOffs16"; - let RenderMethod = "addMemOffsOperands"; - let SuperClasses = [X86Mem16AsmOperand]; -} -def X86MemOffs32AsmOperand : AsmOperandClass { - let Name = "MemOffs32"; - let RenderMethod = "addMemOffsOperands"; - let SuperClasses = [X86Mem32AsmOperand]; -} -def X86MemOffs64AsmOperand : AsmOperandClass { - let Name = "MemOffs64"; - let RenderMethod = "addMemOffsOperands"; - let SuperClasses = [X86Mem64AsmOperand]; -} -let OperandType = "OPERAND_MEMORY" in { -def srcidx8 : Operand<iPTR> { - let ParserMatchClass = X86SrcIdx8Operand; - let MIOperandInfo = (ops ptr_rc, i8imm); - let PrintMethod = "printSrcIdx8"; } -def srcidx16 : Operand<iPTR> { - let ParserMatchClass = X86SrcIdx16Operand; - let MIOperandInfo = (ops ptr_rc, i8imm); - let PrintMethod = "printSrcIdx16"; } -def srcidx32 : Operand<iPTR> { - let ParserMatchClass = X86SrcIdx32Operand; - let MIOperandInfo = (ops ptr_rc, i8imm); - let PrintMethod = "printSrcIdx32"; } -def srcidx64 : Operand<iPTR> { - let ParserMatchClass = X86SrcIdx64Operand; +// Special parser to detect 16-bit mode to select 16-bit displacement. +def X86AbsMem16AsmOperand : AsmOperandClass { + let Name = "AbsMem16"; + let RenderMethod = "addAbsMemOperands"; + let SuperClasses = [X86AbsMemAsmOperand]; +} + +// Branch targets have OtherVT type and print as pc-relative values. +let OperandType = "OPERAND_PCREL", + PrintMethod = "printPCRelImm" in { +let ParserMatchClass = X86AbsMem16AsmOperand in + def brtarget16 : Operand<OtherVT>; +let ParserMatchClass = X86AbsMemAsmOperand in + def brtarget32 : Operand<OtherVT>; +} + +let RenderMethod = "addSrcIdxOperands" in { + def X86SrcIdx8Operand : AsmOperandClass { + let Name = "SrcIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86SrcIdx16Operand : AsmOperandClass { + let Name = "SrcIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86SrcIdx32Operand : AsmOperandClass { + let Name = "SrcIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86SrcIdx64Operand : AsmOperandClass { + let Name = "SrcIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addSrcIdxOperands" + +let RenderMethod = "addDstIdxOperands" in { + def X86DstIdx8Operand : AsmOperandClass { + let Name = "DstIdx8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86DstIdx16Operand : AsmOperandClass { + let Name = "DstIdx16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86DstIdx32Operand : AsmOperandClass { + let Name = "DstIdx32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86DstIdx64Operand : AsmOperandClass { + let Name = "DstIdx64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addDstIdxOperands" + +let RenderMethod = "addMemOffsOperands" in { + def X86MemOffs16_8AsmOperand : AsmOperandClass { + let Name = "MemOffs16_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs16_16AsmOperand : AsmOperandClass { + let Name = "MemOffs16_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs16_32AsmOperand : AsmOperandClass { + let Name = "MemOffs16_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_8AsmOperand : AsmOperandClass { + let Name = "MemOffs32_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs32_16AsmOperand : AsmOperandClass { + let Name = "MemOffs32_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs32_32AsmOperand : AsmOperandClass { + let Name = "MemOffs32_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs32_64AsmOperand : AsmOperandClass { + let Name = "MemOffs32_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } + def X86MemOffs64_8AsmOperand : AsmOperandClass { + let Name = "MemOffs64_8"; + let SuperClasses = [X86Mem8AsmOperand]; + } + def X86MemOffs64_16AsmOperand : AsmOperandClass { + let Name = "MemOffs64_16"; + let SuperClasses = [X86Mem16AsmOperand]; + } + def X86MemOffs64_32AsmOperand : AsmOperandClass { + let Name = "MemOffs64_32"; + let SuperClasses = [X86Mem32AsmOperand]; + } + def X86MemOffs64_64AsmOperand : AsmOperandClass { + let Name = "MemOffs64_64"; + let SuperClasses = [X86Mem64AsmOperand]; + } +} // RenderMethod = "addMemOffsOperands" + +class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> + : X86MemOperand<printMethod, parserMatchClass> { let MIOperandInfo = (ops ptr_rc, i8imm); - let PrintMethod = "printSrcIdx64"; } -def dstidx8 : Operand<iPTR> { - let ParserMatchClass = X86DstIdx8Operand; - let MIOperandInfo = (ops ptr_rc); - let PrintMethod = "printDstIdx8"; } -def dstidx16 : Operand<iPTR> { - let ParserMatchClass = X86DstIdx16Operand; - let MIOperandInfo = (ops ptr_rc); - let PrintMethod = "printDstIdx16"; } -def dstidx32 : Operand<iPTR> { - let ParserMatchClass = X86DstIdx32Operand; - let MIOperandInfo = (ops ptr_rc); - let PrintMethod = "printDstIdx32"; } -def dstidx64 : Operand<iPTR> { - let ParserMatchClass = X86DstIdx64Operand; +} + +class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> + : X86MemOperand<printMethod, parserMatchClass> { let MIOperandInfo = (ops ptr_rc); - let PrintMethod = "printDstIdx64"; } -def offset8 : Operand<iPTR> { - let ParserMatchClass = X86MemOffs8AsmOperand; - let MIOperandInfo = (ops i64imm, i8imm); - let PrintMethod = "printMemOffs8"; } -def offset16 : Operand<iPTR> { - let ParserMatchClass = X86MemOffs16AsmOperand; - let MIOperandInfo = (ops i64imm, i8imm); - let PrintMethod = "printMemOffs16"; } -def offset32 : Operand<iPTR> { - let ParserMatchClass = X86MemOffs32AsmOperand; - let MIOperandInfo = (ops i64imm, i8imm); - let PrintMethod = "printMemOffs32"; } -def offset64 : Operand<iPTR> { - let ParserMatchClass = X86MemOffs64AsmOperand; - let MIOperandInfo = (ops i64imm, i8imm); - let PrintMethod = "printMemOffs64"; } } +def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; +def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; +def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; +def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; +def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; +def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; +def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; +def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; + +class X86MemOffsOperand<Operand immOperand, string printMethod, + AsmOperandClass parserMatchClass> + : X86MemOperand<printMethod, parserMatchClass> { + let MIOperandInfo = (ops immOperand, i8imm); +} + +def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", + X86MemOffs16_8AsmOperand>; +def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", + X86MemOffs16_16AsmOperand>; +def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", + X86MemOffs16_32AsmOperand>; +def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", + X86MemOffs32_8AsmOperand>; +def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", + X86MemOffs32_16AsmOperand>; +def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", + X86MemOffs32_32AsmOperand>; +def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", + X86MemOffs32_64AsmOperand>; +def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", + X86MemOffs64_8AsmOperand>; +def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", + X86MemOffs64_16AsmOperand>; +def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", + X86MemOffs64_32AsmOperand>; +def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", + X86MemOffs64_64AsmOperand>; def SSECC : Operand<i8> { - let PrintMethod = "printSSECC"; + let PrintMethod = "printSSEAVXCC"; let OperandType = "OPERAND_IMMEDIATE"; } +def i8immZExt3 : ImmLeaf<i8, [{ + return Imm >= 0 && Imm < 8; +}]>; + def AVXCC : Operand<i8> { - let PrintMethod = "printAVXCC"; + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def i8immZExt5 : ImmLeaf<i8, [{ + return Imm >= 0 && Imm < 32; +}]>; + +def AVX512ICC : Operand<i8> { + let PrintMethod = "printSSEAVXCC"; + let OperandType = "OPERAND_IMMEDIATE"; +} + +def XOPCC : Operand<i8> { + let PrintMethod = "printXOPCC"; let OperandType = "OPERAND_IMMEDIATE"; } @@ -599,6 +613,14 @@ def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { ImmSExti64i32AsmOperand]; } +// Unsigned immediate used by SSE/AVX instructions +// [0, 0xFF] +// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] +def ImmUnsignedi8AsmOperand : AsmOperandClass { + let Name = "ImmUnsignedi8"; + let RenderMethod = "addImmOperands"; +} + // A couple of more descriptive operand definitions. // 16-bits but only 8 bits are significant. def i16i8imm : Operand<i16> { @@ -617,6 +639,27 @@ def i64i32imm : Operand<i64> { let OperandType = "OPERAND_IMMEDIATE"; } +// 64-bits but only 8 bits are significant. +def i64i8imm : Operand<i64> { + let ParserMatchClass = ImmSExti64i8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// Unsigned 8-bit immediate used by SSE/AVX instructions. +def u8imm : Operand<i8> { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + +// 32-bit immediate but only 8-bits are significant and they are unsigned. +// Used by some SSE/AVX instructions that use intrinsics. +def i32u8imm : Operand<i32> { + let PrintMethod = "printU8Imm"; + let ParserMatchClass = ImmUnsignedi8AsmOperand; + let OperandType = "OPERAND_IMMEDIATE"; +} + // 64-bits but only 32 bits are significant, and those bits are treated as being // pc relative. def i64i32imm_pcrel : Operand<i64> { @@ -625,21 +668,15 @@ def i64i32imm_pcrel : Operand<i64> { let OperandType = "OPERAND_PCREL"; } -// 64-bits but only 8 bits are significant. -def i64i8imm : Operand<i64> { - let ParserMatchClass = ImmSExti64i8AsmOperand; - let OperandType = "OPERAND_IMMEDIATE"; -} - def lea64_32mem : Operand<i32> { - let PrintMethod = "printi32mem"; + let PrintMethod = "printanymem"; let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); let ParserMatchClass = X86MemAsmOperand; } // Memory operands that use 64-bit pointers in both ILP32 and LP64. def lea64mem : Operand<i64> { - let PrintMethod = "printi64mem"; + let PrintMethod = "printanymem"; let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); let ParserMatchClass = X86MemAsmOperand; } @@ -676,6 +713,9 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", [tglobaltlsaddr], []>; +def vectoraddr : ComplexPattern<iPTR, 5, "SelectAddr", [],[SDNPWantParent]>; +//def vectoraddr : ComplexPattern<iPTR, 5, "SelectVectorAddr", [],[SDNPWantParent]>; + //===----------------------------------------------------------------------===// // X86 Instruction Predicate Definitions. def HasCMov : Predicate<"Subtarget->hasCMov()">; @@ -706,14 +746,19 @@ def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; -def HasCDI : Predicate<"Subtarget->hasCDI()">; -def HasPFI : Predicate<"Subtarget->hasPFI()">; -def HasERI : Predicate<"Subtarget->hasERI()">; -def HasDQI : Predicate<"Subtarget->hasDQI()">; +def HasCDI : Predicate<"Subtarget->hasCDI()">, + AssemblerPredicate<"FeatureCDI", "AVX-512 CD ISA">; +def HasPFI : Predicate<"Subtarget->hasPFI()">, + AssemblerPredicate<"FeaturePFI", "AVX-512 PF ISA">; +def HasERI : Predicate<"Subtarget->hasERI()">, + AssemblerPredicate<"FeatureERI", "AVX-512 ER ISA">; +def HasDQI : Predicate<"Subtarget->hasDQI()">, + AssemblerPredicate<"FeatureDQI", "AVX-512 DQ ISA">; def NoDQI : Predicate<"!Subtarget->hasDQI()">; -def HasBWI : Predicate<"Subtarget->hasBWI()">; +def HasBWI : Predicate<"Subtarget->hasBWI()">, + AssemblerPredicate<"FeatureBWI", "AVX-512 BW ISA">; def HasVLX : Predicate<"Subtarget->hasVLX()">, - AssemblerPredicate<"FeatureVLX", "AVX-512 VLX ISA">; + AssemblerPredicate<"FeatureVLX", "AVX-512 VL ISA">; def NoVLX : Predicate<"!Subtarget->hasVLX()">; def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; @@ -736,10 +781,8 @@ def HasHLE : Predicate<"Subtarget->hasHLE()">; def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; def HasADX : Predicate<"Subtarget->hasADX()">; def HasSHA : Predicate<"Subtarget->hasSHA()">; -def HasSGX : Predicate<"Subtarget->hasSGX()">; def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; -def HasSMAP : Predicate<"Subtarget->hasSMAP()">; def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; @@ -757,6 +800,9 @@ def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, def In32BitMode : Predicate<"Subtarget->is32Bit()">, AssemblerPredicate<"Mode32Bit", "32-bit mode">; def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; +def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; +def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; +def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; @@ -773,6 +819,7 @@ def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; +def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; //===----------------------------------------------------------------------===// // X86 Instruction Format Definitions. @@ -803,6 +850,11 @@ def X86_COND_O : PatLeaf<(i8 13)>; def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE def X86_COND_S : PatLeaf<(i8 15)>; +// Predicate used to help when pattern matching LZCNT/TZCNT. +def X86_COND_E_OR_NE : ImmLeaf<i8, [{ + return (Imm == X86::COND_E) || (Imm == X86::COND_NE); +}]>; + let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; @@ -905,7 +957,7 @@ def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ // // Nop -let neverHasSideEffects = 1, SchedRW = [WriteZero] in { +let hasSideEffects = 0, SchedRW = [WriteZero] in { def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; @@ -919,12 +971,12 @@ def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; let SchedRW = [WriteALU] in { -let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in +let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", [], IIC_LEAVE>, Requires<[Not64BitMode]>; -let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in +let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", [], IIC_LEAVE>, Requires<[In64BitMode]>; @@ -934,7 +986,7 @@ def LEAVE64 : I<0xC9, RawFrm, // Miscellaneous Instructions. // -let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { +let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { let mayLoad = 1, SchedRW = [WriteLoad] in { def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], IIC_POP_REG16>, OpSize16; @@ -948,11 +1000,6 @@ def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; - -def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, - OpSize16; -def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, - OpSize32, Requires<[Not64BitMode]>; } // mayLoad, SchedRW let mayStore = 1, SchedRW = [WriteStore] in { @@ -981,16 +1028,26 @@ def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, Requires<[Not64BitMode]>; +} // mayStore, SchedRW +} + +let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0, + SchedRW = [WriteLoad] in { +def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, + OpSize16; +def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, + OpSize32, Requires<[Not64BitMode]>; +} +let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0, + SchedRW = [WriteStore] in { def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, OpSize16; def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, OpSize32, Requires<[Not64BitMode]>; - -} // mayStore, SchedRW } -let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { +let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { let mayLoad = 1, SchedRW = [WriteLoad] in { def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; @@ -1009,7 +1066,7 @@ def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], } // mayStore, SchedRW } -let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1, +let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, SchedRW = [WriteStore] in { def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; @@ -1021,22 +1078,22 @@ def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), Requires<[In64BitMode]>; } -let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in +let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; -let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in +let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], - mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in { + mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, OpSize32, Requires<[Not64BitMode]>; def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, OpSize16, Requires<[Not64BitMode]>; } let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], - mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in { + mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, OpSize32, Requires<[Not64BitMode]>; def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, @@ -1166,7 +1223,7 @@ def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), // Move Instructions. // let SchedRW = [WriteMove] in { -let neverHasSideEffects = 1 in { +let hasSideEffects = 0 in { def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), @@ -1225,62 +1282,67 @@ def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), let hasSideEffects = 0 in { -/// moffs8, moffs16 and moffs32 versions of moves. The immediate is a -/// 32-bit offset from the segment base. These are only valid in x86-32 mode. +/// Memory offset versions of moves. The immediate is an address mode sized +/// offset from the segment base. let SchedRW = [WriteALU] in { let mayLoad = 1 in { let Defs = [AL] in -def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), - "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, - Requires<[In32BitMode]>; +def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), + "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, + AdSize32; let Defs = [AX] in -def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), - "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, - OpSize16, Requires<[In32BitMode]>; +def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, + OpSize16, AdSize32; let Defs = [EAX] in -def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), - "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, - OpSize32, Requires<[In32BitMode]>; +def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, + OpSize32, AdSize32; +let Defs = [RAX] in +def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), + "mov{q}\t{$src, %rax|rax, $src}", [], IIC_MOV_MEM>, + AdSize32; let Defs = [AL] in -def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), - "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, - AdSize, Requires<[In16BitMode]>; +def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), + "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, AdSize16; let Defs = [AX] in -def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), - "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, - OpSize16, AdSize, Requires<[In16BitMode]>; +def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), + "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, + OpSize16, AdSize16; let Defs = [EAX] in -def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), - "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, - AdSize, OpSize32, Requires<[In16BitMode]>; +def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), + "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, + AdSize16, OpSize32; } let mayStore = 1 in { let Uses = [AL] in -def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), - "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, - Requires<[In32BitMode]>; +def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs offset32_8:$dst), (ins), + "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize32; let Uses = [AX] in -def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), - "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, - OpSize16, Requires<[In32BitMode]>; +def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_16:$dst), (ins), + "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, + OpSize16, AdSize32; let Uses = [EAX] in -def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), - "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, - OpSize32, Requires<[In32BitMode]>; +def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs offset32_32:$dst), (ins), + "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, + OpSize32, AdSize32; +let Uses = [RAX] in +def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs offset32_64:$dst), (ins), + "mov{q}\t{%rax, $dst|$dst, rax}", [], IIC_MOV_MEM>, + AdSize32; let Uses = [AL] in -def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), - "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, - AdSize, Requires<[In16BitMode]>; +def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs offset16_8:$dst), (ins), + "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, AdSize16; let Uses = [AX] in -def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), - "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, - OpSize16, AdSize, Requires<[In16BitMode]>; +def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_16:$dst), (ins), + "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, + OpSize16, AdSize16; let Uses = [EAX] in -def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), - "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, - OpSize32, AdSize, Requires<[In16BitMode]>; +def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs offset16_32:$dst), (ins), + "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, + OpSize32, AdSize16; } } @@ -1288,40 +1350,34 @@ def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), // and use the movabs mnemonic to indicate this specific form. let mayLoad = 1 in { let Defs = [AL] in -def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), - "movabs{b}\t{$src, %al|al, $src}", []>, - Requires<[In64BitMode]>; +def MOV8ao64 : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), + "movabs{b}\t{$src, %al|al, $src}", []>, AdSize64; let Defs = [AX] in -def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), - "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, - Requires<[In64BitMode]>; +def MOV16ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), + "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, AdSize64; let Defs = [EAX] in -def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), +def MOV32ao64 : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, - Requires<[In64BitMode]>; + AdSize64; let Defs = [RAX] in -def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src), - "movabs{q}\t{$src, %rax|rax, $src}", []>, - Requires<[In64BitMode]>; +def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), + "movabs{q}\t{$src, %rax|rax, $src}", []>, AdSize64; } let mayStore = 1 in { let Uses = [AL] in -def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), - "movabs{b}\t{%al, $dst|$dst, al}", []>, - Requires<[In64BitMode]>; +def MOV8o64a : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset64_8:$dst), (ins), + "movabs{b}\t{%al, $dst|$dst, al}", []>, AdSize64; let Uses = [AX] in -def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), - "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, - Requires<[In64BitMode]>; +def MOV16o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_16:$dst), (ins), + "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, AdSize64; let Uses = [EAX] in -def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), +def MOV32o64a : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset64_32:$dst), (ins), "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, - Requires<[In64BitMode]>; + AdSize64; let Uses = [RAX] in -def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins), - "movabs{q}\t{%rax, $dst|$dst, rax}", []>, - Requires<[In64BitMode]>; +def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs offset64_64:$dst), (ins), + "movabs{q}\t{%rax, $dst|$dst, rax}", []>, AdSize64; } } // hasSideEffects = 0 @@ -1371,17 +1427,17 @@ def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), // that they can be used for copying and storing h registers, which can't be // encoded when a REX prefix is present. let isCodeGenOnly = 1 in { -let neverHasSideEffects = 1 in +let hasSideEffects = 0 in def MOV8rr_NOREX : I<0x88, MRMDestReg, (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, Sched<[WriteMove]>; -let mayStore = 1, neverHasSideEffects = 1 in +let mayStore = 1, hasSideEffects = 0 in def MOV8mr_NOREX : I<0x88, MRMDestMem, (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV_MEM>, Sched<[WriteStore]>; -let mayLoad = 1, neverHasSideEffects = 1, +let mayLoad = 1, hasSideEffects = 0, canFoldAsLoad = 1, isReMaterializable = 1 in def MOV8rm_NOREX : I<0x8A, MRMSrcMem, (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), @@ -1395,7 +1451,7 @@ let SchedRW = [WriteALU] in { let Defs = [EFLAGS], Uses = [AH] in def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", [(set EFLAGS, (X86sahf AH))], IIC_AHF>; -let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in +let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], IIC_AHF>; // AH = flags } // SchedRW @@ -1981,42 +2037,42 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in { } let Predicates = [HasLZCNT] in { - def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E), - (X86cmp GR16:$src, (i16 0))), + def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE), + (X86cmp GR16:$src, (i16 0))), (LZCNT16rr GR16:$src)>; - def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E), + def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE), (X86cmp GR32:$src, (i32 0))), (LZCNT32rr GR32:$src)>; - def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E), + def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE), (X86cmp GR64:$src, (i64 0))), (LZCNT64rr GR64:$src)>; - def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E), + def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE), (X86cmp GR16:$src, (i16 0))), (LZCNT16rr GR16:$src)>; - def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E), + def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE), (X86cmp GR32:$src, (i32 0))), (LZCNT32rr GR32:$src)>; - def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E), + def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE), (X86cmp GR64:$src, (i64 0))), (LZCNT64rr GR64:$src)>; - def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E), - (X86cmp (loadi16 addr:$src), (i16 0))), + def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), + (X86cmp (loadi16 addr:$src), (i16 0))), (LZCNT16rm addr:$src)>; - def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E), - (X86cmp (loadi32 addr:$src), (i32 0))), + def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), + (X86cmp (loadi32 addr:$src), (i32 0))), (LZCNT32rm addr:$src)>; - def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E), - (X86cmp (loadi64 addr:$src), (i64 0))), + def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), + (X86cmp (loadi64 addr:$src), (i64 0))), (LZCNT64rm addr:$src)>; - def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E), - (X86cmp (loadi16 addr:$src), (i16 0))), + def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi16 addr:$src), (i16 0))), (LZCNT16rm addr:$src)>; - def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E), - (X86cmp (loadi32 addr:$src), (i32 0))), + def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi32 addr:$src), (i32 0))), (LZCNT32rm addr:$src)>; - def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E), - (X86cmp (loadi64 addr:$src), (i64 0))), + def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi64 addr:$src), (i64 0))), (LZCNT64rm addr:$src)>; } @@ -2097,42 +2153,42 @@ let Predicates = [HasBMI] in { } let Predicates = [HasBMI] in { - def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E), + def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE), (X86cmp GR16:$src, (i16 0))), (TZCNT16rr GR16:$src)>; - def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E), + def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE), (X86cmp GR32:$src, (i32 0))), (TZCNT32rr GR32:$src)>; - def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E), + def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE), (X86cmp GR64:$src, (i64 0))), (TZCNT64rr GR64:$src)>; - def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E), + def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE), (X86cmp GR16:$src, (i16 0))), (TZCNT16rr GR16:$src)>; - def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E), + def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE), (X86cmp GR32:$src, (i32 0))), (TZCNT32rr GR32:$src)>; - def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E), + def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE), (X86cmp GR64:$src, (i64 0))), (TZCNT64rr GR64:$src)>; - def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E), - (X86cmp (loadi16 addr:$src), (i16 0))), + def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE), + (X86cmp (loadi16 addr:$src), (i16 0))), (TZCNT16rm addr:$src)>; - def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E), - (X86cmp (loadi32 addr:$src), (i32 0))), + def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE), + (X86cmp (loadi32 addr:$src), (i32 0))), (TZCNT32rm addr:$src)>; - def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E), - (X86cmp (loadi64 addr:$src), (i64 0))), + def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE), + (X86cmp (loadi64 addr:$src), (i64 0))), (TZCNT64rm addr:$src)>; - def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E), - (X86cmp (loadi16 addr:$src), (i16 0))), + def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi16 addr:$src), (i16 0))), (TZCNT16rm addr:$src)>; - def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E), - (X86cmp (loadi32 addr:$src), (i32 0))), + def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi32 addr:$src), (i32 0))), (TZCNT32rm addr:$src)>; - def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E), - (X86cmp (loadi64 addr:$src), (i64 0))), + def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE), + (X86cmp (loadi64 addr:$src), (i64 0))), (TZCNT64rm addr:$src)>; } @@ -2167,11 +2223,11 @@ let Predicates = [HasBMI2], Defs = [EFLAGS] in { def CountTrailingOnes : SDNodeXForm<imm, [{ // Count the trailing ones in the immediate. - return getI8Imm(CountTrailingOnes_64(N->getZExtValue())); + return getI8Imm(countTrailingOnes(N->getZExtValue())); }]>; def BZHIMask : ImmLeaf<i64, [{ - return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32); + return isMask_64(Imm) && (countTrailingOnes<uint64_t>(Imm) > 32); }]>; let Predicates = [HasBMI2] in { @@ -2361,6 +2417,16 @@ let Predicates = [HasTBM] in { } // HasTBM //===----------------------------------------------------------------------===// +// Memory Instructions +// + +def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), + "clflushopt\t$src", []>, PD; +def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", []>, PD; +def PCOMMIT : I<0xAE, MRM_F8, (outs), (ins), "pcommit", []>, PD; + + +//===----------------------------------------------------------------------===// // Subsystems. //===----------------------------------------------------------------------===// @@ -2513,6 +2579,12 @@ def : MnemonicAlias<"fnstsww", "fnstsw", "att">; def : MnemonicAlias<"fucomip", "fucompi", "att">; def : MnemonicAlias<"fwait", "wait">; +def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; +def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; +def : MnemonicAlias<"xsaveq", "xsave64", "att">; +def : MnemonicAlias<"xrstorq", "xrstor64", "att">; +def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; + class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, string VariantName> @@ -2700,28 +2772,28 @@ def : InstAlias<"fnstsw" , (FNSTSW16r)>; // this is compatible with what GAS does. def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; -def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; -def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"lcall {*}$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; +def : InstAlias<"ljmp {*}$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; -def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; -def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"lcall {*}$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"ljmp {*}$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; -def : InstAlias<"call *$dst", (CALL64m i16mem:$dst), 0>, Requires<[In64BitMode]>; -def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst), 0>, Requires<[In64BitMode]>; -def : InstAlias<"call *$dst", (CALL32m i16mem:$dst), 0>, Requires<[In32BitMode]>; -def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst), 0>, Requires<[In32BitMode]>; -def : InstAlias<"call *$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; -def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"call {*}$dst", (CALL64m i64mem:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"jmp {*}$dst", (JMP64m i64mem:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"call {*}$dst", (CALL32m i32mem:$dst), 0>, Requires<[In32BitMode]>; +def : InstAlias<"jmp {*}$dst", (JMP32m i32mem:$dst), 0>, Requires<[In32BitMode]>; +def : InstAlias<"call {*}$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; +def : InstAlias<"jmp {*}$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; // "imul <imm>, B" is an alias for "imul <imm>, B, B". -def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; -def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; -def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; -def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; -def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; -def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; +def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; +def : InstAlias<"imulw {$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; +def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; +def : InstAlias<"imull {$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; +def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; +def : InstAlias<"imulq {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; // inb %dx -> inb %al, %dx def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; @@ -2745,34 +2817,34 @@ def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; // Force mov without a suffix with a segment and mem to prefer the 'l' form of // the move. All segment/mem forms are equivalent, this has the shortest // encoding. -def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; -def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; +def : InstAlias<"mov {$mem, $seg|$seg, $mem}", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; +def : InstAlias<"mov {$seg, $mem|$mem, $seg}", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; // Match 'movq <largeimm>, <reg>' as an alias for movabsq. -def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm), 0>; +def : InstAlias<"movq {$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; // Match 'movq GR64, MMX' as an alias for movd. -def : InstAlias<"movq $src, $dst", +def : InstAlias<"movq {$src, $dst|$dst, $src}", (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; -def : InstAlias<"movq $src, $dst", +def : InstAlias<"movq {$src, $dst|$dst, $src}", (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; // movsx aliases -def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; -def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; +def : InstAlias<"movsx {$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; // movzx aliases -def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; -def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; -def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; -def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; -def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; -def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; +def : InstAlias<"movzx {$src, $dst|$dst, $src}", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; // Note: No GR32->GR64 movzx form. // outb %dx -> outb %al, %dx |