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-rw-r--r--lib/Target/X86/X86InstrMMX.td142
1 files changed, 71 insertions, 71 deletions
diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index c774460..eed8843 100644
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -23,21 +23,21 @@
// MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
// MMXID - MMX instructions with XD prefix.
// MMXIS - MMX instructions with XS prefix.
-class MMXI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : I<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
-class MMXRI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : I<o, F, ops, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
-class MMX2I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
-class MMXIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasMMX]>;
-class MMXID<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : Ii8<o, F, ops, asm, pattern>, XD, Requires<[HasMMX]>;
-class MMXIS<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
- : Ii8<o, F, ops, asm, pattern>, XS, Requires<[HasMMX]>;
+class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : I<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
+class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : I<o, F, outs, ins, asm, pattern>, TB, REX_W, Requires<[HasMMX]>;
+class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : I<o, F, outs, ins, asm, pattern>, TB, OpSize, Requires<[HasMMX]>;
+class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : Ii8<o, F, outs, ins, asm, pattern>, TB, Requires<[HasMMX]>;
+class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX]>;
+class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern>
+ : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX]>;
// Some 'special' instructions
-def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
+def IMPLICIT_DEF_VR64 : I<0, Pseudo, (outs VR64:$dst), (ins),
"#IMPLICIT_DEF $dst",
[(set VR64:$dst, (v8i8 (undef)))]>,
Requires<[HasMMX]>;
@@ -107,12 +107,12 @@ let isTwoAddress = 1 in {
// MMXI_binop_rm - Simple MMX binary operator.
multiclass MMXI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
ValueType OpVT, bit Commutable = 0> {
- def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
- def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (OpVT (OpNode VR64:$src1,
(bitconvert
@@ -121,12 +121,12 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
bit Commutable = 0> {
- def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]> {
let isCommutable = Commutable;
}
- def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>;
@@ -139,12 +139,12 @@ let isTwoAddress = 1 in {
//
multiclass MMXI_binop_rm_v1i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
bit Commutable = 0> {
- def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (v1i64 (OpNode VR64:$src1, VR64:$src2)))]> {
let isCommutable = Commutable;
}
- def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst,
(OpNode VR64:$src1,(load_mmx addr:$src2)))]>;
@@ -152,14 +152,14 @@ let isTwoAddress = 1 in {
multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
string OpcodeStr, Intrinsic IntId> {
- def rr : MMXI<opc, MRMSrcReg, (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>;
- def rm : MMXI<opc, MRMSrcMem, (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(bitconvert (load_mmx addr:$src2))))]>;
- def ri : MMXIi8<opc2, ImmForm, (ops VR64:$dst, VR64:$src1, i32i8imm:$src2),
+ def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), (ins VR64:$src1, i32i8imm:$src2),
!strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
[(set VR64:$dst, (IntId VR64:$src1,
(scalar_to_vector (i32 imm:$src2))))]>;
@@ -170,58 +170,58 @@ let isTwoAddress = 1 in {
// MMX EMMS & FEMMS Instructions
//===----------------------------------------------------------------------===//
-def MMX_EMMS : MMXI<0x77, RawFrm, (ops), "emms", [(int_x86_mmx_emms)]>;
-def MMX_FEMMS : MMXI<0x0E, RawFrm, (ops), "femms", [(int_x86_mmx_femms)]>;
+def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", [(int_x86_mmx_emms)]>;
+def MMX_FEMMS : MMXI<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
//===----------------------------------------------------------------------===//
// MMX Scalar Instructions
//===----------------------------------------------------------------------===//
// Data Transfer Instructions
-def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
"movd {$src, $dst|$dst, $src}", []>;
-def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
"movd {$src, $dst|$dst, $src}", []>;
-def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (ops i32mem:$dst, VR64:$src),
+def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
"movd {$src, $dst|$dst, $src}", []>;
-def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (ops VR64:$dst, GR64:$src),
+def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src),
"movd {$src, $dst|$dst, $src}", []>;
-def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (ops VR64:$dst, VR64:$src),
+def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
"movq {$src, $dst|$dst, $src}", []>;
-def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
+def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
"movq {$src, $dst|$dst, $src}",
[(set VR64:$dst, (load_mmx addr:$src))]>;
-def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movq {$src, $dst|$dst, $src}",
[(store (v1i64 VR64:$src), addr:$dst)]>;
-def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
+def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (outs VR64:$dst), (ins VR128:$src),
"movdq2q {$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v1i64 (vector_extract (v2i64 VR128:$src),
(iPTR 0))))]>;
-def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
+def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (outs VR128:$dst), (ins VR64:$src),
"movq2dq {$src, $dst|$dst, $src}",
[(set VR128:$dst,
(bitconvert (v1i64 VR64:$src)))]>;
-def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
+def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movntq {$src, $dst|$dst, $src}",
[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
let AddedComplexity = 15 in
// movd to MMX register zero-extends
-def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
+def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
"movd {$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v2i32 (vector_shuffle immAllZerosV,
(v2i32 (scalar_to_vector GR32:$src)),
MMX_MOVL_shuffle_mask)))]>;
let AddedComplexity = 20 in
-def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
+def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
"movd {$src, $dst|$dst, $src}",
[(set VR64:$dst,
(v2i32 (vector_shuffle immAllZerosV,
@@ -283,12 +283,12 @@ defm MMX_PXOR : MMXI_binop_rm_v1i64<0xEF, "pxor", xor, 1>;
let isTwoAddress = 1 in {
def MMX_PANDNrr : MMXI<0xDF, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"pandn {$src2, $dst|$dst, $src2}",
[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
VR64:$src2)))]>;
def MMX_PANDNrm : MMXI<0xDF, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"pandn {$src2, $dst|$dst, $src2}",
[(set VR64:$dst, (v1i64 (and (vnot VR64:$src1),
(load addr:$src2))))]>;
@@ -329,13 +329,13 @@ defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d>;
let isTwoAddress = 1 in {
// Unpack High Packed Data Instructions
def MMX_PUNPCKHBWrr : MMXI<0x68, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhbw {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHBWrm : MMXI<0x68, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhbw {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1,
@@ -343,13 +343,13 @@ let isTwoAddress = 1 in {
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHWDrr : MMXI<0x69, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhwd {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHWDrm : MMXI<0x69, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhwd {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1,
@@ -357,13 +357,13 @@ let isTwoAddress = 1 in {
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHDQrr : MMXI<0x6A, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckhdq {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKH_shuffle_mask)))]>;
def MMX_PUNPCKHDQrm : MMXI<0x6A, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckhdq {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1,
@@ -372,13 +372,13 @@ let isTwoAddress = 1 in {
// Unpack Low Packed Data Instructions
def MMX_PUNPCKLBWrr : MMXI<0x60, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpcklbw {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLBWrm : MMXI<0x60, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpcklbw {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v8i8 (vector_shuffle VR64:$src1,
@@ -386,13 +386,13 @@ let isTwoAddress = 1 in {
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLWDrr : MMXI<0x61, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpcklwd {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLWDrm : MMXI<0x61, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpcklwd {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle VR64:$src1,
@@ -400,13 +400,13 @@ let isTwoAddress = 1 in {
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLDQrr : MMXI<0x62, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, VR64:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, VR64:$src2),
"punpckldq {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1, VR64:$src2,
MMX_UNPCKL_shuffle_mask)))]>;
def MMX_PUNPCKLDQrm : MMXI<0x62, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i64mem:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i64mem:$src2),
"punpckldq {$src2, $dst|$dst, $src2}",
[(set VR64:$dst,
(v2i32 (vector_shuffle VR64:$src1,
@@ -421,14 +421,14 @@ defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
// -- Shuffle Instructions
def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, i8imm:$src2),
+ (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2),
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle
VR64:$src1, (undef),
MMX_PSHUFW_shuffle_mask:$src2)))]>;
def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
- (ops VR64:$dst, i64mem:$src1, i8imm:$src2),
+ (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2),
"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set VR64:$dst,
(v4i16 (vector_shuffle
@@ -437,34 +437,34 @@ def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
MMX_PSHUFW_shuffle_mask:$src2)))]>;
// -- Conversion Instructions
-def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvtpd2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
+def MMX_CVTPD2PIrm : MMX2I<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
"cvtpd2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def MMX_CVTPI2PDrr : MMX2I<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def MMX_CVTPI2PDrm : MMX2I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"cvtpi2pd {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (ops VR128:$dst, VR64:$src),
+def MMX_CVTPI2PSrr : MMXI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
+def MMX_CVTPI2PSrm : MMXI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
"cvtpi2ps {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def MMX_CVTPS2PIrr : MMXI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
+def MMX_CVTPS2PIrm : MMXI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
"cvtps2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def MMX_CVTTPD2PIrr : MMX2I<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvttpd2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (ops VR64:$dst, f128mem:$src),
+def MMX_CVTTPD2PIrm : MMX2I<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
"cvttpd2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
+def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>;
-def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
+def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
"cvttps2pi {$src, $dst|$dst, $src}", []>;
// Extract / Insert
@@ -472,18 +472,18 @@ def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
def MMX_PEXTRWri : MMXIi8<0xC5, MRMSrcReg,
- (ops GR32:$dst, VR64:$src1, i16i8imm:$src2),
+ (outs GR32:$dst), (ins VR64:$src1, i16i8imm:$src2),
"pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
[(set GR32:$dst, (MMX_X86pextrw (v4i16 VR64:$src1),
(iPTR imm:$src2)))]>;
let isTwoAddress = 1 in {
def MMX_PINSRWrri : MMXIi8<0xC4, MRMSrcReg,
- (ops VR64:$dst, VR64:$src1, GR32:$src2, i16i8imm:$src3),
+ (outs VR64:$dst), (ins VR64:$src1, GR32:$src2, i16i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst, (v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
GR32:$src2, (iPTR imm:$src3))))]>;
def MMX_PINSRWrmi : MMXIi8<0xC4, MRMSrcMem,
- (ops VR64:$dst, VR64:$src1, i16mem:$src2, i16i8imm:$src3),
+ (outs VR64:$dst), (ins VR64:$src1, i16mem:$src2, i16i8imm:$src3),
"pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
[(set VR64:$dst,
(v4i16 (MMX_X86pinsrw (v4i16 VR64:$src1),
@@ -492,12 +492,12 @@ let isTwoAddress = 1 in {
}
// Mask creation
-def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (ops GR32:$dst, VR64:$src),
+def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),
"pmovmskb {$src, $dst|$dst, $src}",
[(set GR32:$dst, (int_x86_mmx_pmovmskb VR64:$src))]>;
// Misc.
-def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
+def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (outs), (ins VR64:$src, VR64:$mask),
"maskmovq {$mask, $src|$src, $mask}",
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>,
Imp<[EDI],[]>;
@@ -509,10 +509,10 @@ def MMX_MASKMOVQ : MMXI<0xF7, MRMDestMem, (ops VR64:$src, VR64:$mask),
// Alias instructions that map zero vector to pxor.
// FIXME: remove when we can teach regalloc that xor reg, reg is ok.
let isReMaterializable = 1 in {
- def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (ops VR64:$dst),
+ def MMX_V_SET0 : MMXI<0xEF, MRMInitReg, (outs VR64:$dst), (ins),
"pxor $dst, $dst",
[(set VR64:$dst, (v1i64 immAllZerosV))]>;
- def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (ops VR64:$dst),
+ def MMX_V_SETALLONES : MMXI<0x76, MRMInitReg, (outs VR64:$dst), (ins),
"pcmpeqd $dst, $dst",
[(set VR64:$dst, (v1i64 immAllOnesV))]>;
}
generated by cgit v1.1 at 2025-08-04 05:05:19 +0000