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Diffstat (limited to 'lib/Target/X86/X86SchedHaswell.td')
| -rw-r--r-- | lib/Target/X86/X86SchedHaswell.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index 62ba2bc..9748261 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -19,6 +19,10 @@ def HaswellModel : SchedMachineModel { let MicroOpBufferSize = 192; // Based on the reorder buffer. let LoadLatency = 4; let MispredictPenalty = 16; + + // FIXME: SSE4 and AVX are unimplemented. This flag is set to allow + // the scheduler to assign a default model to unrecognized opcodes. + let CompleteModel = 0; } let SchedModel = HaswellModel in { |