diff options
Diffstat (limited to 'lib/Target/X86/X86Subtarget.cpp')
| -rw-r--r-- | lib/Target/X86/X86Subtarget.cpp | 364 |
1 files changed, 55 insertions, 309 deletions
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index 207d0ba..989e0d6 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -11,12 +11,12 @@ // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "subtarget" #include "X86Subtarget.h" #include "X86InstrInfo.h" #include "llvm/IR/Attributes.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Host.h" @@ -24,15 +24,24 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#if defined(_MSC_VER) +#include <intrin.h> +#endif + +using namespace llvm; + +#define DEBUG_TYPE "subtarget" + #define GET_SUBTARGETINFO_TARGET_DESC #define GET_SUBTARGETINFO_CTOR #include "X86GenSubtargetInfo.inc" -using namespace llvm; +// Temporary option to control early if-conversion for x86 while adding machine +// models. +static cl::opt<bool> +X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, + cl::desc("Enable early if-conversion on X86")); -#if defined(_MSC_VER) -#include <intrin.h> -#endif /// ClassifyBlockAddressReference - Classify a blockaddress reference for the /// current subtarget according to how we should reference it in a non-pcrel @@ -153,7 +162,7 @@ const char *X86Subtarget::getBZeroEntry() const { !getTargetTriple().isMacOSXVersionLT(10, 6)) return "__bzero"; - return 0; + return nullptr; } bool X86Subtarget::hasSinCos() const { @@ -173,251 +182,16 @@ bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const { return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } -static bool OSHasAVXSupport() { -#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ - || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) -#if defined(__GNUC__) - // Check xgetbv; this uses a .byte sequence instead of the instruction - // directly because older assemblers do not include support for xgetbv and - // there is no easy way to conditionally compile based on the assembler used. - int rEAX, rEDX; - __asm__ (".byte 0x0f, 0x01, 0xd0" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); -#elif defined(_MSC_FULL_VER) && defined(_XCR_XFEATURE_ENABLED_MASK) - unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); -#else - int rEAX = 0; // Ensures we return false -#endif - return (rEAX & 6) == 6; -#else - return false; -#endif -} - -void X86Subtarget::AutoDetectSubtargetFeatures() { - unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0; - unsigned MaxLevel; - union { - unsigned u[3]; - char c[12]; - } text; - - if (X86_MC::GetCpuIDAndInfo(0, &MaxLevel, text.u+0, text.u+2, text.u+1) || - MaxLevel < 1) - return; - - X86_MC::GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX); - - if ((EDX >> 15) & 1) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } - if ((EDX >> 23) & 1) { X86SSELevel = MMX; ToggleFeature(X86::FeatureMMX); } - if ((EDX >> 25) & 1) { X86SSELevel = SSE1; ToggleFeature(X86::FeatureSSE1); } - if ((EDX >> 26) & 1) { X86SSELevel = SSE2; ToggleFeature(X86::FeatureSSE2); } - if (ECX & 0x1) { X86SSELevel = SSE3; ToggleFeature(X86::FeatureSSE3); } - if ((ECX >> 9) & 1) { X86SSELevel = SSSE3; ToggleFeature(X86::FeatureSSSE3);} - if ((ECX >> 19) & 1) { X86SSELevel = SSE41; ToggleFeature(X86::FeatureSSE41);} - if ((ECX >> 20) & 1) { X86SSELevel = SSE42; ToggleFeature(X86::FeatureSSE42);} - if (((ECX >> 27) & 1) && ((ECX >> 28) & 1) && OSHasAVXSupport()) { - X86SSELevel = AVX; ToggleFeature(X86::FeatureAVX); - } - - bool IsIntel = memcmp(text.c, "GenuineIntel", 12) == 0; - bool IsAMD = !IsIntel && memcmp(text.c, "AuthenticAMD", 12) == 0; - - if ((ECX >> 1) & 0x1) { - HasPCLMUL = true; - ToggleFeature(X86::FeaturePCLMUL); - } - if ((ECX >> 12) & 0x1) { - HasFMA = true; - ToggleFeature(X86::FeatureFMA); - } - if (IsIntel && ((ECX >> 22) & 0x1)) { - HasMOVBE = true; - ToggleFeature(X86::FeatureMOVBE); - } - if ((ECX >> 23) & 0x1) { - HasPOPCNT = true; - ToggleFeature(X86::FeaturePOPCNT); - } - if ((ECX >> 25) & 0x1) { - HasAES = true; - ToggleFeature(X86::FeatureAES); - } - if ((ECX >> 29) & 0x1) { - HasF16C = true; - ToggleFeature(X86::FeatureF16C); - } - if (IsIntel && ((ECX >> 30) & 0x1)) { - HasRDRAND = true; - ToggleFeature(X86::FeatureRDRAND); - } - - if ((ECX >> 13) & 0x1) { - HasCmpxchg16b = true; - ToggleFeature(X86::FeatureCMPXCHG16B); - } - - if (IsIntel || IsAMD) { - // Determine if bit test memory instructions are slow. - unsigned Family = 0; - unsigned Model = 0; - X86_MC::DetectFamilyModel(EAX, Family, Model); - if (IsAMD || (Family == 6 && Model >= 13)) { - IsBTMemSlow = true; - ToggleFeature(X86::FeatureSlowBTMem); - } - - // Determine if SHLD/SHRD instructions have higher latency then the - // equivalent series of shifts/or instructions. - // FIXME: Add Intel's processors that have SHLD instructions with very - // poor latency. - if (IsAMD) { - IsSHLDSlow = true; - ToggleFeature(X86::FeatureSlowSHLD); - } - - // If it's an Intel chip since Nehalem and not an Atom chip, unaligned - // memory access is fast. We hard code model numbers here because they - // aren't strictly increasing for Intel chips it seems. - if (IsIntel && - ((Family == 6 && Model == 0x1E) || // Nehalem: Clarksfield, Lynnfield, - // Jasper Froest - (Family == 6 && Model == 0x1A) || // Nehalem: Bloomfield, Nehalem-EP - (Family == 6 && Model == 0x2E) || // Nehalem: Nehalem-EX - (Family == 6 && Model == 0x25) || // Westmere: Arrandale, Clarksdale - (Family == 6 && Model == 0x2C) || // Westmere: Gulftown, Westmere-EP - (Family == 6 && Model == 0x2F) || // Westmere: Westmere-EX - (Family == 6 && Model == 0x2A) || // SandyBridge - (Family == 6 && Model == 0x2D) || // SandyBridge: SandyBridge-E* - (Family == 6 && Model == 0x3A) || // IvyBridge - (Family == 6 && Model == 0x3E) || // IvyBridge EP - (Family == 6 && Model == 0x3C) || // Haswell - (Family == 6 && Model == 0x3F) || // ... - (Family == 6 && Model == 0x45) || // ... - (Family == 6 && Model == 0x46))) { // ... - IsUAMemFast = true; - ToggleFeature(X86::FeatureFastUAMem); - } - - // Set processor type. Currently only Atom or Silvermont (SLM) is detected. - if (Family == 6 && - (Model == 28 || Model == 38 || Model == 39 || - Model == 53 || Model == 54)) { - X86ProcFamily = IntelAtom; - - UseLeaForSP = true; - ToggleFeature(X86::FeatureLeaForSP); - } - else if (Family == 6 && - (Model == 55 || Model == 74 || Model == 77)) { - X86ProcFamily = IntelSLM; - } - - unsigned MaxExtLevel; - X86_MC::GetCpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX); - - if (MaxExtLevel >= 0x80000001) { - X86_MC::GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); - if ((EDX >> 29) & 0x1) { - HasX86_64 = true; - ToggleFeature(X86::Feature64Bit); - } - if ((ECX >> 5) & 0x1) { - HasLZCNT = true; - ToggleFeature(X86::FeatureLZCNT); - } - if (IsIntel && ((ECX >> 8) & 0x1)) { - HasPRFCHW = true; - ToggleFeature(X86::FeaturePRFCHW); - } - if (IsAMD) { - if ((ECX >> 6) & 0x1) { - HasSSE4A = true; - ToggleFeature(X86::FeatureSSE4A); - } - if ((ECX >> 11) & 0x1) { - HasXOP = true; - ToggleFeature(X86::FeatureXOP); - } - if ((ECX >> 16) & 0x1) { - HasFMA4 = true; - ToggleFeature(X86::FeatureFMA4); - } - } - } - } - - if (MaxLevel >= 7) { - if (!X86_MC::GetCpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX)) { - if (IsIntel && (EBX & 0x1)) { - HasFSGSBase = true; - ToggleFeature(X86::FeatureFSGSBase); - } - if ((EBX >> 3) & 0x1) { - HasBMI = true; - ToggleFeature(X86::FeatureBMI); - } - if ((EBX >> 4) & 0x1) { - HasHLE = true; - ToggleFeature(X86::FeatureHLE); - } - if (IsIntel && ((EBX >> 5) & 0x1)) { - X86SSELevel = AVX2; - ToggleFeature(X86::FeatureAVX2); - } - if (IsIntel && ((EBX >> 8) & 0x1)) { - HasBMI2 = true; - ToggleFeature(X86::FeatureBMI2); - } - if (IsIntel && ((EBX >> 11) & 0x1)) { - HasRTM = true; - ToggleFeature(X86::FeatureRTM); - } - if (IsIntel && ((EBX >> 16) & 0x1)) { - X86SSELevel = AVX512F; - ToggleFeature(X86::FeatureAVX512); - } - if (IsIntel && ((EBX >> 18) & 0x1)) { - HasRDSEED = true; - ToggleFeature(X86::FeatureRDSEED); - } - if (IsIntel && ((EBX >> 19) & 0x1)) { - HasADX = true; - ToggleFeature(X86::FeatureADX); - } - if (IsIntel && ((EBX >> 26) & 0x1)) { - HasPFI = true; - ToggleFeature(X86::FeaturePFI); - } - if (IsIntel && ((EBX >> 27) & 0x1)) { - HasERI = true; - ToggleFeature(X86::FeatureERI); - } - if (IsIntel && ((EBX >> 28) & 0x1)) { - HasCDI = true; - ToggleFeature(X86::FeatureCDI); - } - if (IsIntel && ((EBX >> 29) & 0x1)) { - HasSHA = true; - ToggleFeature(X86::FeatureSHA); - } - } - if (IsAMD && ((ECX >> 21) & 0x1)) { - HasTBM = true; - ToggleFeature(X86::FeatureTBM); - } - } -} - void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) { AttributeSet FnAttrs = MF->getFunction()->getAttributes(); - Attribute CPUAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex, - "target-cpu"); - Attribute FSAttr = FnAttrs.getAttribute(AttributeSet::FunctionIndex, - "target-features"); + Attribute CPUAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu"); + Attribute FSAttr = + FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features"); std::string CPU = - !CPUAttr.hasAttribute(Attribute::None) ?CPUAttr.getValueAsString() : ""; + !CPUAttr.hasAttribute(Attribute::None) ? CPUAttr.getValueAsString() : ""; std::string FS = - !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : ""; + !FSAttr.hasAttribute(Attribute::None) ? FSAttr.getValueAsString() : ""; if (!FS.empty()) { initializeEnvironment(); resetSubtargetFeatures(CPU, FS); @@ -426,54 +200,23 @@ void X86Subtarget::resetSubtargetFeatures(const MachineFunction *MF) { void X86Subtarget::resetSubtargetFeatures(StringRef CPU, StringRef FS) { std::string CPUName = CPU; - if (!FS.empty() || !CPU.empty()) { - if (CPUName.empty()) { -#if defined(i386) || defined(__i386__) || defined(__x86__) || defined(_M_IX86)\ - || defined(__x86_64__) || defined(_M_AMD64) || defined (_M_X64) - CPUName = sys::getHostCPUName(); -#else - CPUName = "generic"; -#endif - } - - // Make sure 64-bit features are available in 64-bit mode. (But make sure - // SSE2 can be turned off explicitly.) - std::string FullFS = FS; - if (In64BitMode) { - if (!FullFS.empty()) - FullFS = "+64bit,+sse2," + FullFS; - else - FullFS = "+64bit,+sse2"; - } - - // If feature string is not empty, parse features string. - ParseSubtargetFeatures(CPUName, FullFS); - } else { - if (CPUName.empty()) { -#if defined (__x86_64__) || defined(__i386__) - CPUName = sys::getHostCPUName(); -#else - CPUName = "generic"; -#endif - } - // Otherwise, use CPUID to auto-detect feature set. - AutoDetectSubtargetFeatures(); - - // Make sure 64-bit features are available in 64-bit mode. - if (In64BitMode) { - if (!HasX86_64) { HasX86_64 = true; ToggleFeature(X86::Feature64Bit); } - if (!HasCMov) { HasCMov = true; ToggleFeature(X86::FeatureCMOV); } - - if (X86SSELevel < SSE2) { - X86SSELevel = SSE2; - ToggleFeature(X86::FeatureSSE1); - ToggleFeature(X86::FeatureSSE2); - } - } + if (CPUName.empty()) + CPUName = "generic"; + + // Make sure 64-bit features are available in 64-bit mode. (But make sure + // SSE2 can be turned off explicitly.) + std::string FullFS = FS; + if (In64BitMode) { + if (!FullFS.empty()) + FullFS = "+64bit,+sse2," + FullFS; + else + FullFS = "+64bit,+sse2"; } - // CPUName may have been set by the CPU detection code. Make sure the - // new MCSchedModel is used. + // If feature string is not empty, parse features string. + ParseSubtargetFeatures(CPUName, FullFS); + + // Make sure the right MCSchedModel is used. InitCPUSchedModel(CPUName); if (X86ProcFamily == IntelAtom || X86ProcFamily == IntelSLM) @@ -547,33 +290,36 @@ void X86Subtarget::initializeEnvironment() { PadShortFunctions = false; CallRegIndirect = false; LEAUsesAG = false; + SlowLEA = false; stackAlignment = 4; // FIXME: this is a known good value for Yonah. How about others? MaxInlineSizeThreshold = 128; } X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, - const std::string &FS, - unsigned StackAlignOverride) - : X86GenSubtargetInfo(TT, CPU, FS) - , X86ProcFamily(Others) - , PICStyle(PICStyles::None) - , TargetTriple(TT) - , StackAlignOverride(StackAlignOverride) - , In64BitMode(TargetTriple.getArch() == Triple::x86_64) - , In32BitMode(TargetTriple.getArch() == Triple::x86 && - TargetTriple.getEnvironment() != Triple::CODE16) - , In16BitMode(TargetTriple.getArch() == Triple::x86 && - TargetTriple.getEnvironment() == Triple::CODE16) { + const std::string &FS, unsigned StackAlignOverride) + : X86GenSubtargetInfo(TT, CPU, FS), X86ProcFamily(Others), + PICStyle(PICStyles::None), TargetTriple(TT), + StackAlignOverride(StackAlignOverride), + In64BitMode(TargetTriple.getArch() == Triple::x86_64), + In32BitMode(TargetTriple.getArch() == Triple::x86 && + TargetTriple.getEnvironment() != Triple::CODE16), + In16BitMode(TargetTriple.getArch() == Triple::x86 && + TargetTriple.getEnvironment() == Triple::CODE16) { initializeEnvironment(); resetSubtargetFeatures(CPU, FS); } -bool X86Subtarget::enablePostRAScheduler( - CodeGenOpt::Level OptLevel, - TargetSubtargetInfo::AntiDepBreakMode& Mode, - RegClassVector& CriticalPathRCs) const { +bool +X86Subtarget::enablePostRAScheduler(CodeGenOpt::Level OptLevel, + TargetSubtargetInfo::AntiDepBreakMode &Mode, + RegClassVector &CriticalPathRCs) const { Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL; CriticalPathRCs.clear(); return PostRAScheduler && OptLevel >= CodeGenOpt::Default; } + +bool +X86Subtarget::enableEarlyIfConversion() const { + return hasCMov() && X86EarlyIfConv; +} |