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-rw-r--r--lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h3
-rw-r--r--lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp3
-rw-r--r--lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h3
-rw-r--r--lib/Target/X86/X86.h7
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp9
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp17
-rw-r--r--lib/Target/X86/X86TargetMachine.h17
7 files changed, 37 insertions, 22 deletions
diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
index ecb0f4d..1e8b3ad 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
@@ -34,7 +34,8 @@ class VISIBILITY_HIDDEN X86ATTAsmPrinter : public AsmPrinter {
const X86Subtarget *Subtarget;
public:
explicit X86ATTAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V), DW(0), MMI(0) {
Subtarget = &TM.getSubtarget<X86Subtarget>();
}
diff --git a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
index 85c5471..c874849 100644
--- a/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp
@@ -25,7 +25,8 @@ using namespace llvm;
///
FunctionPass *llvm::createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose) {
+ CodeGenOpt::Level OptLevel,
+ bool verbose) {
const X86Subtarget *Subtarget = &tm.getSubtarget<X86Subtarget>();
if (Subtarget->isFlavorIntel()) {
diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
index 054cd9c..9520d98 100644
--- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
@@ -26,7 +26,8 @@ namespace llvm {
struct VISIBILITY_HIDDEN X86IntelAsmPrinter : public AsmPrinter {
explicit X86IntelAsmPrinter(raw_ostream &O, X86TargetMachine &TM,
- const TargetAsmInfo *T, unsigned OL, bool V)
+ const TargetAsmInfo *T, CodeGenOpt::Level OL,
+ bool V)
: AsmPrinter(O, TM, T, OL, V) {}
virtual const char *getPassName() const {
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 9dad017..a9ac859 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -15,6 +15,8 @@
#ifndef TARGET_X86_H
#define TARGET_X86_H
+#include "llvm/Target/TargetMachine.h"
+
namespace llvm {
class X86TargetMachine;
@@ -25,7 +27,7 @@ class raw_ostream;
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *createX86ISelDag(X86TargetMachine &TM, unsigned OptSize);
+FunctionPass *createX86ISelDag(X86TargetMachine &TM, CodeGenOpt::Level OptLevel);
/// createX86FloatingPointStackifierPass - This function returns a pass which
/// converts floating point register references and pseudo instructions into
@@ -44,7 +46,8 @@ FunctionPass *createX87FPRegKillInserterPass();
///
FunctionPass *createX86CodePrinterPass(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool Verbose);
+ CodeGenOpt::Level OptLevel,
+ bool Verbose);
/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
/// to the specified MCE object.
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 7da43e9..ceac594 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -134,7 +134,7 @@ namespace {
bool OptForSize;
public:
- explicit X86DAGToDAGISel(X86TargetMachine &tm, unsigned OptLevel)
+ explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel)
: SelectionDAGISel(tm, OptLevel),
TM(tm), X86Lowering(*TM.getTargetLowering()),
Subtarget(&TM.getSubtarget<X86Subtarget>()),
@@ -306,7 +306,7 @@ static inline bool isNonImmUse(SDNode *Root, SDNode *Def, SDNode *ImmedUse) {
bool X86DAGToDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U,
SDNode *Root) const {
- if (OptLevel == 0) return false;
+ if (OptLevel == CodeGenOpt::None) return false;
if (U == Root)
switch (U->getOpcode()) {
@@ -714,7 +714,7 @@ void X86DAGToDAGISel::InstructionSelect() {
OptForSize = F->hasFnAttr(Attribute::OptimizeForSize);
DEBUG(BB->dump());
- if (OptLevel != 0)
+ if (OptLevel != CodeGenOpt::None)
PreprocessForRMW();
// FIXME: This should only happen when not compiled with -O0.
@@ -1744,6 +1744,7 @@ SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
/// createX86ISelDag - This pass converts a legalized DAG into a
/// X86-specific DAG, ready for instruction scheduling.
///
-FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, unsigned OptLevel) {
+FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM,
+ llvm::CodeGenOpt::Level OptLevel) {
return new X86DAGToDAGISel(TM, OptLevel);
}
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index df086e8..761d098 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -180,7 +180,8 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
@@ -194,20 +195,22 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM, unsigned OptLevel) {
return false;
}
-bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Calculate and set max stack object alignment early, so we can decide
// whether we will need stack realignment (and thus FP).
PM.add(createX86MaxStackAlignmentCalculatorPass());
return false; // -print-machineinstr shouldn't print after this.
}
-bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel) {
+bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
PM.add(createX86FloatingPointStackifierPass());
return true; // -print-machineinstr should print after this.
}
bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- unsigned OptLevel,
+ CodeGenOpt::Level OptLevel,
bool Verbose,
raw_ostream &Out) {
assert(AsmPrinterCtor && "AsmPrinter was not linked in");
@@ -216,7 +219,8 @@ bool X86TargetMachine::addAssemblyEmitter(PassManagerBase &PM,
return false;
}
-bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
// On Darwin, do not override 64-bit setting made in X86TargetMachine().
@@ -245,7 +249,8 @@ bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
}
bool X86TargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- unsigned OptLevel, bool DumpAsm,
+ CodeGenOpt::Level OptLevel,
+ bool DumpAsm,
MachineCodeEmitter &MCE) {
PM.add(createX86CodeEmitterPass(*this, MCE));
if (DumpAsm) {
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index 4b4e26f..c25fc1d 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -45,7 +45,8 @@ protected:
// set this functions to ctor pointer at startup time if they are linked in.
typedef FunctionPass *(*AsmPrinterCtorFn)(raw_ostream &o,
X86TargetMachine &tm,
- unsigned OptLevel, bool verbose);
+ CodeGenOpt::Level OptLevel,
+ bool verbose);
static AsmPrinterCtorFn AsmPrinterCtor;
public:
@@ -74,14 +75,16 @@ public:
}
// Set up the pass pipeline.
- virtual bool addInstSelector(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPreRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addPostRegAlloc(PassManagerBase &PM, unsigned OptLevel);
- virtual bool addAssemblyEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPostRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addAssemblyEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool Verbose, raw_ostream &Out);
- virtual bool addCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(PassManagerBase &PM, unsigned OptLevel,
+ virtual bool addSimpleCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
bool DumpAsm, MachineCodeEmitter &MCE);
/// symbolicAddressesAreRIPRel - Return true if symbolic addresses are
generated by cgit v1.1 at 2024-07-15 15:22:29 +0000