diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/X86/X86ISelDAGToDAG.cpp | 28 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrCompiler.td | 8 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 4 |
3 files changed, 1 insertions, 39 deletions
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 88cfe10..d836c29 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -204,9 +204,6 @@ namespace { bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment); - bool SelectSingleRegAddr(SDNode *Parent, SDValue N, SDValue &Base, - SDValue &Scale, SDValue &Index, SDValue &Disp, - SDValue &Segment); bool SelectLEAAddr(SDValue N, SDValue &Base, SDValue &Scale, SDValue &Index, SDValue &Disp, SDValue &Segment); @@ -1322,31 +1319,6 @@ bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, return true; } -/// SelectSingleRegAddr - Like SelectAddr, but reject any address that would -/// require more than one allocatable register. -/// -/// This is used for a TCRETURNmi64 instruction when used to tail call a -/// variadic function with 6 arguments: Only %r11 is available from GR64_TC. -/// The other scratch register, %rax, is needed to pass in the number of vector -/// registers used in the variadic arguments. -/// -bool X86DAGToDAGISel::SelectSingleRegAddr(SDNode *Parent, SDValue N, - SDValue &Base, - SDValue &Scale, SDValue &Index, - SDValue &Disp, SDValue &Segment) { - if (!SelectAddr(Parent, N, Base, Scale, Index, Disp, Segment)) - return false; - // Anything %RIP relative is fine. - if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Base)) - if (Reg->getReg() == X86::RIP) - return true; - // Check that the index register is 0. - if (RegisterSDNode *Reg = dyn_cast<RegisterSDNode>(Index)) - if (Reg->getReg() == 0) - return true; - return false; -} - /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to /// match a load whose top elements are either undef or zeros. The load flavor /// is derived from the type of N, which is either v4f32 or v2f64. diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index 2540455..99c2b8f 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -1041,13 +1041,7 @@ def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, Requires<[In64BitMode]>; -// When calling a variadic function with 6 arguments, 7 scratch registers are -// needed since %al holds the number of vector registers used. That leaves %r11 -// as the only remaining GR64_TC register for the addressing mode. -// -// The single_reg_addr pattern rejects any addressing modes that would need -// more than one register. -def : Pat<(X86tcret (load single_reg_addr:$dst), imm:$off), +def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi64 addr:$dst, imm:$off)>, Requires<[In64BitMode]>; diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index b91f3c0..aabb442 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -543,10 +543,6 @@ def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", [tglobaltlsaddr], []>; -// Same as addr, but reject addressing modes requiring more than one register. -def single_reg_addr : ComplexPattern<iPTR, 5, "SelectSingleRegAddr", [], - [SDNPWantParent]>; - //===----------------------------------------------------------------------===// // X86 Instruction Predicate Definitions. def HasCMov : Predicate<"Subtarget->hasCMov()">; |