diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 5 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86Instr64bit.td | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 6 |
7 files changed, 14 insertions, 14 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index bdaf6b2..d62e4f4 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -133,6 +133,9 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) // ARM does not have f32 extending load. setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); + // ARM does not have i1 sign extending load. + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + // ARM supports all 4 flavors of integer indexed load / store. for (unsigned im = (unsigned)ISD::PRE_INC; im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 46aadb1..d81d5e6 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -37,9 +37,9 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM) setLoadXAction(ISD::EXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Expand); + setLoadXAction(ISD::ZEXTLOAD , MVT::i1 , Promote); - setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Expand); + setLoadXAction(ISD::SEXTLOAD , MVT::i1 , Promote); setLoadXAction(ISD::SEXTLOAD , MVT::i8 , Expand); setLoadXAction(ISD::SEXTLOAD , MVT::i16 , Expand); setLoadXAction(ISD::SEXTLOAD , MVT::i32 , Expand); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 87f101d..1c8c0a6c 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -52,9 +52,9 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); // PowerPC has an i16 but no i8 (or i1) SEXTLOAD - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand); - + setTruncStoreAction(MVT::f64, MVT::f32, Expand); // PowerPC has pre-inc load and store's. diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index df63f20..7c3e2a7 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -138,7 +138,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) // Turn FP extload into load/fextend setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); - + + // Sparc doesn't have i1 sign extending load + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); + // Custom legalize GlobalAddress nodes into LO/HI parts. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index bd1ee55..5c1ce69 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -80,7 +80,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM) if (Subtarget->is64Bit()) addRegisterClass(MVT::i64, X86::GR64RegisterClass); - setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand); + setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); // We don't accept any truncstore of integer registers. setTruncStoreAction(MVT::i64, MVT::i32, Expand); diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td index 673cc20..cdd455e 100644 --- a/lib/Target/X86/X86Instr64bit.td +++ b/lib/Target/X86/X86Instr64bit.td @@ -61,7 +61,6 @@ def i64immSExt8 : PatLeaf<(i64 imm), [{ return (int64_t)N->getValue() == (int8_t)N->getValue(); }]>; -def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>; def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; @@ -1177,8 +1176,7 @@ def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)), (TEST64rr GR64:$src1, GR64:$src1)>; -// {s|z}extload bool -> {s|z}extload byte -def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>; +// zextload bool -> zextload byte def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>; // extload diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index f5a5803..478007b 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -226,8 +226,6 @@ def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; -def sextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (sextloadi1 node:$ptr))>; -def sextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (sextloadi1 node:$ptr))>; def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; @@ -2608,9 +2606,7 @@ def : Pat<(parallel (X86cmp GR16:$src1, 0), (implicit EFLAGS)), def : Pat<(parallel (X86cmp GR32:$src1, 0), (implicit EFLAGS)), (TEST32rr GR32:$src1, GR32:$src1)>; -// {s|z}extload bool -> {s|z}extload byte -def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>; -def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>; +// zextload bool -> zextload byte def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>; def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>; def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>; 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