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-rw-r--r--lib/Target/XCore/XCoreISelLowering.cpp5
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.td4
2 files changed, 4 insertions, 5 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp
index 96b1ae7..765e618 100644
--- a/lib/Target/XCore/XCoreISelLowering.cpp
+++ b/lib/Target/XCore/XCoreISelLowering.cpp
@@ -226,9 +226,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG)
}
static inline SDValue BuildGetId(SelectionDAG &DAG) {
- // TODO
- assert(0 && "Unimplemented");
- return SDValue();
+ return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::i32,
+ DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
}
static inline bool isZeroLengthArray(const Type *Ty) {
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td
index 15e51f5..031ad87 100644
--- a/lib/Target/XCore/XCoreInstrInfo.td
+++ b/lib/Target/XCore/XCoreInstrInfo.td
@@ -750,7 +750,7 @@ def MKMSK_2r : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$size),
// getd, testlcl, tinitlr, getps, setps
def BITREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"bitrev $dst, $src",
- []>;
+ [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
def BYTEREV_l2r : _FL2R<(outs GRRegs:$dst), (ins GRRegs:$src),
"byterev $dst, $src",
@@ -790,7 +790,7 @@ def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops),
let Defs = [R11] in
def GETID_0R : _F0R<(outs), (ins),
"get r11, id",
- []>;
+ [(set R11, (int_xcore_getid))]>;
//===----------------------------------------------------------------------===//
// Non-Instruction Patterns